JPH0632057B2 - Data transmission device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device, and more particularly to a loop-shaped data transmission detection device having a loop-shaped data transmission line formed of a self-propelled shift register. It is about efficiency.

[Prior Art] Conventionally, there is an apparatus of this type shown in FIG.
FIG. 8 is a conceptual diagram showing an example of a data driven computer having a ring-shaped transmission line. In the figure, 100 is an interface for exchanging data packets inside and outside the data driven computer, and 101 to 105 are data. A merging unit for merging data packets into the ring-shaped data transmission path 150 of the drive system computer, 107 to 111 have branch lines vacant, and are provided on the branch line side only when the tab identifier of the data packet matches the branch condition. A branching unit having a function of branching a data packet, 113 is a tag management control unit for performing tag management control of the data packet, 114
Is a function processing unit for performing a function processing of the data packet, 11
5 is a program storage unit for storing a program for processing a data packet, 116 is an operand pair generation unit for generating an operand pair of a data packet, 117 is a buffer transmission line connecting the above network elements and processing elements, The double line in the figure indicates a transmission line configured using a self-propelled shift register.

Next, the operation will be described. A data packet input from the outside through the interface is usually composed of a tab identifier including a pointer address to the memory of the program storage unit and operand data for calculation, and is branched by the branch unit 108 to store the program storage. Part 115
Then, the instruction code for the operation in the function processing section 114 and the next pointer address for the program storage section 115 are fetched in the program storage section 115, and these are stored in the tab of the packet, and then the merging section 104 is entered.
To the ring-shaped transmission path 150 again at the merging unit 104. When the instruction code of this packet is a two-operand instruction, the branching unit 109 branches to the operand pair generating unit 116 to generate an operand pair with another operand. On the other hand, when the instruction code of this packet is a one-operand instruction (for example, a 1-bit shift instruction), the ring-shaped transmission line 150
Is circulated as it is and branched to the function processing unit 114 at the branching unit 110. Also in the case of a packet having a two-operand instruction code, after the operand pair is generated and stored in the data part of the packet, it reaches the function processing part 114 via the ring-shaped transmission path 150.

The packet subjected to the processing corresponding to the instruction code in the function processing unit 114 is branched again to the program storage unit 115 via the ring-shaped transmission path 150. After the execution of the program is completed by repeating such processing a predetermined number of times, the result data is output to the outside via the interface 100.

The data packet circulating around the ring-shaped transmission path 150 is composed of a plurality of words as shown in FIG. 8. Each word of word 1 and word 2 is a BOP (Beginning) separately from the data part.
of Packet) and EOP (End of Packet), and the BOP of the first word is 1, the EOP of the last word is 1, and in other cases, both BOP and EOP are 0.

FIG. 9 shows the structure of an asynchronous self-propelled shift register for connecting the network element and the processing element of FIG. 8 to form a ring-shaped transmission line. In the figure, 210 to 214 are parallel data composed of a plurality of latches. Buffer, 220-2
Reference numeral 24 denotes a C element, which outputs the same level as the input level to the C output when its two inputs X and Y match each other.
When the inputs X and Y are different, the logic circuit holds the output level before the inputs X and Y are different.

The asynchronous free-running shift register configured as described above can perform data push-in and pop-out independently and simultaneously, and the pushed-in data is automatically generated without using a shift clock. Can be shifted in the output direction.

Such an asynchronous self-propelled shift register has a data buffer function and can be used for connection between asynchronous systems. In the data driven system processor, the asynchronous self-propelled shift register is also used to process elements and networks. The elements are connected to each other to form a ring-shaped transmission line.

[Problems to be solved by the invention]

The conventional data transmission device is configured as described above,
Generally, since the processing speed of the operand pair generation unit 116 is slower than that of other functional units, when the processing amount approaches the limit of the computer, the packet that should originally go to the operand pair generation unit cannot be branched at the branching unit 109 and is ring-shaped. There is a case in which the circuit circulates on the transmission line, and in order to buffer the packet that transiently overflows in this way, an asynchronous self-propelled redundant transmission line 117 is provided.
Is provided.

However, as is clear from the above description, the provision of such a buffer transmission line is obliged to pass through this transmission line. For example, a one-operand instruction is a command because the packet transmission line length becomes long. There was a disadvantage that the execution delay time of was unnecessarily long.

The above-mentioned drawback does not cause a problem because the throughput of the system does not decrease in a high operating state where transiently overflowing packets pass through the buffer transmission line, so other commands are processed, but the data flow rate Although the number of processing operations is small and the processing amount is small, when the one-operand instruction is a critical instruction in program execution, that is, an instruction that controls the shortest execution time of the program, the execution delay time becomes apparent and the system throughput is increased. However, there was a problem that

The present invention has been made in order to solve the above-mentioned problems of the conventional one, and an object thereof is to provide a data transmission device capable of eliminating a delay when the data flow rate is small.

[Means for solving problems]

A data transmission device according to the present invention is composed of a plurality of continuously connected shift registers included in a predetermined section of a ring transmission line, a buffer unit for buffering transiently overflowing data, and the ring transmission. A bypass path that does not have a data buffer function for bypassing a predetermined section of the path, a branching unit for branching the data from the ring transmission path to the bypass path, and a merger of the data from the bypass path to the ring transmission path. And the confluence part of
There is an empty buffer in the buffer section, and only when the data density behind the merging section is low, the data is branched to the bypass path having no buffer function.

[Action]

In the present invention, the buffer section of the ring transmission line is bypassed only when there is a space in the predetermined section of the ring transmission line and the data density behind the merging portion is low, so that the data delay due to the unnecessary buffer section is eliminated. .

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a data transmission apparatus according to an embodiment of the present invention. In the figure, the same symbols as in FIG. 8 indicate the same elements. Reference numeral 150a is a buffer unit that is composed of a plurality of continuously connected shift registers included in a predetermined section of the ring-shaped transmission line 150, buffers transiently overflowing data, and 140 is a buffer of the ring-shaped transmission line 150. A bypass path for bypassing the portion 150a,
The bypass path 140 is simply formed by the branch section 112 and the merging section 1
It is a metal bus that is directly connected to 06 and does not have a data buffer function. Further, 112 is a branching unit for branching data from the ring-shaped transmission line 150 to the bypass line 140, 106 is a merging unit for merging data from the bypass line 140 with the ring-shaped transmission line 150, and 130 is the buffer unit. A vacant buffer detection unit for detecting vacancy in the ring-shaped transmission path in 150a, a data density detection unit 120 for detecting the data density behind the merging unit 106, and 121, 122, 123 which are circuits similar to the above vacant buffer detection unit. Each of them is configured to detect the vacancy of several stages of the asynchronous self-propelled shift register. Further, 124 is an AND gate, 125, 126,
127 is an inverter.

FIG. 2 shows the configuration of the empty buffer detection unit 130 of FIG. 1, which means that if there is data in at least one stage of the parallel data buffers 210 to 214, the C element 220 to
The C output of the relevant stage of 224 becomes high and one of the MOS transistors 230 to 234 of that stage is turned on, so that the detection signal BLANK becomes low. 117 is an asynchronous self-propelled shift register, 2
Reference numeral 40 is a pull-up resistor, and BOP and EOP are tag bits of the data packet.

FIG. 6 shows the configuration of the branch unit of FIG.
Reference numeral 2b is for switching the data from the input data transmission line 112a to the output data transmission line 112c or the bypass route 140 in accordance with the detection signals from the empty buffer detection unit 130 and the data density detection unit 120 shown in FIG. .

Further, FIG. 7 shows the configuration of the merging unit of FIG. 1, and the merging control unit 106c outputs the data from the input data transmission line 106a in response to the detection signals from the empty buffer detection unit 130 and the data density detection unit 120 of FIG. Data or bypass path 140
Is output to the output data transmission line 106d.

Next, the operation will be described. In this embodiment, when a large amount of data is flowing, the operation is similar to the conventional one.
Here, the ring-shaped transmission path 150 has a small amount of circulating data, and if there is no data behind the merging unit 106, all the outputs of the circuits 121 to 123 of the data density detecting unit 120 become high, and as a result, the data density detecting unit 120. Output becomes low.

Thus, the branching unit 112 branches the data to the bypass path 140 only when the output of the data density detecting unit 120 is low and the free buffer detecting unit 130 has a free space in the buffer of the buffer unit 150a. Therefore, when the data flow rate is small, the buffer section 150a is bypassed, thereby eliminating unnecessary delay. On the other hand, when the amount of data circulating in the ring-shaped transmission path 150 increases and all the outputs of the circuits 121 to 123 constituting the data density detecting unit 120 become low, the output of the data density detecting unit 120 becomes high and the bypass is bypassed. It is stopped and switched to the main line of the ring transmission line 150.

Although the merging unit is controlled by the data density detecting unit and the empty bypass detecting unit in the above embodiment, the merging unit does not necessarily have to be controlled by the both detecting units, and the function of merely merging the data. If there is

The empty buffer detector may be configured as shown in FIGS. 3 and 4. In the figure, 250-254, 280
Reference numeral 289 is an open collector type inverter.
However, if the empty buffer detector has the structure shown in FIGS. 2 and 3, the C element has the structure shown in FIGS. 5 (a), (b), (c) and (d) and the empty buffer detector is used. 4 has the structure shown in FIG. 4, the C element has the structure shown in FIG. 5 (b). In FIG. 5, 400, 401 and 404 are P channel MOS transistors, 402, 403 and 405 are N channel MOS transistors, 410 and 420 to 422 are 2-input NAND gates, 411 and 412 are negative logic 2-input NOR gates.
Reference numeral 423 is a negative logic 3-input NOR gate, and 424 is an inverter.

〔The invention's effect〕

As described above, according to the data transmission device of the present invention, it is composed of a plurality of continuously connected shift registers included in a predetermined section of the ring transmission line, and buffers transiently overflowing data. Since the data is bypassed by the bypass path that does not have the buffer function only when the buffer part has a space and the data density of the merge part is low, the unnecessary delay when the data flow rate is small is eliminated, This has the effect of reducing the time required for data circulation.

[Brief description of drawings]

FIG. 1 is a diagram showing a data transmission device according to an embodiment of the present invention, FIGS. 2 to 4 are diagrams showing the structure of an empty buffer detection unit of FIG. 1, and FIG. 5 is a C element of FIG. FIG. 6, FIG. 6 and FIG. 7 are diagrams showing the configurations of the branching portion and the merging portion of FIG. 1, respectively. FIG. 8 is a diagram showing the configuration of a conventional data transmission device, and FIG. It is a figure which shows the structure of a self-propelled shift register. In the figure, 150 is a ring-shaped transmission line, 150d is a buffer unit, 100 is an interface, 107-112 are branching units, 101-106 are merging units, 113 is a tag management control unit, 114 is a function processing unit, and 115 is a program. Storage,
Reference numeral 116 is an operand pair generation unit, 130 is an empty buffer detection unit, 120 is a data density detection unit, 140 is a bypass path, 210 to 214 are parallel data buffers (data storage means), and 220 to 224 are C elements (transfer control circuits). Is.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kozo Terada, 52-3 Yamada Nishi, Suita City, Osaka Prefecture B-803 Senri Ichijoike B-803 (72) Katsuhiko Asada 4--11, Higashi-Nambacho, Amagasaki City, Hyogo Prefecture No. (72) Inventor Hiroaki Nishikawa 1-1255-1002, Esaka-cho, Suita City, Osaka Prefecture (72) Nobufumi Komori 4-1-1, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Research Co., Ltd. In-house (72) Kenji Shima Shima 8-1-1 Tsukaguchihonmachi, Amagasaki City, Hyogo Sanryu Electric Co., Ltd. Applied Equipment Research Laboratory (72) Inoue Soichi 2613-1, Ninohonmachi, Tenri City, Nara Prefecture Sharp Co., Ltd. ULSI Laboratory (72) Inventor Satoshi Matsumoto 2613-1, Ninomoto-cho, Tenri-shi, Nara Prefecture Sharp LSI Co., Ltd. ULSI Laboratory (72) Inventor Hajime Asano 3 Yakumo Nakamachi, Moriguchi City, Osaka Prefecture 15 Matsushita Electric Industrial Co., Ltd. System Research and Development Center (72) Inventor Masahisa Shimizu 1-18-13 Hiriya, Hirakata, Hirakata, Osaka (72) Inside Central Research Laboratory, SANYO Electric Co., Ltd. (72) Hiroki Miura, Hirakata, Osaka Tani 1-18-13 Sanyo Electric Co., Ltd. Central Research Laboratory

Claims (1)

[Claims] 1. A ring formed by using a shift register composed of a plurality of data storage means and a transfer control circuit of each stage for controlling the data storage means of its own stage in response to a control signal from a transfer control circuit of an adjacent stage. A transmission line and a buffer unit, which comprises a plurality of continuously connected shift registers included in a predetermined section of the ring transmission line, buffers transiently overflowing data, and bypasses the buffer unit. A bypass path provided only in the bus line having no data buffer function, a branching unit for branching data from the ring transmission path to the bypass path, and the data from the bypass path to the transmission path. Of the ring transmission line, a data density detection unit for detecting the data density of the ring transmission line behind the merging unit, An empty buffer detection unit for detecting an empty state of the buffer unit, and branching of data to the bypass route only when the data density is equal to or less than a predetermined value provided in the branch unit and the buffer unit of the ring transmission line has an empty space. A data transmission device comprising branching and merging control means for performing the following.