JPH07262005A - Extended operand bypass system - Google Patents

Abstract

PURPOSE: To avoid the necessity from another on-chip data cache or off-chip memory by making the output port of a result register adaptive to instruction registers and operand registers by selectively connecting the output port to the input port of one of the instruction and operand registers through multiplexers. CONSTITUTION: Substitute signal processing routes 30 and 40 respectively connect the output port of an ALU 200 to the input ports of operand registers 410 and 420 through multiplexers 610 and 620 and routes 10 and 20 respectively connect the output port of a result register 500 to the input ports of the operand registers 410 and 420 through the multiplexers 610 and 620. The processing circuits 30 and 40 also connect the output port of the ALU 200 to the input ports of instruction registers 310 and 320 through multiplexers 710 and 720 and the routes 10 and 20 make the output port of the result register 500 adaptive to the instruction registers 310 and 320 by connecting the output port to the registers 310 and 320.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to microprocessors, and more particularly to pipelined microprocessors.

[0002]

2. Description of the Related Art Microprocessors, eg digital signal processors, execute coded instructions, eg computer code, in the form of object code. In this context, object code consists of machine-executable digital signals in the form of bits or instruction signals that control the operation of a digital signal processor or microprocessor. This object code or instruction signal is provided directly to the processor for command by a digital signal processor or microprocessor,
Alternatively, it can be obtained by translating a higher level computer programming language into object code instruction signals. These object code instruction signals are then decoded and executed, typically by a digital signal processor or microprocessor. Thus, typically, the steps associated with performing object code instructions include: retrieving object code instruction signals from memory, decoding these instruction signals, and retrieving those signals suitable for performing arithmetic / logical operations. Providing the processor in the form and executing the decoded instruction signal. Further, the steps of executing the decoded instruction signal include: finding the location of the addresses of the operands to be fetched, substeps to get or retrieve these operands, substeps to perform the selected operation on these operands, And substeps for storing the results of the operations performed on those operands.

One way to improve the speed performance of a microprocessor, eg a digital signal processor, is to pipeline combine these rounds of steps. An example of a pipeline coupled digital signal processor or microprocessor was granted on Aug. 11, 1992 and assigned to the assignee of the present invention, Argade.
'Multiplier Signed and Unsigned Overflow Fl
It is disclosed in US Pat. No. 5,138,570 entitled "ags". Typically, in pipelined digital signal processors or microprocessors, instructions are executed after two stages have been decoded within a pipeline of more than one stage, eg, a three stage pipeline. . In the case of a three-stage execution unit, the first stage of the three-stage execution unit or part of the pipeline is called the instruction register (IR) stage. This stage takes the decoded instruction signal for execution from the decoder unit and forms the effective memory address location of the operand to be fetched. It also forms the address of the destination memory location for storing the result of the operation to be performed on those operands. The second stage of the execution unit of the pipeline is called the operand register (OR) stage. This stage determines the operation to be performed based on the decoded instruction instruction, fetches the operands, and performs the selected arithmetic / logical operation on these operands. The third stage of the execution unit of the pipeline is referred to as the result register (RR) stage. This stage stores the result of the operation performed on these operands at the specified destination address location in memory.

In pipelined digital signal processors or microprocessors, it often happens that a subsequent or second instruction uses the result of the preceding or first instruction as an operand. In such situations, due to the nature of the pipeline, timing problems arise due to one stage in the execution unit of the pipeline completing its operation before the operation of the other stage completes. For example, in a clock cycle where a subsequent instruction controls the operation of an IR stage, the IR stage attempts to retrieve the position of the result of the previous or preceding instruction, but the result has not yet been stored. There are cases. That is, if the preceding instruction is, for example, RR
Execution in the pipeline stage before the stage may not be completed. Similarly, the instruction is in an OR stage, and the OR stage attempts to retrieve the result of the preceding instruction as an operand, but this may not yet be stored in memory. These timing issues are typically handled by the operand bypass mechanism. In this regard, for example, IEEE Compute
Hobbit's paper "A High-performance, low-power microprocessor" presented at Compcon Spring '93 , 22-26 February 1993, sponsored by the r Society,
And The 14th Annual , held June 2-5, 1987
Ditre in the minutes of Symposium on Computer Architecture
l and Mcellan's paper The Hardware Archit
ectureof the Crisp Machine ”.

[0005]

Another completely different timing situation arises, in which the instructions are temporally separated in the pipeline, and as a result the first instruction is “out of the pipeline”. Being "clocked out" results in the need for the second instruction to retrieve the result for the first instruction from memory. Therefore, a method or mechanism for handling this latter timing situation is needed.

[0006]

Briefly stated, in one embodiment of the present invention, the microprocessor comprises pipelined microprocessors. This pipelined microprocessor includes an extended operand bypass mechanism.
Similarly, the method for buspassing operands used in pipelined microprocessors according to the present invention provides an arithmetic logic unit (AL) for one executed microprocessor instruction.
U) storing the output signal of U) in a register in the result register stage of the pipelined microprocessor for at least one clock cycle period of the pipelined microprocessor.

The subject matter considered as the invention is specifically claimed by the claims of this description. However, the invention, that is, both the construction and the method of operation of the invention, and the objects, features and advantages of the invention, can be better understood by reading the following detailed description in view of the accompanying drawings. Is.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 2 is a schematic diagram of one embodiment of an execution unit of a pipelined digital signal processor (DSP) or microprocessor. As shown, the microprocessor 50 includes instruction registers (IR) 310 and 320 in the IR stage, operand registers (OR) 410, 420 in the OR stage, arithmetic logic unit (ALU) 200, and in the RR stage. It includes a result or data register (RR) 500. Although not shown in FIG. 2, each stage contains a program counter, which contains the memory address location of the instruction being executed by that stage.

As mentioned above, in a pipelined digital signal processor or microprocessor, various instructions may be in different stages of execution within the pipeline. this is,
In situations where the instructions in the pipeline are dependent on each other, for example, a subsequent or second instruction uses as an operand the result of an arithmetic / logical operation performed by the preceding or first instruction. In case it has a particularly important meaning. If a subsequent or second instruction attempts to retrieve the result of the operation performed by the first instruction from its destination memory address location before the result of the first instruction is stored therein: The second instruction will typically fetch the wrong operand. This is an example of a situation called operand hazard. The above paper “The Hardwa
As described in "ReArchitecture of the Crisp Machine", a pipelined digital signal processor or microprocessor detects this hazard condition and places the operand in an IR or OR stage based on the particular hazard condition. Uses the "bypass" operand bypass mechanism.

Rather than the second instruction requesting the result of the first instruction before the first instruction completes its execution, the first instruction causes its execution and the second instruction causes the first instruction to complete. Different timing situations occur if the operations performed by the instructions are completed before they are needed. That is, the first instruction may produce a result too sooner than the second instruction, which may essentially cause the first instruction to "clock out" from the pipeline. This different timing situation may be due to, for example, uncertain timing of fetching or decoding subsequent instructions, or conflicting microprocessor resources.
For example, this occurs when there is a collision of requests for memory. If the latter situation occurs, the result of the operation performed by the first instruction will be invalidated in the next clock cycle of the pipelined microprocessor so that it reaches the result register 500 too early. . Typically, in such situations, the result of the first instruction is written into auxiliary memory, eg, on-chip data cache, or, alternatively, off-chip memory, where the first instruction causes Loss of the result of the performed action is avoided.

FIG. 1 illustrates an extended operand bypass mechanism 100 according to the present invention. The embodiment of FIG.
Although shown as an execution unit 15 with three series of stages, the scope of the invention is not limited to only three series of stages. For example, an execution unit may include two or more stages, or the stages need not be consecutive. Furthermore, other implementations of pipelined microprocessors are possible. As shown
In addition to the instruction register (IR), operand register (OR), arithmetic logic unit (ALU), result register (RR) described above, the embodiment shown in FIG. 1 uses the IR stage instruction validity (IV) indicator 33.
0, OR stage instruction validity (IV) indicator 43
0, OR stage address register 440, RR stage address register 510, RR stage instruction validity (I
V) indicator 530, RR stage data validity (DV) indicator 52
0 and multiplexers (MUX) 610, 620, 71
Including 0 and 720. The multiplexer shown in FIG.
Although composed of parallel MUXs, the scope of the invention is not limited in this respect. That is, MUX is a serial M
It can also consist of UX, conversion from serial to parallel,
Alternatively, additional digital electronic circuitry may be used to perform the parallel to series conversion. However, due to the attendant signal processing delays, the latter approach may not be suitable for some computational or signal processing applications.

As shown, the extended operand bypass mechanism 100 includes two main signal processing paths 7.
Has 0, 80. The first and second, or left and right, corresponding digital signals or bits for each executed instruction propagate along their respective paths. That is, in the case of the route 70, it propagates to the input port of the ALU 200 via the IR 310 and OR 410, and in the case of the route 80, it propagates via the IR 320 and OR 420. Similarly, as shown, the main signal processing path 90 is
The output port of U200 is coupled to the input port of RR500. In addition to these main paths, mechanism 100 further includes a plurality of alternative signal processing paths. For example, route 3
0 and 40 are the output ports of the ALU 200, respectively.
Via MUX 610 and 620, coupled to the input ports of OR 410 and 420, and in the same way, paths 10 and 20
RR500 via MUX610 and 620, respectively
Of the OR's to the input ports of the ORs 410, 420. Further, the alternative signal processing paths 30, 40 are
200 output ports to MUX710 and 72, respectively
Coupled to the input port of IR 310, 320 via 0,
Similarly, the routes 10 and 20 are connected to the output ports of the RR 500 via the MUXs 710 and 720, respectively.
0, 320 input ports.

In the embodiment shown in FIG. 1, RR5
The connection between 00 and OR 410, 420 is R respectively.
Achieved by paths 10, 20 between the output ports of R500 and MUXs 610, 620. As shown, M
Input ports of UX610 and 620 are IR3
It is coupled to the output ports of 10 and 320, and in the same way to paths 10 and 20. Control signal port 50
And 60 are digital signal streams, for example, M
Adapted (used) to receive control signals that control the flow of bits through the UX 610, 620. Thus
This fact is signaled when a control signal is provided on the control signal ports 50, 60 and the result of the operation performed by the first instruction is held in the RR 500 for more than one clock cycle, which is then indicated by the MUX 610, 620.
Is efficiently bypassed to one of the ROs 410, 420 via one of the two, thus avoiding the need to obtain results from another on-chip data cache or off-chip memory as is conventional. Similarly, the routes 10 and 20 are
IR310 and 320 are replaced with MUX710 and 72, respectively.
0 to the output port of RR500. MU
X710, 720 is coupled to one of the two output ports of the decoding unit or portion of the microprocessor whose input port is pipeline coupled by signal paths 70, 80 in this particular embodiment, and , In the same manner, coupled to paths 10 and 20, respectively. The control signal ports 55 and 56 are MUX710 and 72, respectively.
Adapted (used) to receive control signals that control the flow of digital signals through the zeros. Pipelined D by "bypassing" the result of the first instruction from the RR stage to the IR stage instead of the OR stage.
The indirect addressing mechanism often employed by the SP or microprocessor is aided.

If the contents of RR 500 contain a bypassed result of an instruction, then RR stage data validity indicator 520 is set. Thus, the sign 52
A setting of 0 indicates that the RR 500 contains a "legitimate" digital signal. In this particular embodiment, the bypass mechanism will not complete operation until this indicator is set. As mentioned previously, in the embodiment shown in FIG. 1, the control signal ports 50, 60, 55, 65 are adapted (used) to receive control signals for the MUXs 610, 620, 710, 720, respectively. To be done. Thus, depending on the particular implementation, these control signals are made dependent, at least in part, on the state or content of the RR data validity indicator 520. If indicator 520 is set, then these MUXs know that the contents of RR 500 contain the output signals of ALU 200, and these signals are forwarded to the OR or IR stage for subsequent microprocessor instructions in the pipeline. For example, it is used as an operand for the next instruction in a series of microprocessor instructions, or as a memory address location of an operand. Thus
Instead of reading the result of the operation completed by the ALU from a destination memory address location, eg, a memory location in off-chip memory or on-chip data cache,
The result is held in the result or data register 500 for more than one clock cycle and bypassed to the register in one of the OR or IR stages, thereby providing an extended operand bypass mechanism. Similarly,
The location address of the destination memory is stored or held in the address register 510 of the RR stage for one clock cycle or more.

As shown in FIG. 1, each unit within the execution unit further includes instruction validity indicators, eg, indicators 330, 430, 530. When the contents of each of these signs are set, for example, "1"
, Or depending on the decision, by having a signal value of "0", this indicates that the particular stage is executing a valid instruction. As above, the contents of these registers will not be propagated to the next stage in the series unless the indicator for that particular stage is set. Thus, as illustrated, as the contents of the registers propagate through these stages in turn, a signal indicative of the proper execution of an instruction similarly propagates through these stages in the form of instruction validity indicators.

The control signals provided to MUXs 610, 620, 710, 720 also depend, at least in part, on the validity indicators of the various stages of the pipelined microprocessor's execution units, depending on the particular implementation. Depends on the state. For example, if the instruction validity indicator of the RR stage is not set, the control signal provided to the MUX will be RR5 to avoid operand hazards.
The output port of 00 does not give an instruction to bypass the operand. However, in some embodiments, even if the instruction validity indicator in the RR stage is not set,
That is, even if the RR stage is not executing an instruction, the bypass of the operand according to the present invention from the output port of the RR 500 is executed. However, as noted above, this particular embodiment requires that the RR stage data validity indicator be set.
Similarly, extended operand bypass in accordance with the present invention can be achieved even when the OR instruction validity indicator is not set.

Referring to the embodiment shown in FIG. 1,
The flow of digital output signals from the ALU 200 to the RR 500 is controlled based, at least in part, on the contents of the OR stage instruction validity indicator 430. For example, RR 500 includes a latch that includes an input port and an output port that receives a digital output signal or bit from the output port of ALU 200. The contents of OR are ALU
ALU, after being provided along path 70, 80 to
Provide a digital output signal to be stored in R500. Indicator 430 then forwards its contents to indicator 530 because the contents of the OR are currently "not valid" and RR.
Notify that the contents of 500 are valid. Thus
The contents of the indicator 430, which indicates that the OR stage is "illegal", prevents the latch from getting more digital output signals from the ALU 200. As a result of this, RR5
It is avoided that the contents of 00 are overwritten (overridden) by subsequent digital output signals generated by ALU 200 based on the current "illegal" contents of the OR.

Similarly, in some embodiments, the extended operand bypass mechanism according to the present invention is at least partially based on the output of a comparator, eg, equality comparator 910, 920, 930, 940 shown in FIG. It is triggered or led by a signal. These comparators compare the destination memory address location for the result of the microprocessor instruction with the memory address location for the operand of the next or subsequent microprocessor instruction. If these memory locations match or correspond, then the first or previous instruction may "clock out" from the pipeline, as described above. Thus, in this particular embodiment, the control signal provided to the MUX is made to depend, at least in part, also on the output signal of this comparator, and thus the present invention, as described below. The extended operand bypass mechanism according to is activated. Similarly, as a result, the operation of reading the operand from the memory by the logic circuit is omitted. Alternatively, if these memory locations do not match, then the result of the first instruction need not be bypassed, as described above.

As suggested above, the location address of the destination memory for the result of the operation performed by the microprocessor instruction is typically IR.
Although generated in stages, the scope of the invention is not limited thereby. To describe the embodiment shown in FIG. 1, the OR stage address register 440 uses the IR 310.
To receive the contents of. Similarly, as shown, in this embodiment, the contents of register 440 is the comparator,
For example, provided to equality comparators 910, 920, which compare the destination address stored in OR stage address register 440 with the current contents of IR 310, 320 for that clock cycle. Similarly, on the next clock cycle, register 44
The contents of 0 are provided to the RR stage address register 510,
As a result, here again, the comparison with the contents of RI 310, 320 for this next clock cycle is performed by equality comparators 930, 940 as shown in FIG. Thus, for each clock cycle, the IR31
The contents of 0, 320 are compared with the address locations in the destination memory of the OR and RR stages. Thus, this technique uses IR3
It can be seen that since 10, 320 includes memory address locations, it also handles complex indirect addressing.

As alluded to above, FIG. 1 illustrates the bypass mechanism employed to avoid operand hazards. For example, as shown, paths 30, 40
Outputs the output ports of the ALU200 to the MUXs 610 and 620.
To the input port of. Control signal port 50, 60
Therefore receives the respective MUX control signals and selects the digital signals provided to the MUXs 610, 620 by paths 30, 40, respectively, MUXs 610, 620
To the output port of. As a result, the output signal of ALU 200 is directly bypassed to one of the operand registers 410, 420, thereby avoiding hazards. To this extent, one or more externally generated clocks provide the appropriate clock pulses or timing signals to regulate or control the operation of different pipeline stages, including execution unit stages. Understand that you can synchronize.

The extended operand bypass mechanism, eg, the embodiment shown in FIG. 1, provides several benefits. For example, an increase in speed or performance of the DSP or microprocessor is achieved because the clock cycles associated with reading the results of the first or preceding DSP or microprocessor instructions from memory are avoided. Similarly, as mentioned above, as a result, clock cycles associated with the use of off-chip memory or on-chip data caches are eliminated, so that they are used to complete the operations performed by this instruction. The overall power is reduced. This power savings is difficult to quantify because it depends, in part, on the frequency with which the situations encountered by the extended operand bypass mechanism according to the present invention occur. However, this savings is 2
It is considered to be in the order of 0 to 10%. This is especially
This is especially important in environments where power consumption is an important practical consideration, such as in mobile applications.

For example, a method for performing operand bypass within the execution stages of a pipelined microprocessor that executes microprocessor instructions as in the embodiment shown in FIG. 1 is accomplished as follows. To be done. As mentioned previously, the instructions of the two microprocessors may be at different stages of execution within the pipeline. In some situations, the first or previous instruction may complete execution at least two clock cycles or more clock cycles of the second instruction. To this end, the output signal of the ALU, eg, ALU 200 in FIG. 1, is stored for the instruction thus executed for one clock cycle period or more of the pipelined microprocessor in the RR stage.

The output signal held or stored for more than one clock cycle period is then transferred into a register in one of the IR or OR stages. Thus, as mentioned above,
Instructions or operations for reading the output signal from its destination memory address location in the off-chip memory or on-chip data cache are canceled or omitted. This stored output signal is a MUX, eg, FIG.
Via one of the MUXs 610, 620, 710 or 720 shown in FIG. This stored output signal is O
If transferred to a register in the R stage, the output signal so transferred is then used as an operand for another instruction that is executed after the executed instruction. In the case of the embodiment shown in FIG. 1, the instruction executed after this executed instruction is executed immediately after this executed instruction, although the scope of the invention is limited in this respect. Not a thing.
In some situations, even if there is an intervening instruction between the first instruction that produces a result and the second instruction that uses the result of the first instruction as an operand, the present invention It is possible to achieve extended operand bypass according to Such a situation arises, for example, when the intricate instruction does not store the result in memory. Similarly,
If the stored output signal is transferred to a register in the IR stage, then the output signal thus transferred is used as the memory address location of the operand for another instruction executed immediately after its executed instruction. To be done.

As mentioned above, in the embodiment shown in FIG. 1, if the output signal of the ALU for the executed instruction is stored in the RR stage, eg, RR500 of FIG. 1, the RR stage data validity. Sign, eg sign 43
0 is set. Similarly, the step of transferring the stored output signal to one register in the IR or OR stage is a MUX, eg MUX 610, 6 shown in FIG.
20.710 or 720, the step of transferring the stored output signal further comprises controlling the MUX based at least in part on the set state of the RR data indicator. Including.

As previously mentioned, the extended operand bypass mechanism according to the present invention compares the destination memory address location of the result of the first or preceding instruction with the memory address location of the operand of the subsequent instruction. It is started by This step, as described for the embodiment of FIG.
It is performed prior to or in parallel with the step of storing the U output signal in the result register for one clock cycle period or more. It will be appreciated that the contents of the result register, eg, RR 500 of FIG. 1, are written into memory regardless of whether extended operand bypass in accordance with the present invention occurs.

Although not shown in FIG. 1, in some particular cases it is required to avoid operand bypass. For example, in the case of character manipulation instructions, the microprocessor operates on a subdivided or selected portion of an operand, so that only the subdivided portion of the result stored in register 500 is "valid". . In this particular situation,
In order to successfully accomplish the required character operation, a particular operation for reading the result stored in the result register, eg, RR 500 of FIG. 1, from memory after it has been written into the memory. Is required to be achieved.
Similarly, if the executed instruction is a context switch instruction, it is better not to perform operand bypass. In this case, the instructions that enter the pipeline to be executed after the context switch instruction comprise a second instruction routine or set of instructions. If this situation occurs,
The second set of instructions produces instruction signals that are operationally or logically corresponding to the operands in the first or preceding set of instructions.
It is included although there is no intention to specify these operands. Therefore, after the context switch instruction,
So that the instructions in the second set refer to the results of the instructions in the first set, even though this instruction in the second set actually refers to the contents of a particular memory address location. May look like. Therefore, bypass should be avoided in such situations. In these two above mentioned situations, operand bypass is avoided, for example by preventing the data validity indicator 520 from being set.

While only some features of the present invention have been shown and described herein, many modifications, alternatives, alterations or equivalents will become apparent to those skilled in the art. Therefore, the claims are to be understood to include all such modifications and changes as fall within the true spirit of the invention.

[Brief description of drawings]

FIG. 1 is a schematic diagram of one embodiment of an extended operand bypass mechanism according to the present invention.

FIG. 2 is a schematic diagram of one embodiment of an execution unit or portion of a pipelined digital signal processor or microprocessor.

[Explanation of symbols]

 50 Microprocessor 310, 320 Instruction register 410, 420 Operand register 200 Operation unit 500 Data register

Claims (10)

[Claims] 1. A microprocessor, the microprocessor comprising: two instruction registers (IR) each having one input port and one output port.
Instruction register (IR) stages including (eg, 310, 320); Operand register (O) including two operand registers (OR) (eg, 410, 420) each having one input port and one output port.
R) stage; arithmetic logic unit (ALU) (for example, 20)
0); and a result register (RR) stage including a result register (RR) having one input port and an output port (eg 500);
200) are combined to form a pipelined microprocessor; said pipelined microprocessor being a multiplexer (eg 7
10, 720, 610, 620), and the multiplexer connects the output port of the RR (eg, 500) to at least one register (eg, 310, 320, 410, 420) of the IR and OR stages. A microprocessor adapted (used) to selectively couple to at least one input port. 2. The microprocessor of claim 1, wherein the RR stage further comprises an RR stage data validity indicator register (eg 520) and an RR stage address register (eg 510). 3. The multiplexer (eg 71
0, 720, 610, 620) is, at least in part, the RR stage data validity indicator register (eg,
520); wherein the RR (eg, 500) is adapted (used) to store the output signal of the ALU (eg, 200) for one or more clock cycle periods of the microprocessor. The microprocessor according to claim 2, wherein 4. The RR stage includes an RR stage instruction validity indicator register (eg, 530) and the multiplexer (eg, 710, 720, 61).
0,620) is further at least partially defined by the aforementioned R
R-stage instruction validity indicator register (eg,
The microprocessor of claim 3 depending on 530). 5. The at least one register (eg, 310, 320, 410, 420) is the at least one register of the OR stage (eg, 410, 42).
0); said multiplexer (eg, 610,
620) is an output port of the RR (eg, 500) and at least one register (eg, of the IR stage) (eg,
10. The output port of a device (310, 420) is adapted (used) to selectively couple to an input port of at least one register (eg, 410, 420) of the OR stage. Microprocessor. 6. The pipelined microprocessor includes a decoder unit before the IR stage; the at least one register (eg, 31).
0, 320, 410, 420) includes at least one register (eg, 310, 320) of said IR stage; said multiplexer (eg, 710, 720).
Has at least one of said RR (eg 500) output port and said decoder unit output port said at least one register (eg 3) of said IR stage.
10. The microprocessor of claim 1 adapted (used) to selectively couple to an input port of 10,320). 7. The RR (eg 500) comprises a latch and the OR stage comprises an OR stage instruction validity indicator register (eg 430); the latch comprises the ALU (eg 200). 6. The micro of claim 5, adapted (received) to receive an output signal from an output port of said at least partially in response to said OR stage instruction validity indicator register (eg, 430). Processor. 8. A method for bypassing operands in a pipelined microprocessor for executing a microprocessor instruction, said pipelined microprocessor comprising an arithmetic logic unit (ALU) (ALU). For example, 200) and a result register (RR) stage; the method described above outputs the output signal of an ALU (eg 200) for one executed microprocessor instruction into a register (eg 500) in the RR stage. Storing at least one clock cycle period of at least one pipelined microprocessor. 9. The pipeline coupled microprocessor further comprises an instruction register (I
R) stage and an operand register (OR) stage; and further store said stored output signal essentially with said IR stage and O stage.
9. Transferring to a register (eg, 310, 320, 410, 420) in one stage selected from the group of R stages is included.
the method of. 10. A register (eg, 310, 320, 4) in one stage selected from the group consisting essentially of the IR and OR stages of the stored output signal.
10, 420) to output the stored output signal to the MUX (eg, 710, 720, 610, 62).
0) Method according to claim 9, characterized in that it comprises the step of transferring via 0).