JPH04319598A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To remarkably reduce the current consumption of a stand-by state by deciding so that voltage pulled up by this resistor is lower than the source voltage of a peripheral circuit in a semiconductor memory with four transistors two resistors type SRAM cell. CONSTITUTION:As compared to a conventional four transistors two resistors type cell, this memory is provided with two diodes D1, D2 for preventing back flow so that no current flows backward when potential at A, B are higher than the voltage VCCT of the cell. further, instead of the level of the source voltage VCC of a conventional semiconductor, the memory is constituted so as to have the voltage level independent of the VCC as the voltage VCCT. Then, the memory is constituted so that since the voltage generator of the VCCT has a temperature detector, in the case of high temperature where leak current is increased and in the case of low temperature where the resistance of a high resistance poly-silicon film is high, the voltage is outputted respectively, in normal temperature, the voltage is suppressed to low. Thus, the current consumption of the stand-by state is drastically reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and in particular to an SRAM that enables low power consumption.

In recent years, the capacity of semiconductor memory devices has increased significantly, and along with this, there is a strong demand for lower power consumption.

0003

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional SRAM cell. In the figure, R3 and R4 are resistors made of high-resistance polycrystalline silicon (poly-Si) films.

Conventionally, a 4-transistor, 2-resistance type SRAM
In the case of , the resistances R3 and R4 of the high-resistance poly-Si film of the cell
The voltage that pulls up is the power supply voltage (VCC) of the semiconductor device.
), and in order to reduce power consumption and reduce the voltage applied to the high-resistance poly-Si film, the following steps are required:
It was necessary to lower it in conjunction with VCC.

[0005] However, simply keeping VCC low has disadvantages such as insufficient transistor capacity and sense amplifiers that determine L and H levels not operating correctly.

[0006]

[Problem to be solved by the invention] VCC is always applied to the high-resistance poly-Si film, and the current flowing during standby is the sum of its memory capacity.

[0007] Therefore, by lowering the voltage applied to the high-resistance poly-Si film, it is possible to reduce power consumption during standby. Furthermore, at low temperatures, the resistance value of the high-resistance poly-Si film increases and the cell current itself decreases;
The holding current of the SRAM cell also decreases proportionally, resulting in poor data retention due to junction leakage due to crystal defects and the like.

In this mode, by lowering the pull-up voltage of the high-resistance poly-Si film even at room temperature, the holding current of the cell can be reduced and the cell can be rendered defective. Furthermore, at high temperatures, cell leakage current increases, so the holding current decreases, just as at low temperatures.

At this time, if the resistance of the contact is large,
Furthermore, high-temperature data retention may be impaired due to disconnection of the high-resistance poly film. In this mode as well, by lowering the pull-up voltage of the high-resistance poly-Si film at room temperature, the holding current of the cell can be reduced and the cell can be rendered defective.

In view of the above points, it is an object of the present invention to reduce power consumption during standby and to reject high-temperature and low-temperature defects at room temperature regarding the configuration of the power supply voltage of a semiconductor memory device.

[0011]

[Means for Solving the Problem] FIG. 1 shows an SRAM of the present invention.
FIG. 3 is a circuit configuration diagram of a cell. In the figure, R1, R2
is the resistance of a high-resistance poly-Si film, and D1 and D2 are diodes for preventing backflow.

The above problem is that in the case of a 4-transistor, 2-resistance type SRAM cell, the voltage (VCCT) applied to the resistors R1 and R2 made of a high-resistance poly-Si film of the cell is
It would be better if it could be separated from the level and controlled separately and independently.

In the case of a 4-transistor, 2-resistance type SRAM, the voltage VCCT applied to the resistances R1 and R2 of the poly-Si film of the cell is normally set to the VCC level at the lead voltage.
Execute the write.

[0014] This is the same as the conventional SRAM operation, but when the battery backup mode is entered, the V
The cell current can be reduced by lowering the CCT voltage. Additionally, when testing, it is possible to apply VCCT from the outside, making it possible to freely set the VCCT voltage during writing.

That is, an object of the present invention is to provide a 4-transistor, 2-resistance type S
In a semiconductor memory device having a RAM cell, the voltage pulled up by the resistor is set to be lower than the power supply voltage of the peripheral circuit. This is achieved by having a power supply output circuit that determines the voltage level (VCCT) of the original cell.

[0016]

[Operation] In the SRAM cell using the present invention, when the voltage of VCCT is set to 2.5V during standby, the standby current is simply halved compared to the case of a conventional 5V single power supply.

Furthermore, by keeping the voltage at the time of writing low, it becomes possible to make the minute leak mode, which would not be considered defective unless the temperature is low or high, become defective at room temperature.

[0018]

[Example] Figure 1 is a circuit diagram of an SRAM cell according to the present invention.
FIG. 2 is a block diagram of the VCCT generation circuit of the present invention.

An embodiment of the present invention will be explained with reference to FIGS. 1 and 2. Compared to the conventional 4-transistor 2-resistance cell shown in FIG.
Two diodes D1 for current backflow prevention are installed to prevent the current from flowing backwards due to the potential at A and B becoming higher than VCCT.
, D2 are added.

[0020] Also, instead of the conventional VCC level,
The circuit has a voltage level called VCCT that is independent of VCC. As shown in the block diagram of Figure 3, the voltage generation circuit of the VCCT has a temperature detection circuit, which detects temperature at high temperatures where the leakage current increases and at low temperatures where the resistance of the high-resistance poly-Si film increases. , each outputs a high voltage, and is designed to keep the voltage low at room temperature.

[0021] Reduction of standby current (ISB) will now be described. In the case of a conventional SRAM cell, as shown in FIG. 3, the pull-up voltage of the high resistance poly-Si films R3 and R4 is the same as VCC.

Therefore, the current consumption during standby is determined by the voltage of VCC. Currently, a method called auto power down is used to reduce standby current.

This is a function that automatically lowers the voltage of VCC when no RAM operation is performed for a certain period of time. In the present invention, in order to compensate for the drawback that the peripheral circuits stop operating if the entire VCC is lowered, by applying voltages to the peripheral circuits and memory cells independently, the cell part can be held at a smaller voltage. This is what was used.

Furthermore, in order to set a more efficient voltage level, a temperature factor can be used to generate a voltage level corresponding to the ambient temperature. SRAM
As the temperature increases, lateral leakage increases due to a decrease in the threshold value of the field transistor, etc., and the current value of the standby current increases.

Furthermore, when the standby current is at a low temperature, the resistance of the high-resistance poly-Si film increases, so even a small leak such as a crystal defect mode may cause data to be inverted. In order to solve these problems, the present invention makes it possible to determine an appropriate voltage for each device based on temperature characteristics during the test process, and to write the data into the ROM in the temperature detection circuit.

[0026] This makes it possible to determine optimal voltage conditions for each device. Next, we will discuss how to reject low-temperature and high-temperature defects in room-temperature tests. As mentioned in the previous explanations, characteristic defects such as an increase in leakage current in high-temperature tests and an increase in leakage current in low-temperature tests are caused by
This occurs as a data retention defect among test items.

As shown in FIG. 3, this is a defect in which the voltage levels of C and D decrease due to the increase in leakage current, and the data is eventually inverted. As shown in the block diagram of FIG. 3, an external application circuit for VCCT is provided, which allows the voltage of VCCT to be applied directly from the tester.

Since this is originally a mode in which a defect occurs when the voltage level decreases, by reducing the write voltage from the beginning, it becomes possible to reproduce the defect more quickly. In this way, by setting VCCT to the minimum voltage when writing, it becomes possible to determine that a mode that would conventionally be considered defective at low or high temperatures is defective at room temperature.

[0029]

[Effects of the Invention] As explained above, according to the present invention, the current consumption in the standby state can be significantly reduced.

[0030] Furthermore, it is now possible to test at room temperature a mode that conventionally failed only in low-temperature tests and high-temperature tests, and significant cost reductions such as reduction in test time and elimination of testing steps can be expected.

[Brief explanation of the drawing]

[Figure 1] Circuit configuration diagram of the SRAM cell of the present invention

[Figure 2
] VCCT generation circuit block diagram of the present invention

[Figure 3]
Circuit diagram of conventional SRAM cell

[Explanation of symbols]

Claims (3)

[Claims] 1. A semiconductor memory device characterized in that the power supply voltage of a memory cell is configured to be lower than the power supply voltage of a peripheral circuit. 2. A semiconductor memory device having a four-transistor, two-resistance type SRAM cell, wherein a voltage pulled up by the resistor is set lower than a power supply voltage of a peripheral circuit. [Claim 3] A temperature detection circuit that detects the chip temperature, and a cell voltage level (VCCT) based on the detected temperature.
3. The semiconductor memory device according to claim 1, further comprising a power supply output circuit that determines the output voltage.