JPH04318961A - Lead frame, manufacture thereof and semiconductor ic device using the same - Google Patents

Lead frame, manufacture thereof and semiconductor ic device using the same

Info

Publication number
JPH04318961A
JPH04318961A JP3084971A JP8497191A JPH04318961A JP H04318961 A JPH04318961 A JP H04318961A JP 3084971 A JP3084971 A JP 3084971A JP 8497191 A JP8497191 A JP 8497191A JP H04318961 A JPH04318961 A JP H04318961A
Authority
JP
Japan
Prior art keywords
lead
wire
plating layer
bonding
inner lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3084971A
Other languages
Japanese (ja)
Inventor
Hiroshi Watanabe
宏 渡辺
Susumu Okikawa
進 沖川
Hiroshi Mikino
三木野　博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3084971A priority Critical patent/JPH04318961A/en
Publication of JPH04318961A publication Critical patent/JPH04318961A/en
Pending legal-status Critical Current

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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve junction strength between a coated wire and an inner lead and improve reliability from the view point of its junction. CONSTITUTION:A plated layer 7 having a rougher surface than in the past is formed on the surface of an inner lead 5b of a lead frame 1, with which a coated wire 8 where the surface of a metal wire 8a is coated with a coating insulating film 8b. Then, when the coated wire 8 is to be joined with the inner lead 5b, the coated insulating film 8b of the coated wire 8 can be broken by the unevenness of the surface of the plated layer 7.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は、リードフレーム、その
製造方法およびそれを用いた半導体集積回路装置技術に
関し、特に、被覆ワイヤが接合されるリードフレームお
よび被覆ワイヤによって半導体チップとリードフレーム
とを接続する半導体集積回路装置に適用して有効な技術
に関するものである。TECHNICAL FIELD The present invention relates to a lead frame, a method for manufacturing the same, and a semiconductor integrated circuit device technology using the lead frame, and more particularly to a lead frame to which coated wires are bonded, and a semiconductor chip and a lead frame are connected by the coated wires. The present invention relates to techniques that are effective when applied to semiconductor integrated circuit devices to be connected.

【０００２】0002

【従来の技術】半導体チップの電極を外部に引き出す技
術として、ワイヤボンディング方式がある。2. Description of the Related Art There is a wire bonding method as a technique for drawing out the electrodes of a semiconductor chip to the outside.

【０００３】ワイヤボンディング方式は、半導体チップ
のボンディングパッドと、リードフレームのインナーリ
ードとを金属ワイヤによって接続し、半導体チップの電
極を外部に引き出す技術である。The wire bonding method is a technique in which bonding pads of a semiconductor chip and inner leads of a lead frame are connected with metal wires, and electrodes of the semiconductor chip are brought out to the outside.

【０００４】ところで、従来、リードフレームのインナ
ーリード表面には、金属ワイヤとの接着性を良好にさせ
る観点からメッキが施されている。[0004] Conventionally, the inner lead surface of a lead frame has been plated to improve adhesion to metal wires.

【０００５】そのメッキの特性は、メッキ処理時の条件
によって種々変化するのが普通であるが、通常のワイヤ
ボンディング技術では、その特性が大幅に変化してもボ
ンダビリィティに影響ないので、メッキの特性をさほど
重視する必要もなかった。[0005] The characteristics of the plating usually change variously depending on the conditions during the plating process, but with normal wire bonding technology, even if the characteristics change significantly, bondability is not affected, so the plating There was no need to place much emphasis on the characteristics of

【０００６】そこで、従来は、生産性を考慮して、短時
間でメッキ処理が完了するように、メッキ液、メッキ温
度およびメッキ電流等のようなメッキ条件を設定してい
た。Conventionally, in consideration of productivity, plating conditions such as the plating solution, plating temperature, and plating current have been set so that the plating process can be completed in a short time.

【０００７】この場合、インナーリードの表面には、表
面の凹凸の少ない滑らかな光沢のあるメッキ層が形成さ
れていた。[0007] In this case, a smooth and glossy plating layer with few surface irregularities was formed on the surface of the inner lead.

【０００８】なお、ワイヤボンディング技術については
、例えば日刊工業新聞社、昭和６２年９月２９日発行、
「ＣＭＯＳデバイスハンドブック」Ｐ２８６〜Ｐ２８７
に記載があり、熱圧着法、超音波法およびそれらを組み
合わせた方法等、ワイヤボンディングの手法について説
明されている。[0008] Regarding wire bonding technology, for example, Nikkan Kogyo Shimbun, published September 29, 1988,
"CMOS Device Handbook" P286-P287
describes wire bonding techniques such as thermocompression bonding, ultrasonic bonding, and combinations thereof.

【０００９】[0009]

【発明が解決しようとする課題】ところで、近年、半導
体集積回路装置においては、集積度および回路機能の向
上等に伴ってリード本数が増加する傾向にある。In recent years, the number of leads in semiconductor integrated circuit devices has tended to increase as the degree of integration and circuit functions have improved.

【００１０】しかし、ワイヤボンディング方式を用いる
半導体集積回路装置におけるリード本数の増加は、隣接
する金属ワイヤの間隔を狭めるので、それらの接触によ
る短絡不良の危険性を増大させつつある。However, the increase in the number of leads in semiconductor integrated circuit devices using the wire bonding method narrows the distance between adjacent metal wires, increasing the risk of short circuit failures due to contact between them.

【００１１】そこで、そのような隣接金属ワイヤ同士の
短絡不良を回避する観点等から、隣接する金属ワイヤ同
士が接触しても短絡しないように、金属ワイヤの表面に
絶縁膜を被覆させる被覆ワイヤボンディング技術の開発
が進められている。[0011] Therefore, from the viewpoint of avoiding such short-circuit failures between adjacent metal wires, coated wire bonding is used in which the surfaces of metal wires are coated with an insulating film to prevent short-circuits even if adjacent metal wires come into contact with each other. The technology is being developed.

【００１２】被覆ワイヤボンディング技術においては、
被覆ワイヤをインナーリードに接合する際に金属ワイヤ
表面の絶縁膜を破ることにより、被覆ワイヤの金属表面
を露出させて、その露出部分だけで被覆ワイヤとインナ
ーリードとを接合する。In coated wire bonding technology,
When the covered wire is bonded to the inner lead, the insulating film on the surface of the metal wire is broken to expose the metal surface of the covered wire, and the covered wire and the inner lead are bonded using only the exposed portion.

【００１３】このため、その接合の際の金属ワイヤ表面
の絶縁膜の破れ方が、ワイヤ／リード間の良好なボンダ
ビリィティを得る上で重要な要素となっている。[0013] Therefore, the way the insulating film on the surface of the metal wire breaks during bonding is an important factor in obtaining good bondability between the wire and the lead.

【００１４】ところが、従来の通常のワイヤボンディン
グ方式で用いられていたリードフレームでは、そのイン
ナーリード表面に形成されたメッキ層表面の凹凸が小さ
すぎて、被覆ワイヤをそのインナーリードに接合する際
に、金属ワイヤ表面の絶縁膜を充分破らせることができ
ない。However, in the lead frame used in the conventional wire bonding method, the unevenness of the plating layer formed on the surface of the inner lead is too small, making it difficult to bond the coated wire to the inner lead. , the insulating film on the surface of the metal wire cannot be sufficiently broken.

【００１５】このため、金属ワイヤ表面に被覆絶縁膜が
残留し、ワイヤ／リード間の接合強度を低下させ、それ
ら部材間の接合上の信頼性を低下させる問題があること
を本発明者は見い出した。[0015] For this reason, the inventor has discovered that there is a problem in that the coating insulating film remains on the surface of the metal wire, reducing the bonding strength between the wire and the lead, and reducing the reliability of the bond between these members. Ta.

【００１６】本発明は上記課題に着目してなされたもの
であり、その目的は、被覆ワイヤとインナーリードとの
接合強度を向上させ、それら部材間の接合上の信頼性を
向上させることのできる技術を提供することにある。The present invention has been made with attention to the above-mentioned problems, and its purpose is to improve the bonding strength between the coated wire and the inner lead, and to improve the reliability of the bond between these members. The goal is to provide technology.

【００１７】本発明の前記ならびにその他の目的と新規
な特徴は、明細書の記述および添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.

【００１８】[0018]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions will be as follows.
It is as follows.

【００１９】すなわち、請求項１記載の発明は、被覆ワ
イヤが接合されるインナーリードの表面のメッキ層の表
面を粗くしたリードフレーム構造とするものである。That is, the invention according to claim 1 provides a lead frame structure in which the surface of the plating layer on the surface of the inner lead to which the covered wire is bonded is roughened.

【００２０】[0020]

【作用】上記した請求項１記載の発明によれば、被覆ワ
イヤをインナーリードに接合する際、ワイヤ表面の被覆
絶縁膜等をメッキ層表面の凹凸によって充分破らせるこ
とができるので、被覆ワイヤをその活性面を露出させた
状態でインナーリードに接合することができる。このた
め、被覆ワイヤとインナーリードとの接合強度を向上さ
せることができ、それら部材間の接合上の信頼性を向上
させることが可能となる。[Function] According to the invention as set forth in claim 1, when the covered wire is bonded to the inner lead, the covering insulating film etc. on the wire surface can be sufficiently broken by the unevenness on the surface of the plating layer, so that the covered wire can be bonded to the inner lead. It can be bonded to the inner lead with its active surface exposed. Therefore, the bonding strength between the covered wire and the inner lead can be improved, and the reliability of the bonding between these members can be improved.

【００２１】[0021]

【実施例１】図１は本発明の一実施例であるリードフレ
ームのインナーリードの要部断面図、図２はそのリード
フレームの要部平面図、図３はそのインナーリード表面
におけるメッキ層表面の粗さを示すグラフ図、図４は従
来のインナーリード表面におけるメッキ層表面の粗さを
示すグラフ図、図５はインナーリード表面のメッキ層の
変形例を示す要部断面図、図６は図１のリードフレーム
を用いた半導体集積回路装置の一部破断斜視図、図７は
その半導体集積回路装置の要部断面図、図８および図９
はその半導体集積回路装置における被覆ワイヤ／リード
接合の作業領域を示すグラフ図、図１０および図１１は
従来の半導体集積回路装置における被覆ワイヤ／リード
接合の作業領域を示すグラフ図、図１２はその半導体集
積回路装置と従来の半導体集積回路装置との被覆ワイヤ
／リード接合部の接合強度を比較するためのグラフ図で
ある。[Embodiment 1] Fig. 1 is a sectional view of a main part of an inner lead of a lead frame according to an embodiment of the present invention, Fig. 2 is a plan view of a main part of the lead frame, and Fig. 3 is a surface of a plating layer on the surface of the inner lead. 4 is a graph showing the roughness of the surface of the plating layer on the surface of the conventional inner lead. FIG. 5 is a cross-sectional view of the main part showing a modification of the plating layer on the surface of the inner lead. A partially cutaway perspective view of a semiconductor integrated circuit device using the lead frame of FIG. 1, FIG. 7 is a cross-sectional view of the main part of the semiconductor integrated circuit device, and FIGS. 8 and 9.
10 and 11 are graphs showing the working area of covered wire/lead bonding in the conventional semiconductor integrated circuit device, and FIG. 12 is a graph showing the working area of covered wire/lead bonding in the conventional semiconductor integrated circuit device. FIG. 2 is a graph diagram for comparing the bond strength of a covered wire/lead bond between a semiconductor integrated circuit device and a conventional semiconductor integrated circuit device.

【００２２】本実施例１のリードフレームの単位領域を
図２に示す。リードフレーム１は、例えば４２アロイま
たは銅（Ｃｕ）からなり、その中央にはダイパッド２が
設けられている。FIG. 2 shows a unit area of the lead frame of the first embodiment. The lead frame 1 is made of, for example, 42 alloy or copper (Cu), and a die pad 2 is provided in the center thereof.

【００２３】ダイパッド２は、後述する半導体チップ３
が搭載される構成部であり、その四隅に設けられた吊り
部４によってリードフレーム１に支持されている。The die pad 2 is a semiconductor chip 3 which will be described later.
is a component on which is mounted, and is supported by the lead frame 1 by hanging parts 4 provided at its four corners.

【００２４】ダイパッド２の中央には、例えば十字状の
貫通孔２ａが穿孔されている。貫通孔２ａは、リードフ
レーム１と後述するモールド樹脂との密着性を向上させ
る上、ダイパッド２の下面側で発生した応力を分散させ
る機能を有している。In the center of the die pad 2, for example, a cross-shaped through hole 2a is bored. The through hole 2a has a function of improving the adhesion between the lead frame 1 and a mold resin to be described later, as well as dispersing stress generated on the lower surface side of the die pad 2.

【００２５】ダイパッド２の外周には、それを囲むよう
に複数のリード５が、その中途に設けられたダム片６に
よって連結され支持された状態で設けられている。A plurality of leads 5 are provided around the outer periphery of the die pad 2 so as to surround it, and are connected and supported by a dam piece 6 provided in the middle.

【００２６】リード５は、アウターリード５ａおよびイ
ンナーリード５ｂによって構成されている。リード５の
本数は、例えば１００本程度である。The lead 5 is composed of an outer lead 5a and an inner lead 5b. The number of leads 5 is, for example, about 100.

【００２７】本実施例１においては、図１に示すように
、インナーリード５ｂの表面に、例えばＡｇからなる無
光沢なメッキ層７が形成されている。図１の二点鎖線は
、後述する被覆ワイヤ８を示している。In the first embodiment, as shown in FIG. 1, a matte plating layer 7 made of, for example, Ag is formed on the surface of the inner lead 5b. The two-dot chain line in FIG. 1 indicates a covered wire 8, which will be described later.

【００２８】本実施例１のメッキ層７の表面粗さと、従
来のメッキ層の表面粗さとを、それぞれ図３、図４に示
す。The surface roughness of the plating layer 7 of Example 1 and the conventional plating layer are shown in FIGS. 3 and 4, respectively.

【００２９】図３および図４に示すように、本実施例１
のインナーリード５ｂのメッキ層７（図１参照）の表面
は、従来のメッキ表面よりも粗くなっている。As shown in FIGS. 3 and 4, this embodiment 1
The surface of the plating layer 7 (see FIG. 1) of the inner lead 5b is rougher than the conventional plating surface.

【００３０】メッキ層７の表面の凹凸幅は、大きいほど
良く、一概には規定できないが、例えば２．５μｍ以上
が望ましい。その条件の時、被覆ワイヤ８（図１参照）
との接合性等の上で、最も良好な結果が得られたからで
ある。The width of the unevenness on the surface of the plating layer 7 is preferably 2.5 μm or more, for example, although it cannot be absolutely defined. Under these conditions, the coated wire 8 (see Figure 1)
This is because the best results were obtained in terms of bondability, etc.

【００３１】また、メッキ層７の厚さも、一概に規定で
きないが、例えば５〜６μｍ程度が望ましい。この場合
もその条件の時、被覆ワイヤ８（図１参照）との接合性
等の上で、最も良好な結果が得られたからである。[0031]Although the thickness of the plating layer 7 cannot be absolutely defined, it is preferably about 5 to 6 μm, for example. This is because, in this case as well, the best results were obtained in terms of bondability with the coated wire 8 (see FIG. 1) under these conditions.

【００３２】このような表面の粗いメッキ層７を形成す
るには、例えばインナーリード５ｂの表面にメッキを施
す際、メッキ電流密度を従来よりも下げれば良い。In order to form such a plating layer 7 with a rough surface, for example, when plating the surface of the inner lead 5b, the plating current density may be lowered compared to the conventional one.

【００３３】また、メッキ層７の表面を粗くする方法と
して、例えば図５に示すように、インナーリード５ｂの
表面にアルミナ（Ａｌ２　Ｏ３）粒子（図示せず）等を
高速、高圧で吹き付けて凹凸を形成し、その表面に通常
の、すなわち、従来のメッキ層７ａを形成しても良い。Further, as a method of roughening the surface of the plating layer 7, for example, as shown in FIG. 5, alumina (Al2O3) particles (not shown) or the like are sprayed onto the surface of the inner lead 5b at high speed and high pressure to make the surface rough. , and a normal or conventional plating layer 7a may be formed on the surface thereof.

【００３４】ただし、この場合は、インナーリード５ｂ
の表面の凹凸がメッキ層７ａによって消えないように、
メッキ厚さ等のような条件を設定する。However, in this case, the inner lead 5b
so that the unevenness on the surface of the plated layer 7a is not erased by the plating layer 7a.
Setting conditions such as plating thickness, etc.

【００３５】また、インナーリード５ｂの表面に凹凸を
形成し、その表面に本実施例１のメッキ層７を形成して
も良い。この場合、メッキ層７の表面自体に凹凸が形成
されるので、インナーリード５ｂの表面の凹凸の消去を
余り考慮する必要がない。このため、メッキ厚さ等のよ
うな条件設定を容易にすることが可能となる。Furthermore, it is also possible to form irregularities on the surface of the inner lead 5b, and to form the plating layer 7 of the first embodiment on the surface. In this case, since irregularities are formed on the surface of the plating layer 7 itself, there is no need to give much consideration to erasing the irregularities on the surface of the inner lead 5b. Therefore, it becomes possible to easily set conditions such as plating thickness.

【００３６】図１に示すようにメッキ層７の表面を粗く
すると、例えば熱圧着法によって被覆ワイヤ８をインナ
ーリード５ｂにボンディングする際、金属ワイヤ８ａの
表面の被覆絶縁膜８ｂをメッキ層７の表面の凹凸によっ
て破らせることができる。When the surface of the plating layer 7 is roughened as shown in FIG. 1, when the covered wire 8 is bonded to the inner lead 5b by thermocompression bonding, for example, the covering insulating film 8b on the surface of the metal wire 8a is roughened by the plating layer 7. It can be broken by the unevenness of the surface.

【００３７】すなわち、金属ワイヤ８ａの表面を充分に
露出させることができるので、被覆ワイヤ８とインナー
リード５ｂとの接合性を良好にすることができ、被覆ワ
イヤ／リード間の接合強度を向上させることが可能とな
る。That is, since the surface of the metal wire 8a can be sufficiently exposed, the bondability between the covered wire 8 and the inner lead 5b can be improved, and the bonding strength between the covered wire and the lead can be improved. becomes possible.

【００３８】次に、以上のようなリードフレーム１を用
いた半導体集積回路装置を図６および図７に示す。Next, a semiconductor integrated circuit device using the lead frame 1 as described above is shown in FIGS. 6 and 7.

【００３９】本実施例１の半導体集積回路装置９は、例
えばＱＦＰ（ＱｕａｄＦｌａｔ　Ｐａｃｋａｇｅ）構造
を有する。The semiconductor integrated circuit device 9 of the first embodiment has, for example, a QFP (QuadFlat Package) structure.

【００４０】図６に示すように、ダイパッド２上に搭載
された半導体チップ３は、モールド樹脂１０によって封
止されている。As shown in FIG. 6, the semiconductor chip 3 mounted on the die pad 2 is sealed with a molding resin 10. As shown in FIG.

【００４１】モールド樹脂１０は、例えばエポキシ系の
樹脂からなり、その側壁から、例えばガルウィング状に
成形されたアウターリード５ａが突出されている。アウ
ターリードＳａの本数は、例えば１００本程度である。The mold resin 10 is made of, for example, an epoxy resin, and has outer leads 5a formed in, for example, a gull wing shape protruding from its side wall. The number of outer leads Sa is, for example, about 100.

【００４２】なお、図１および図２に示したインナーリ
ード５ｂは、図面を見易くするため、図６に示していな
い。Note that the inner lead 5b shown in FIGS. 1 and 2 is not shown in FIG. 6 in order to make the drawing easier to see.

【００４３】半導体チップ３は、図７に示すように、そ
の主面を上に向けた状態で接着部１１によってダイパッ
ド２上に接着されている。接着部１１は、例えばＡｇ入
りエポキシ樹脂からなる。As shown in FIG. 7, the semiconductor chip 3 is bonded onto the die pad 2 by an adhesive portion 11 with its main surface facing upward. The adhesive portion 11 is made of, for example, epoxy resin containing Ag.

【００４４】また、半導体チップ３は、例えばシリコン
（Ｓｉ）単結晶からなり、その主面側には、例えばＣＭ
ＯＳ（Ｃｏｍｐｌｅｍｅｎｔａｒｙ　ＭＯＳ）ゲートア
レイ等のような論理回路が形成されている。The semiconductor chip 3 is made of, for example, silicon (Si) single crystal, and has, for example, CM on its main surface side.
A logic circuit such as an OS (Complementary MOS) gate array is formed.

【００４５】半導体チップ３のボンディングパッド（以
下、単にパッドという）１２と、リードフレーム１のイ
ンナーリード５ｂとは、被覆ワイヤ８によって電気的に
接続されている。Bonding pads (hereinafter simply referred to as pads) 12 of the semiconductor chip 3 and inner leads 5b of the lead frame 1 are electrically connected by covered wires 8.

【００４６】被覆ワイヤ８の金属ワイヤ８ａは、例えば
金（Ａｕ）等のような金属からなり、その直径は、例え
ば３０μｍ程度である。The metal wire 8a of the coated wire 8 is made of a metal such as gold (Au), and has a diameter of, for example, about 30 μm.

【００４７】金属ワイヤ８ａの一端は、例えば熱圧着法
によってパッド１２に接合されている。また、金属ワイ
ヤ８ａの他端は、例えば熱圧着法によってインナーリー
ド５ｂに接合されている。One end of the metal wire 8a is bonded to the pad 12 by, for example, thermocompression bonding. Further, the other end of the metal wire 8a is joined to the inner lead 5b by, for example, thermocompression bonding.

【００４８】本実施例１においては、例えば被覆ワイヤ
８とパッド１２とを接合した後、被覆ワイヤ８とインナ
ーリード５ｂとが接合されている。被覆ワイヤ８とイン
ナーリード１２との接合時における接合温度は、例えば
２５０℃程度である。In the first embodiment, for example, after the covered wire 8 and the pad 12 are bonded, the covered wire 8 and the inner lead 5b are bonded. The bonding temperature when bonding the coated wire 8 and the inner lead 12 is, for example, about 250°C.

【００４９】金属ワイヤ８ａの表面には、例えばポリウ
レタン樹脂、ポリイミド樹脂またはエステルイミド樹脂
等からなる被覆絶縁膜８ｂが形成されている。An insulating coating film 8b made of, for example, polyurethane resin, polyimide resin, or esterimide resin is formed on the surface of the metal wire 8a.

【００５０】すなわち、本実施例１の半導体集積回路装
置９は、隣接する金属ワイヤ８ａ同士の接触による短絡
不良等を防止できるようになっている。That is, the semiconductor integrated circuit device 9 of the first embodiment is designed to prevent short-circuit defects and the like due to contact between adjacent metal wires 8a.

【００５１】ところで、本実施例１においては、上記し
たようにインナーリード５ｂの表面に、従来よりも表面
の粗いメッキ層７が形成されている。In the first embodiment, as described above, the plating layer 7, which has a rougher surface than the conventional one, is formed on the surface of the inner lead 5b.

【００５２】メッキ層７は、金属ワイヤ８ａとの接着性
を高める機能を有する上、上記したように被覆ワイヤ８
とインナーリード５ｂとの接合に際し、メッキ層７の表
面の凹凸によって被覆絶縁膜８ｂを破り、金属ワイヤ８
ａを露出させ、被覆ワイヤ／リード間の接合強度を高め
る機能も有している。[0052] The plating layer 7 not only has the function of increasing the adhesion to the metal wire 8a, but also has the function of increasing the adhesion to the metal wire 8a.
When joining the metal wire 8 to the inner lead 5b, the coating insulation film 8b is broken due to the unevenness of the surface of the plating layer 7, and the metal wire 8
It also has the function of exposing a and increasing the bonding strength between the covered wire and the lead.

【００５３】次に、本実施例１の被覆ワイヤ／リード接
合の作業領域を図８および図９に、また、比較のため従
来の被覆ワイヤ／リード接合の作業領域を図１０および
図１１にそれぞれ示す。Next, FIGS. 8 and 9 show the working area of the covered wire/lead bonding in Example 1, and FIGS. 10 and 11 show the working area of the conventional covered wire/lead bonding for comparison. show.

【００５４】図８〜図１１のうち、図８および図１０は
、横引っ張り強度試験の結果を示し、図９および図１１
は、被覆ワイヤ／リード接合部の剥がれ試験の結果をそ
れぞれ示している。8 to 11, FIGS. 8 and 10 show the results of the lateral tensile strength test, and FIGS. 9 and 11 show the results of the lateral tensile strength test.
1 and 2 show the results of a peel test of the coated wire/lead joint, respectively.

【００５５】図８〜図１１のＰ１は、パワーを示し、Ｗ
１は荷重を示している。また、図８〜図１１の黒丸はワ
イヤ／リード接合部の剥がれ有りを示し、斜線丸はワイ
ヤ／リード接合部のメクレ有を示し、白丸はワイヤ／リ
ード接合部の剥がれ無しを、それぞれ示している。P1 in FIGS. 8 to 11 indicates power, and W
1 indicates the load. In addition, in FIGS. 8 to 11, black circles indicate peeling of the wire/lead joint, diagonal circles indicate peeling of the wire/lead joint, and white circles indicate no peeling of the wire/lead joint. There is.

【００５６】なお、黒丸の時に加わる強度の最低値は、
例えば１ｇよりも小さい。また、斜線丸の時に加わる強
度の最低値は、例えば１〜２ｇ程度である。さらに、白
丸の時に加わる強度の最低値は、例えば３ｇよりも大き
い。[0056] The lowest value of the intensity applied when the black circle is
For example, it is smaller than 1g. Further, the minimum value of the strength applied when the circle is shaded is, for example, about 1 to 2 g. Furthermore, the lowest value of the strength applied when the circle is white is, for example, greater than 3 g.

【００５７】このような図８〜図１１において、被覆ワ
イヤ／リード接合部の剥がれが発生せず、かつ、その接
合部の接合強度が良好な領域が作業領域であり、作業領
域が広いほど安定な接合が可能となる。In FIGS. 8 to 11, the working area is the area where the coated wire/lead joint does not peel off and the joint has good bonding strength, and the wider the working area, the more stable it is. This makes it possible to perform various types of bonding.

【００５８】すなわち、図８〜図１１に示すように、本
実施例１の場合は、従来よりも作業領域が広範囲であり
、被覆ワイヤ／リード間において安定なボンディングが
可能である。That is, as shown in FIGS. 8 to 11, in the case of the first embodiment, the working area is wider than the conventional one, and stable bonding between the covered wire and the lead is possible.

【００５９】また、このような半導体集積回路装置９に
おける被覆ワイヤ／リード接合強度と、従来の半導体集
積回路装置の被覆ワイヤ／リード接合強度との比較を図
１２に示す。Further, FIG. 12 shows a comparison between the covered wire/lead bonding strength in such a semiconductor integrated circuit device 9 and the covered wire/lead bonding strength in a conventional semiconductor integrated circuit device.

【００６０】実線が本実施例１の場合であり、二点鎖線
が従来の場合である。図１２に示すように、本実施例１
においては、被覆ワイヤ／リード接合部の接合強度を従
来よりも向上させることが可能である。The solid line is for the first embodiment, and the two-dot chain line is for the conventional case. As shown in FIG. 12, this example 1
In this case, it is possible to improve the bonding strength of the covered wire/lead bonding portion compared to the conventional method.

【００６１】以上、本実施例１によれば、インナーリー
ド５ｂ表面のメッキ層７の表面を粗くしたことにより、
被覆ワイヤ８をインナーリード５ｂに熱圧着法等によっ
て接合する際、金属ワイヤ８ａの表面の被覆絶縁膜８ｂ
を、メッキ層７の表面の凹凸によって破らせることがで
きる。As described above, according to the first embodiment, by roughening the surface of the plating layer 7 on the surface of the inner lead 5b,
When bonding the coated wire 8 to the inner lead 5b by thermocompression bonding or the like, the coated insulating film 8b on the surface of the metal wire 8a
can be broken by the unevenness of the surface of the plating layer 7.

【００６２】このため、金属ワイヤ８ａの表面を充分に
露出させることができるので、被覆ワイヤ８とインナー
リード５ｂとの接合性を良好にすることができる。[0062] Therefore, the surface of the metal wire 8a can be sufficiently exposed, so that the bondability between the coated wire 8 and the inner lead 5b can be improved.

【００６３】したがって、被覆ワイヤ／リード接合部の
接合強度を向上させることができ、被覆ワイヤ／リード
接合部の接合上の信頼性を向上させることが可能となる
。[0063] Therefore, the bonding strength of the covered wire/lead bonding portion can be improved, and the reliability of the bonding of the covered wire/lead bonding portion can be improved.

【００６４】[0064]

【実施例２】図１３は本発明の他の実施例である半導体
集積回路装置の要部断面図、図１４はその半導体集積回
路装置における被覆ワイヤとパッケージ基板上のリード
との接合部を示す要部断面図である。[Embodiment 2] FIG. 13 is a sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 14 shows a joint between a covered wire and a lead on a package substrate in the semiconductor integrated circuit device. It is a sectional view of the main part.

【００６５】図１３に示す本実施例２の半導体集積回路
装置１３は、例えば気密封止形パッケージ構造を有する
。The semiconductor integrated circuit device 13 of the second embodiment shown in FIG. 13 has, for example, a hermetically sealed package structure.

【００６６】パッケージ基板１４は、例えばＡｌ２　Ｏ
３　−ＺｒＯ２　等のようなセラミックからなり、その
凹部１４ａの底面には、半導体チップ３がその主面を上
に向けた状態で接着部１１によって接着されている。The package substrate 14 is made of Al2O, for example.
3 -ZrO2 or the like, and the semiconductor chip 3 is bonded to the bottom surface of the recess 14a with the adhesive portion 11 with its main surface facing upward.

【００６７】また、パッケージ基板１４において、リー
ド形成面には、リード（外部引出用端子）１５が形成さ
れている。Furthermore, in the package substrate 14, leads (terminals for external extraction) 15 are formed on the lead forming surface.

【００６８】このようなリード１５と、半導体チップ３
のパッド１２とは、被覆ワイヤ８によって電気的に接続
されている。[0068] Such leads 15 and semiconductor chip 3
The pad 12 is electrically connected to the pad 12 by a covered wire 8.

【００６９】被覆ワイヤ８とリード１５との接合部の断
面図を図１４に示す。図１４に示すように、リード１５
の表面には、前記実施例１で説明したメッキ層７が形成
されている。FIG. 14 shows a cross-sectional view of the joint between the covered wire 8 and the lead 15. As shown in FIG.
The plating layer 7 described in Example 1 is formed on the surface of the substrate.

【００７０】したがって、本実施例２においても、被覆
ワイヤ８をリード１５に熱圧着法等によって接合する際
、金属ワイヤ８ａの表面の被覆絶縁膜８ｂを、メッキ層
７の表面の凹凸によって破らせることができる。Therefore, in the second embodiment, when bonding the coated wire 8 to the lead 15 by thermocompression bonding or the like, the coating insulating film 8b on the surface of the metal wire 8a is broken by the unevenness on the surface of the plating layer 7. be able to.

【００７１】このため、金属ワイヤ８ａの表面を充分に
露出させることができるので、被覆ワイヤ８とリード１
５との接合性を良好にすることができる。Therefore, since the surface of the metal wire 8a can be sufficiently exposed, the coated wire 8 and the lead 1 can be
5 can be improved.

【００７２】したがって、被覆ワイヤ／リード接合部の
接合強度を向上させることができ、被覆ワイヤ／リード
接合部の接合上の信頼性を向上させることが可能となる
。[0072] Therefore, the bonding strength of the covered wire/lead bonding portion can be improved, and the reliability of the bonding of the covered wire/lead bonding portion can be improved.

【００７３】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
１，２に限定されるものではなく、その要旨を逸脱しな
い範囲で種々変更可能であることはいうまでもない。[0073] The invention made by the present inventor has been specifically explained based on Examples, but the present invention is not limited to Examples 1 and 2, and various modifications can be made without departing from the gist thereof. It goes without saying that it is possible.

【００７４】例えば前記実施例１，２においては、被覆
ワイヤとインナーリードとを接合する方法として熱圧着
法を用いた場合について説明したが、これに限定される
ものではなく種々変更可能であり、例えば比較的低温で
接合処理が可能な超音波ワイヤボンディング法または熱
圧着法と超音波ワイヤボンディング法とを併用した方法
によって接合しても良い。For example, in the first and second embodiments described above, a case was explained in which a thermocompression bonding method was used as a method of joining the covered wire and the inner lead, but the method is not limited to this and various modifications can be made. For example, bonding may be performed by an ultrasonic wire bonding method or a method using a combination of a thermocompression bonding method and an ultrasonic wire bonding method, which can perform a bonding process at a relatively low temperature.

【００７５】この場合、被覆ワイヤ／リード接合に際し
て、金属ワイヤを超音波振動エネルギーによって振動さ
せることにより、ワイヤ表面の被覆絶縁膜をインナーリ
ード表面におけるメッキ層の凹凸によって機械的に研削
・除去することができる。In this case, when bonding the coated wire/lead, by vibrating the metal wire with ultrasonic vibration energy, the coating insulation film on the wire surface is mechanically ground and removed by the unevenness of the plating layer on the inner lead surface. Can be done.

【００７６】この結果、被覆ワイヤの金属面を良好に露
出させることができるので、被覆ワイヤとリードとの接
合性を良好にすることができ、被覆ワイヤ／リード接合
部の接合強度を向上させることが可能となる。As a result, the metal surface of the coated wire can be well exposed, so that the bondability between the coated wire and the lead can be improved, and the bonding strength of the coated wire/lead joint can be improved. becomes possible.

【００７７】また、前記実施例１，２においては、被覆
ワイヤのワイヤをＡｕとした場合について説明したが、
これに限定されるものではなく種々変更可能であり、例
えばアルミニウム（Ａｌ）またはＣｕとしても良い。[0077] Furthermore, in the first and second embodiments described above, the case where the coated wire was made of Au was explained.
The material is not limited to this, and various changes are possible. For example, aluminum (Al) or Cu may be used.

【００７８】この場合、被覆絶縁膜を、例えばＡｌ２　
Ｏ３　、ＣｕＯ２　またはＣｕＯ等のような、金属酸化
膜としても良い。In this case, the covering insulating film is made of, for example, Al2
A metal oxide film such as O3, CuO2 or CuO may also be used.

【００７９】また、前記実施例１，２においては、半導
体チップにＣＭＯＳゲートアレイ等のような論理回路が
形成されている場合について説明したが、これに限定さ
れるものではなく種々変更可能であり、例えばＤＲＡＭ
（Ｄｙｎａｍｉｃ　ＲＡＭ）等のような半導体メモリ回
路が形成されていても良い。Furthermore, in the first and second embodiments, the case where a logic circuit such as a CMOS gate array is formed on a semiconductor chip has been described, but the present invention is not limited to this and various modifications can be made. , for example, DRAM
A semiconductor memory circuit such as (Dynamic RAM) or the like may be formed.

【００８０】また、前記実施例２においては、パッケー
ジ基板上に形成されたリードのメッキ層表面を粗くした
場合について説明したが、これに限定されるものではな
く、例えば半導体チップが搭載されるプリント配線基板
に形成されたリードのメッキ層の表面を粗くしても良い
。Further, in the second embodiment, the case where the surface of the plating layer of the lead formed on the package substrate is roughened is explained, but the present invention is not limited to this. The surface of the plating layer of the lead formed on the wiring board may be roughened.

【００８１】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野であるＱＦＰ
構造を有する半導体集積回路装置に適用した場合につい
て説明したが、これに限定されず種々適用可能であり、
例えば樹脂モールド形ＤＩＰ（Ｄｕａｌ　Ｉｎ−ｌｉｎ
ｅ　Ｐａｃｋａｇｅ）　やＳＯＪ（Ｓｍａｌｌ　Ｏｕｔ
ｌｉｎｅ　Ｊ−ｌｅａｄ）パッケージ等、他のパッケー
ジ構造を有する半導体集積回路装置に適用することも可
能である。[0081] In the above explanation, the invention made by the present inventor will be mainly explained in relation to QFP, which is the application field that is the background of the invention.
Although the case where the present invention is applied to a semiconductor integrated circuit device having a structure has been described, it is not limited to this and various applications are possible.
For example, resin mold type DIP (Dual In-lin)
e Package) and SOJ (Small Out
It is also possible to apply the present invention to semiconductor integrated circuit devices having other package structures, such as a line J-lead package.

【００８２】[0082]

【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
下記のとおりである。[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions are briefly explained as follows.
It is as follows.

【００８３】すなわち、請求項１記載の発明によれば、
被覆ワイヤをインナーリードに接合する際、ワイヤ表面
の被覆絶縁膜等をメッキ層表面の凹凸によって充分破ら
せることができるので、被覆ワイヤをその活性面を露出
させた状態でインナートードに接合することができる。 このため、被覆ワイヤとインナーリードとの接合強度を
向上させることができ、それら部材間の接合上の信頼性
を向上させることが可能となる。That is, according to the invention described in claim 1,
When bonding the coated wire to the inner lead, the coating insulation film on the wire surface can be sufficiently broken by the unevenness of the plating layer surface, so the coated wire should be bonded to the inner lead with its active surface exposed. Can be done. Therefore, the bonding strength between the covered wire and the inner lead can be improved, and the reliability of the bonding between these members can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

【図１】本発明の一実施例であるリードフレームにおけ
るインナーリードの要部断面図である。FIG. 1 is a sectional view of a main part of an inner lead in a lead frame that is an embodiment of the present invention.

【図２】そのリードフレームの要部平面図である。FIG. 2 is a plan view of essential parts of the lead frame.

【図３】そのインナーリード表面のメッキ層表面の粗さ
を示すグラフ図である。FIG. 3 is a graph showing the roughness of the surface of the plating layer on the inner lead surface.

【図４】従来のインナーリード表面のメッキ層表面の粗
さを示すグラフ図である。FIG. 4 is a graph showing the roughness of the surface of the plating layer on the surface of the conventional inner lead.

【図５】本発明の他の実施例であるインナーリード表面
のメッキ層を示す要部断面図である。FIG. 5 is a sectional view of a main part showing a plating layer on the surface of an inner lead according to another embodiment of the present invention.

【図６】図１に示したリードフレームを用いた半導体集
積回路装置の一部破断斜視図である。6 is a partially cutaway perspective view of a semiconductor integrated circuit device using the lead frame shown in FIG. 1. FIG.

【図７】その半導体集積回路装置の要部断面図である。FIG. 7 is a sectional view of a main part of the semiconductor integrated circuit device.

【図８】その半導体集積回路装置における被覆ワイヤ／
リード接合の作業領域を示すグラフ図である。[Fig. 8] Covered wire/in the semiconductor integrated circuit device
FIG. 3 is a graph diagram showing a work area for lead joining.

【図９】その半導体集積回路装置における被覆ワイヤ／
リード接合の作業領域を示すグラフ図である。[Fig. 9] Covered wire/in the semiconductor integrated circuit device
FIG. 3 is a graph diagram showing a work area for lead joining.

【図１０】従来の半導体集積回路装置における被覆ワイ
ヤ／リード接合の作業領域を示すグラフ図である。FIG. 10 is a graph diagram showing a work area for covered wire/lead bonding in a conventional semiconductor integrated circuit device.

【図１１】従来の半導体集積回路装置における被覆ワイ
ヤ／リード接合の作業領域を示すグラフ図である。FIG. 11 is a graph diagram showing a work area for covered wire/lead bonding in a conventional semiconductor integrated circuit device.

【図１２】図７の半導体集積回路装置と従来の半導体集
積回路装置との被覆ワイヤ／リード接合部の接合強度を
比較するためのグラフ図である。12 is a graph diagram for comparing the bond strength of the covered wire/lead bond between the semiconductor integrated circuit device of FIG. 7 and a conventional semiconductor integrated circuit device; FIG.

【図１３】本発明の他の実施例である半導体集積回路装
置の要部断面図である。FIG. 13 is a sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

【図１４】図１３の半導体集積回路装置における被覆ワ
イヤとパッケージ基板上のリードとの接合部を示す要部
断面図である。14 is a sectional view of a main part showing a joint between a covered wire and a lead on a package substrate in the semiconductor integrated circuit device of FIG. 13; FIG.

【符号の説明】[Explanation of symbols]

１　　リードフレーム ２　　ダイパッド ２ａ　　貫通孔 ３　　半導体チップ ４　　吊り部 ５　　リード ５ａ　　アウターリード ５ｂ　　インナーリード ６　　ダム片 ７　　メッキ層 ７ａ　　メッキ層 ８　　被覆ワイヤ ８ａ　　金属ワイヤ ８ｂ　　被覆絶縁膜 ９　　半導体集積回路装置 １０　　モールド樹脂 １１　　接着部 １２　　ボンディングパッド １３　　半導体集積回路装置 １４　　パッケージ基板 １４ａ　　凹部 １５　　リード（外部引出用端子） 1 Lead frame 2 Die pad 2a Through hole 3 Semiconductor chip 4 Hanging part 5 Lead 5a Outer lead 5b Inner lead 6 Dam piece 7 Plating layer 7a Plating layer 8 Covered wire 8a Metal wire 8b Coating insulating film 9 Semiconductor integrated circuit device 10 Mold resin 11 Adhesive part 12 Bonding pad 13 Semiconductor integrated circuit device 14 Package board 14a Recessed part 15 Lead (terminal for external extraction)

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】　　被覆ワイヤが接合されるインナーリー
ドの表面に形成されたメッキ層の表面を粗くしたことを
特徴とするリードフレーム。1. A lead frame characterized in that the surface of a plating layer formed on the surface of an inner lead to which a covered wire is bonded is roughened. 【請求項２】　　前記メッキ層の表面の凹凸幅を２．５
μｍ以上としたことを特徴とする請求項１記載のリード
フレーム。2. The width of the unevenness on the surface of the plating layer is 2.5.
The lead frame according to claim 1, characterized in that the lead frame has a diameter of μm or more. 【請求項３】　　前記メッキ層が銀メッキ層であること
を特徴とする請求項１または２記載のリードフレーム。3. The lead frame according to claim 1, wherein the plating layer is a silver plating layer. 【請求項４】　　前記インナーリードの表面に、ブラス
ト処理を施した後、メッキ処理を施すことによって、前
記メッキ層の表面を粗くすることを特徴とする請求項１
記載のリードフレームの製造方法。4. The surface of the inner lead is subjected to blasting treatment and then plating treatment to roughen the surface of the plating layer.
Method of manufacturing the lead frame described. 【請求項５】　　請求項１，２，３または４記載のリー
ドフレームのインナーリードと、半導体チップのボンデ
ィングパッドとを被覆ワイヤによって接合したことを特
徴とする半導体集積回路装置。5. A semiconductor integrated circuit device, wherein the inner lead of the lead frame according to claim 1, 2, 3, or 4 and the bonding pad of a semiconductor chip are bonded to each other by a covered wire. 【請求項６】　　半導体チップのボンディングパッドと
、パッケージ基板または配線基板の外部引出用端子とが
被覆ワイヤによって接合されてなる半導体集積回路装置
であって、前記外部引出用端子の表面に形成されたメッ
キ層の表面を粗くしたことを特徴とする半導体集積回路
装置。6. A semiconductor integrated circuit device in which a bonding pad of a semiconductor chip and an external lead-out terminal of a package substrate or a wiring board are bonded by a covered wire, wherein a bonding pad of a semiconductor chip is bonded to an external lead-out terminal of a package substrate or a wiring board, wherein A semiconductor integrated circuit device characterized by having a roughened surface of a plating layer.
JP3084971A 1991-04-17 1991-04-17 Lead frame, manufacture thereof and semiconductor ic device using the same Pending JPH04318961A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3084971A JPH04318961A (en) 1991-04-17 1991-04-17 Lead frame, manufacture thereof and semiconductor ic device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3084971A JPH04318961A (en) 1991-04-17 1991-04-17 Lead frame, manufacture thereof and semiconductor ic device using the same

Publications (1)

Publication Number Publication Date
JPH04318961A true JPH04318961A (en) 1992-11-10

Family

ID=13845516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3084971A Pending JPH04318961A (en) 1991-04-17 1991-04-17 Lead frame, manufacture thereof and semiconductor ic device using the same

Country Status (1)

Country Link
JP (1) JPH04318961A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100286694B1 (en) * 1998-03-12 2001-04-16 최현두 Crystal oscillator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100286694B1 (en) * 1998-03-12 2001-04-16 최현두 Crystal oscillator

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