JPH04318913A - Exposure method and manufacture of semiconductor device using that method - Google Patents

Exposure method and manufacture of semiconductor device using that method

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Publication number
JPH04318913A
JPH04318913A JP3085385A JP8538591A JPH04318913A JP H04318913 A JPH04318913 A JP H04318913A JP 3085385 A JP3085385 A JP 3085385A JP 8538591 A JP8538591 A JP 8538591A JP H04318913 A JPH04318913 A JP H04318913A
Authority
JP
Japan
Prior art keywords
positions
exposure
wafer
image plane
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3085385A
Other languages
Japanese (ja)
Inventor
Akiyoshi Suzuki
章義 鈴木
Hirohiko Shinonaga
浩彦 篠永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP3085385A priority Critical patent/JPH04318913A/en
Publication of JPH04318913A publication Critical patent/JPH04318913A/en
Pending legal-status Critical Current

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Projection-Type Copiers In General (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To provide an exposure method which can print a pattern excellent in contrast on a photosensitive layer. CONSTITUTION:By changing the relative position in the direction of the optical axis of a photosensitive layer 4 to the image face of a projecting optical system 3, in the condition that any place of the photosensitive layer 4 is focused on this image face, and projecting the image of a circuit pattern in each position and laying them on top of each other, a circuit pattern is printed on the photosensitive layer 4.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は露光方法及び該方法を用
いた半導体デバイスの製造方法に関し、特に、投影光学
系により微細パタ−ンの像を被露光基板上に投影して該
被露光基板を露光する、所謂投影露光技術の改良に関す
るものである。
FIELD OF INDUSTRIAL APPLICATION This invention relates to an exposure method and a method for manufacturing semiconductor devices using the method, and more particularly, the present invention relates to an exposure method and a method for manufacturing semiconductor devices using the method. This invention relates to the improvement of so-called projection exposure technology that exposes images.

【0002】0002

【従来の技術】従来、半導体デバイスを製造する際、縮
小投影レンズ系によりレチクルの回路パタ−ンの像をウ
エハ−上に投影し、該回路パタ−ン像で該ウエハ−のレ
ジストを露光し、該レジストに縮小された回路パタ−ン
をプリントし、該レジストを現像していた。
Conventionally, when manufacturing semiconductor devices, an image of a circuit pattern on a reticle is projected onto a wafer using a reduction projection lens system, and a resist on the wafer is exposed with the circuit pattern image. , a reduced circuit pattern was printed on the resist, and the resist was developed.

【0003】この種の投影露光は、通常、投影レンズ系
の像面とウエハ−の該投影レンズ系の光軸方向に関する
相対位置を固定して行なう。しかしながら、近年、その
解像力を向上させる為に投影レンズ系の開口数(NA)
を大きくするにつれ投影レンズ系の焦点深度が非常に浅
くなり、投影レンズ系の像面湾曲やウエハ−の表面の凹
凸を補償して被露光領域全面に回路パタ−ン像を鮮明に
投影することが難しくなってきている。
This type of projection exposure is normally carried out by fixing the relative positions of the image plane of the projection lens system and the wafer with respect to the optical axis direction of the projection lens system. However, in recent years, in order to improve the resolution, the numerical aperture (NA) of the projection lens system has been increased.
As the depth of focus of the projection lens system increases, the depth of focus of the projection lens system becomes extremely shallow, which compensates for the curvature of field of the projection lens system and the unevenness of the wafer surface to clearly project a circuit pattern image over the entire exposed area. is becoming difficult.

【0004】そこで、近年、縮小投影レンズ系によりレ
チクルの回路パタ−ン像をウエハ−上に投影する時に、
ウエハ−を該投影レンズ系の光軸方向に上下動させるこ
とにより回路パタ−ン像に対するウエハ−の相対位置を
複数設定し、各位置で回路パタ−ン像を投影し多重露光
する方法が提案された。この方法によれば、投影レンズ
系の焦点深度が見かけ上増加するので、上記問題が幾分
解消される。
Therefore, in recent years, when projecting a circuit pattern image of a reticle onto a wafer using a reduction projection lens system,
A method has been proposed in which multiple relative positions of the wafer to the circuit pattern image are set by moving the wafer up and down in the optical axis direction of the projection lens system, and the circuit pattern image is projected at each position for multiple exposure. It was done. According to this method, the depth of focus of the projection lens system is apparently increased, so that the above-mentioned problem is solved to some extent.

【0005】[0005]

【発明が解決しようとしている課題】しかしながら、こ
の露光方法は、ウエハのレジストの厚さに比較してウエ
ハ−の上下方向への移動量が大きく、レジストに回路パ
タ−ン像がフォ−カスした状態で露光される割合が少な
い。従って、レジストにプリントされた回路パタ−ンの
コントラストがあまり良くない。
[Problems to be Solved by the Invention] However, in this exposure method, the amount of vertical movement of the wafer is large compared to the thickness of the resist on the wafer, and the circuit pattern image is not focused on the resist. The proportion of exposure to light is low. Therefore, the contrast of the circuit pattern printed on the resist is not very good.

【0006】更に、この露光方法では、利用できるレチ
クルのパタ−ンに制限がある。つまり、ホ−ルパタ−ン
の像を投影する場合、レジストにプリントされたパタ−
ンのコントラストがあまり良くないだけであるが、ライ
ンアンドスペ−スパタ−ンの像を投影する場合、ウエハ
−のレジストに対して大きくデフォ−カスさせると偽解
像が生じ、強度分布が反転したパタ−ン像がレジストに
投影されてしまう。従って、フォ−カス時の正規の強度
分布のパタ−ン像とデフォ−カス時の反転した強度分布
のパタ−ン像とがレジストに投影されることになり、コ
ントラストが極端に悪くなったり、ラインアンドスペ−
スがプリントされなくなったりする。
Furthermore, this exposure method has limitations on the reticle patterns that can be used. In other words, when projecting an image of a hole pattern, the pattern printed on the resist
The contrast is not very good, but when projecting a line-and-space pattern image, if the wafer resist is greatly defocused, false resolution will occur and the intensity distribution will be reversed. The pattern image is projected onto the resist. Therefore, a pattern image of a normal intensity distribution during focusing and a pattern image of an inverted intensity distribution during defocusing are projected onto the resist, resulting in extremely poor contrast and line and space
The page may not be printed.

【0007】[0007]

【課題を解決するための手段】本発明の露光方法は、投
影光学系の像面に対する被露光基板の相対位置を該投影
光学系の光軸方向に複数設定し、各々の位置で所定パタ
−ンの像を該被露光基板上に投影して該被露光基板を露
光する方法において、前記被露光基板の感光層の前記光
軸方向の複数位置に前記像面を一致させて露光すること
により上記課題を解決する。
Means for Solving the Problems In the exposure method of the present invention, a plurality of relative positions of the substrate to be exposed with respect to the image plane of the projection optical system are set in the optical axis direction of the projection optical system, and a predetermined pattern is set at each position. In the method of exposing the exposed substrate by projecting an image of the image onto the exposed substrate, by aligning the image plane with a plurality of positions in the optical axis direction of the photosensitive layer of the exposed substrate, and exposing the exposed substrate. Solve the above issues.

【0008】又、本発明の製造方法の第1の形態は、投
影光学系の像面に対するウエハ−の相対位置を該投影光
学系の光軸方向に複数設定し、各々の位置で回路パタ−
ン像を該ウエハ−上に投影して該ウエハ−を露光した後
、該ウエハ−を現像し、半導体デバイスを製造する方法
において、前記ウエハ−のレジスト膜の前記光軸方向の
複数位置に前記像面を一致させて露光することにより上
記課題を解決する。
In the first embodiment of the manufacturing method of the present invention, a plurality of relative positions of the wafer to the image plane of the projection optical system are set in the optical axis direction of the projection optical system, and a circuit pattern is formed at each position.
In the method of manufacturing a semiconductor device by projecting an image onto the wafer to expose the wafer and then developing the wafer, the resist film of the wafer is exposed at a plurality of positions in the optical axis direction. The above problem is solved by aligning the image planes and performing exposure.

【0009】更に、本発明の製造方法の第2の形態は、
投影光学系の像面に対するウエハ−の相対位置を該投影
光学系の光軸方向に複数設定し、各々の位置で回路パタ
−ン像を該ウエハ−上に投影して該ウエハ−を露光した
後、該ウエハ−を現像し、半導体デバイスを製造する方
法において、前記ウエハ−のレジスト膜及び透明膜を含
む層の前記光軸方向の複数位置に前記像面を一致させて
露光することにより上記課題を解決する。
Furthermore, a second form of the manufacturing method of the present invention is as follows:
A plurality of relative positions of the wafer to the image plane of the projection optical system were set in the optical axis direction of the projection optical system, and a circuit pattern image was projected onto the wafer at each position to expose the wafer. After that, in the method of developing the wafer and manufacturing a semiconductor device, the image plane is exposed to light by aligning the image plane with a plurality of positions in the optical axis direction of a layer including a resist film and a transparent film of the wafer. Solve problems.

【0010】本発明の好ましい形態では、前記感光層の
光軸方向の複数位置、前記レジスト膜の光軸方向の複数
位置、前記層の光軸方向の複数位置は、前記感光層、前
記レジスト膜、前記層の上面側から順に第1、第2位置
を含み、前記パタ−ン像を、該第1、第2位置の順に順
次投影することにより多重露光が行われる。
In a preferred embodiment of the present invention, the plurality of positions in the optical axis direction of the photosensitive layer, the plurality of positions in the optical axis direction of the resist film, and the plurality of positions in the optical axis direction of the layer include the photosensitive layer, the resist film , including first and second positions in order from the upper surface side of the layer, and multiple exposure is performed by sequentially projecting the pattern image on the first and second positions.

【0011】又、本発明の別の形態では、前記第1、第
2位置に対して同時に、前記パタ−ン像の投影が行われ
る。
In another aspect of the present invention, the pattern image is simultaneously projected onto the first and second positions.

【0012】本発明の露光方法及び第1の形態の製造方
法において、前記レジスト膜の光軸方向の複数位置の少
なくとも一つが前記レジスト膜内に設定され、該少なく
とも一つの位置の前記レジスト膜の上面からの距離をd
、前記レジスト膜の厚さと屈折率を各々t0 、n0と
する時、 0<d≦t0 /n0 なる条件を満たす、好ましい形態がある。
In the exposure method and manufacturing method of the first aspect of the present invention, at least one of a plurality of positions in the optical axis direction of the resist film is set within the resist film, and the resist film at the at least one position is The distance from the top surface is d
There is a preferred form that satisfies the following condition: 0<d≦t0/n0, where the thickness and refractive index of the resist film are t0 and n0, respectively.

【0013】本発明の第2の形態の製造方法において、
前記層の光軸方向の複数位置の少なくとも一つが前記層
内に設定され、該少なくとも一つの位置の前記層の上面
からの距離をd、前記レジスト膜の厚さと屈折率を各々
t0 、n0、前記透明膜の厚さと屈折率を各々tS、
nS、とする時、 0<d≦t0 /n0+tS/nS なる条件を満たす、好ましい形態がある。
[0013] In the manufacturing method of the second embodiment of the present invention,
At least one of a plurality of positions in the optical axis direction of the layer is set in the layer, the distance of the at least one position from the upper surface of the layer is d, the thickness and refractive index of the resist film are t0, n0, respectively. The thickness and refractive index of the transparent film are respectively tS,
When nS, there is a preferable form that satisfies the following condition: 0<d≦t0/n0+tS/nS.

【0014】又、本発明において、投影光学系の像面に
対するウエハ−(被露光基板)の相対位置を複数設定す
る手法には様々なものがある。例えば、(1)ウエハ−
を投影光学系の光軸方向に動かす、(2)投影光学系の
少なくとも一部を光軸方向に動かす、(3)パタ−ンを
備えるレチクル(被投影原板)を投影光学系の光軸方向
に動かす、(4)投影光学系に空気レンズやプリズム等
の光路長変更部材を設け、光路長を順次変える、(5)
パタ−ンの投影に使用する光の波長を順次変える、(6
)パタ−ンの投影を相異なる波長の光を同時に使用して
行なう、(7)同じパタ−ンを備える複数のレチクルを
投影光学系の光軸方向に沿って近接配置し、各レチクル
のパタ−ン像を同時に投影する。
Furthermore, in the present invention, there are various methods for setting a plurality of relative positions of the wafer (substrate to be exposed) with respect to the image plane of the projection optical system. For example, (1) wafer
(2) move at least a portion of the projection optical system in the optical axis direction; (3) move the reticle (projection target original plate) provided with a pattern in the optical axis direction of the projection optical system. (4) Provide an optical path length changing member such as an air lens or prism in the projection optical system to sequentially change the optical path length. (5)
Sequentially changing the wavelength of the light used to project the pattern (6
(7) A plurality of reticles with the same pattern are arranged close to each other along the optical axis direction of the projection optical system, and the pattern of each reticle is projected using light of different wavelengths at the same time. - project images at the same time.

【0015】又、パタ−ンの投影は、超高圧水銀等、レ
−ザ−、X線源などからの放射された光を、パタ−ンを
備えるレチクルに照射し、レチクルで微細パタ−ンに従
って透過又は反射せしめて投影光学系の瞳に向けること
により行なう。この投影光学系は、レンズアセンブリよ
り構成されるもの、ミラ−アセンブリより構成されるも
の、レンズ及びミラ−により構成されるもの、が使用さ
れる。
[0015] Further, to project a pattern, light emitted from ultra-high pressure mercury, a laser, an X-ray source, etc. is irradiated onto a reticle provided with a pattern, and a fine pattern is formed on the reticle. This is done by transmitting or reflecting the light and directing it to the pupil of the projection optical system. The projection optical system used may be one composed of a lens assembly, one composed of a mirror assembly, or one composed of a lens and a mirror.

【0016】[0016]

【実施例】図1は、基板5上のレジスト膜4をラインア
ンドスペ−スパタ−ンを介して露光した時のレジストの
光学特性の経時変化を示す説明図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory diagram showing changes over time in optical properties of a resist film 4 on a substrate 5 when exposed through a line-and-space pattern.

【0017】図1の最も上にパタ−ン像の強度分布を示
しており、このパタ−ン像がレジスト4上に投影される
。図1に矢印で示すように、パタ−ン像が投影され露光
されるレジスト4は、先ず、その上面40近傍の部分が
光エネルギ−を吸収し、この部分で光化学反応が生じレ
ジスト4を構成する感材が分解され、レジスト4による
光エネルギ−吸収が小さくなる所謂ブリ−チングが生じ
る。露光を継続すると、レジスト4の中央部、レジスト
の下面50の近傍へと順次光エネルギ−が到達するから
、この順にブリ−チングが生じていくことになる。 尚、レジスト4のブリ−チングが生じた部分はパタ−ン
像を形成する光に対しほぼ透明になる。
The intensity distribution of the pattern image is shown at the top of FIG. 1, and this pattern image is projected onto the resist 4. As shown by the arrow in FIG. 1, the resist 4 on which the pattern image is projected and exposed first absorbs light energy in a portion near its upper surface 40, and a photochemical reaction occurs in this portion, forming the resist 4. The photosensitive material is decomposed, and so-called bleaching occurs in which light energy absorption by the resist 4 is reduced. If the exposure is continued, the light energy reaches the center of the resist 4 and the vicinity of the lower surface 50 of the resist in sequence, so that bleaching occurs in this order. Incidentally, the bleached portion of the resist 4 becomes almost transparent to the light forming the pattern image.

【0018】本発明は、このようなレジストのブリ−チ
ング過程に着目し、投影光学系の像面に対するウエハ−
の相対位置を複数設定する際、レジストのブリ−チング
が進行する過程に応じて各位置を定め、パタ−ン像をレ
ジストの上面及び他の部分にフォ−カスせしめながら、
レジスト上面、他の部分、の順に露光を行なう。これに
より、レジストにパタ−ン像がフォ−カスした状態で露
光される割合を増加させ、レジストにプリントされるパ
タ−ンのコントラストを改善する。
The present invention focuses on such a resist bleaching process, and the wafer is
When setting multiple relative positions, each position is determined according to the progress of bleaching of the resist, and while focusing the pattern image on the top surface of the resist and other parts,
Exposure is performed on the upper surface of the resist and then on the other parts. This increases the rate at which the pattern image is exposed to light while being focused on the resist, thereby improving the contrast of the pattern printed on the resist.

【0019】図2に本発明の露光方法が適用される半導
体デバイスを製造する為の投影露光装置の一例を示す。
FIG. 2 shows an example of a projection exposure apparatus for manufacturing semiconductor devices to which the exposure method of the present invention is applied.

【0020】図2において、1はg線やi線やKrFエ
キシマレ−ザ−光等から成る照明光であり、照明系10
が照明光1を供給する。照明系10は照明光1によりレ
チクル2を均一な照度で照明する。
In FIG. 2, reference numeral 1 denotes illumination light consisting of g-line, i-line, KrF excimer laser light, etc., and the illumination system 10
provides illumination light 1. Illumination system 10 illuminates reticle 2 with illumination light 1 with uniform illuminance.

【0021】レチクル2を照明しレチクル2の回路パタ
−ン(ラインアンドスペ−スパタ−ンを含む)の光透過
部を透過した光は、縮小投影レンズ系3(光射出側がテ
レセントリック)の瞳に入射し、投影レンズ系3を介し
て出射する。この時、投影レンズ系3は、この光で、そ
の像面に回路パタ−ン像を形成する。
The light that illuminates the reticle 2 and passes through the light-transmitting part of the circuit pattern (including the line-and-space pattern) of the reticle 2 enters the pupil of the reduction projection lens system 3 (the light exit side is telecentric). The light enters and exits through the projection lens system 3. At this time, the projection lens system 3 uses this light to form a circuit pattern image on its image plane.

【0022】基板4上にレジスト5が塗布されたウエハ
−は、ウエハ−ステ−ジ6上に載置される。ウエハ−ス
テ−ジ6は、投影レンズ系3の光軸と直交する平面に沿
って可動のXYステ−ジ9、XYステ−ジ9上に付けた
複数の圧電素子7、複数の圧電素子7で支持されたZス
テ−ジ8とを備え、ウエハ−はZステ−ジ8により保持
される。又、各圧電素子7にパルス電圧を印加すること
によりZステ−ジ8を投影レンズ系3の光軸方向へ所望
の距離だけ動かすことができる。
A wafer having a resist 5 coated on a substrate 4 is placed on a wafer stage 6. As shown in FIG. The wafer stage 6 includes an XY stage 9 movable along a plane perpendicular to the optical axis of the projection lens system 3, a plurality of piezoelectric elements 7 attached to the XY stage 9, and a plurality of piezoelectric elements 7. The wafer is held by the Z stage 8. Furthermore, by applying a pulse voltage to each piezoelectric element 7, the Z stage 8 can be moved a desired distance in the optical axis direction of the projection lens system 3.

【0023】従って、この装置では、ウエハ−ステ−ジ
6上にウエハ−を載置し、XYステ−ジ9を移動させる
ことによりレチクル2にウエハ−の被露光領域が位置合
せされるようXYステ−ジ9を位置決めし、Zステ−ジ
8を動かしてウエハ−の被露光領域を投影レンズ系の像
面に合焦させ、ウエハ−の被露光領域にレチクル2の回
路パタ−ン像を投影し、露光する。露光終了後、ウエハ
−が、ウエハ−ステ−ジ6から搬出され、不図示の現像
器による現像、不図示のエッチング装置によるエッチン
グ等の各種工程を経て、半導体デバイスが製造される。
Therefore, in this apparatus, the wafer is placed on the wafer stage 6, and the XY stage 9 is moved so that the exposed area of the wafer is aligned with the reticle 2. The stage 9 is positioned, the Z stage 8 is moved to focus the exposed area of the wafer on the image plane of the projection lens system, and the circuit pattern image of the reticle 2 is placed on the exposed area of the wafer. Project and expose. After the exposure, the wafer is taken out from the wafer stage 6 and subjected to various steps such as development using a developing device (not shown) and etching using an etching device (not shown), thereby manufacturing semiconductor devices.

【0024】図2の装置を使用し本発明の露光方法を行
なう例について、図3(A)、(B)、(C)を用いて
説明する。
An example of performing the exposure method of the present invention using the apparatus shown in FIG. 2 will be described with reference to FIGS. 3(A), (B), and (C).

【0025】本実施例では、図1のZステ−ジ8を段階
的に上昇させることにより、図3に示すように、投影レ
ンズ系3の像面を、(A)レジスト4の上面、(B)レ
ジスト4の真ん中、(C)レジスト4の下面に、順次位
置付け、各位置において回路パタ−ン像による投影露光
を行ないレジスト4にパタ−ンをプリントしている。こ
こでは、レジスト4の上面と像面とを一致させた状態で
露光し、レジスト4の上面近傍をブリ−チングしてほぼ
透明に変化させた後、レジスト4の真ん中と像面とを一
致させた状態で露光し、レジスト4の真ん中近傍でブリ
−チングを進行させて、この部分までほぼ透明に変化さ
せた後、最後に、レジスト4の下面と像面とを一致させ
た状態で露光する。レジスト4に対する露光量は、レジ
スト4の感度に基づいて決定される。又、パタ−ンのプ
リントに要する全露光量Eを、(A)、(B)、(C)
の各投影露光でどのように分配するかは、適時決める。 例えば、(A)、(B)、(C)の各投影露光で、E/
3づつ分配するといった具合である。このような、間欠
的な投影露光の重ね合せによる露光の結果、非常に鮮明
な、レジステ4にパターンをプリントすることができる
In this embodiment, by raising the Z stage 8 in FIG. B) The center of the resist 4 and (C) the lower surface of the resist 4 are sequentially positioned, and a pattern is printed on the resist 4 by performing projection exposure using a circuit pattern image at each position. Here, exposure is performed with the top surface of the resist 4 aligned with the image plane, the vicinity of the top surface of the resist 4 is bleached and turned almost transparent, and then the center of the resist 4 is aligned with the image plane. After bleaching progresses near the center of the resist 4 to make it almost transparent up to this part, the resist 4 is finally exposed with the lower surface of the resist 4 aligned with the image plane. . The amount of exposure to the resist 4 is determined based on the sensitivity of the resist 4. Also, the total exposure amount E required to print the pattern is (A), (B), (C)
The distribution method for each projection exposure will be determined at the appropriate time. For example, in each projection exposure of (A), (B), and (C), E/
For example, 3 each will be distributed. As a result of such exposure by superimposing intermittent projection exposure, a very clear pattern can be printed on the register 4.

【0026】本実施例では、回路パタ−ン像に対するレ
ジスト4の相対位置を複数設定し、各位置での投影露光
の重ね合わせによりパタ−ンをプリントしているので、
投影レンズ系3の焦点深度を見かけ上増加させる。その
上、ここでは、レジスト4のブリ−チングの進行に合わ
せてレジスト4の上面、内部及び下面のみに像面を一致
させ、レジスト4以外の場所には像面を設定せずにプリ
ントを完了させているので、このレジストにプリントさ
れるパタ−ンのコントラストも高い。
In this embodiment, a plurality of relative positions of the resist 4 with respect to the circuit pattern image are set, and the pattern is printed by superimposing projection exposure at each position.
The apparent depth of focus of the projection lens system 3 is increased. Moreover, here, as the bleaching of resist 4 progresses, the image plane is matched only to the top, inside, and bottom surfaces of resist 4, and printing is completed without setting the image plane anywhere other than resist 4. Therefore, the contrast of the pattern printed on this resist is also high.

【0027】本実施例では、ウエハ−に対する像面位置
をレジスト4の上面から下面にかけて間欠的に変化させ
ているが、連続的に変化させてもいい。又、像面位置を
連続的に変化させる時には、リニア−に移動させても、
ノンリニア−に移動させても良い。又、像面位置を間欠
的に変化させる時には、像面位置の移動量、移動回数、
各位置での滞留時間等が主たるパラメ−タ−として考慮
されて、例えばウエハ−の上下動の制御が行なわれる。 更に、像面位置を間欠的に変化させる時には、照明系1
0の照明光1に対するシャッタ−を開いた状態で像面位
置を変化させる形態や、照明系10の照明光1に対する
シャッタ−の開閉と像面位置の変化を同期させる形態が
、採り得る。一方、像面位置を連続的に変化させる時に
も、シャッタ−を開いた状態で像面位置を変化させる形
態や、シャッタ−の開閉を像面位置の変化に同期させる
形態が、採り得る。
In this embodiment, the position of the image plane with respect to the wafer is intermittently changed from the upper surface to the lower surface of the resist 4, but it may be changed continuously. Also, when changing the image plane position continuously, even if you move it linearly,
It may be moved non-linearly. Also, when changing the image plane position intermittently, the amount of movement of the image plane position, the number of movements,
For example, the vertical movement of the wafer is controlled by considering the residence time at each position as a main parameter. Furthermore, when changing the image plane position intermittently, the illumination system 1
It is possible to adopt a mode in which the image plane position is changed with the shutter open for the illumination light 1 of 0, or a mode in which opening and closing of the shutter for the illumination light 1 of the illumination system 10 and changes in the image plane position are synchronized. On the other hand, when changing the image plane position continuously, it is possible to change the image plane position while the shutter is open, or to synchronize the opening and closing of the shutter with changes in the image plane position.

【0028】又、本実施例では、像面位置をレジスト4
の上面から下面(基板5の上面)まで変化させるようウ
エハ−を移動させているが、このようにウエハ−の移動
量とレジスト4の厚みとを同じにする形態に限定はされ
ない。即ち、レジスト4の下面に達する手前のレジスト
4内のある平面に像面を一致させた状態で露光を行なっ
て終了するように、或はレジスト4の下面の下方に像面
を一致させた状態で露光を行なって終了するように、ウ
エハ−を移動させてもいい。従って、例えば、図3の(
A)、(B)の工程だけでパタ−ンのプリントを完了さ
せることも可能である。又、必ずしもレジスト4の上面
に像面位置を一致させる必要もなく、要は、レジスト4
のその膜厚方向に関する相異なる複数位置に好ましくは
レジスト4内の複数位置に、像面位置を、レジスト4の
上面から下面に向かって、変化させればいい。そして、
レジスト4以外の場所に像面を一致させないようにして
露光を終わらせると効果が高い。
Furthermore, in this embodiment, the image plane position is set to the resist 4.
Although the wafer is moved so as to change from the upper surface to the lower surface (the upper surface of the substrate 5), the wafer is not limited to such a form in which the amount of movement of the wafer and the thickness of the resist 4 are made the same. In other words, the exposure is completed with the image plane aligned with a certain plane within the resist 4 before reaching the lower surface of the resist 4, or with the image plane aligned below the lower surface of the resist 4. The wafer may be moved so that the exposure is completed at . Therefore, for example, (
It is also possible to complete printing of the pattern with only steps A) and (B). Furthermore, it is not necessary to align the image plane position with the upper surface of the resist 4;
The image plane position may be changed from the upper surface to the lower surface of the resist 4 at a plurality of different positions in the film thickness direction, preferably at a plurality of positions within the resist 4. and,
It is highly effective if the exposure is completed in such a way that the image plane does not coincide with any location other than the resist 4.

【0029】レジスト4に対する投影レンズ系3の像面
の相対的な移動量及び移動特性は、レジスト4のブリ−
チング特性、基板5の表面構造(パタ−ン構造)や反射
率、照明光1の強度、等によって変更される。因に、レ
ジスト4の特性を示すパラメ−タ−として、A、B、C
パラメ−タ−というものが挙げられる。この内、Aパラ
メ−タ−がブリ−チング特性を表し、Bパラメ−タ−が
経時変化を起こさない基礎吸収を表し、Cパラメ−タ−
が感度を表す。
The relative movement amount and movement characteristics of the image plane of the projection lens system 3 with respect to the resist 4 are determined by the bleed of the resist 4.
It is changed depending on the switching characteristics, the surface structure (pattern structure) and reflectance of the substrate 5, the intensity of the illumination light 1, etc. Incidentally, as parameters indicating the characteristics of resist 4, A, B, C
One example is a parameter. Among these, the A parameter represents the bleaching characteristic, the B parameter represents the basal absorption that does not change over time, and the C parameter
represents the sensitivity.

【0030】我々の検討では、本実施例で、基板5が照
明光1を反射する表面を有し、レジスト4がブリ−チン
グにより照明光1に対し完全に透明になる場合を考える
と、レジスト4の上面40からのレジスト4に対する像
面の相対的な最大移動量dの最適値は、レジスト4の厚
さと屈折率を各々t0 、n0とする時、d=t0 /
n0で与えられることが分かった。又、実際は、Bパラ
メ−タ−で表される基礎吸収の影響等により、最適値は
、このdの値から若干小さめにずれることも判明した。
In our study, in this embodiment, considering the case where the substrate 5 has a surface that reflects the illumination light 1 and the resist 4 becomes completely transparent to the illumination light 1 by bleaching, the resist The optimum value of the maximum relative movement amount d of the image plane from the upper surface 40 of the resist 4 to the resist 4 is d=t0 / when the thickness and refractive index of the resist 4 are t0 and n0, respectively.
It turns out that it is given by n0. It has also been found that, in reality, the optimum value deviates slightly from this value of d due to the influence of basal absorption represented by the B parameter.

【0031】又、ウエハ−の構造が、図4に示すように
基板5上に照明光1に対して透明なSiO2膜11が形
成され、SiO2膜11上にレジスト4が形成されてい
る場合、基板5が照明光1を反射する表面を有し、レジ
スト4がブリ−チングにより照明光1に対し完全に透明
になる場合を考えると、レジスト4の上面からのレジス
ト4及び膜11より成る層に対する像面の相対的な最大
移動量dの最適値は、SiO2膜11の厚さと屈折率を
各々tS、nS、とする時、t0 /n0+tS/nS
で与えられる。従って、図4に示すウエハ−にパタ−ン
をプリントする場合には、図3に示すウエハ−にパタ−
ンをプリントする場合とは異なる露光制御を行なう必要
が出てくる時がある。又、図4のウエハ−の場合も、実
際は、Bパラメ−タ−で表される基礎吸収の影響等によ
り、最適値は、このdの値から若干小さめにずれる。
Further, when the structure of the wafer is such that a SiO2 film 11 transparent to the illumination light 1 is formed on the substrate 5 and a resist 4 is formed on the SiO2 film 11 as shown in FIG. Considering the case where the substrate 5 has a surface that reflects the illumination light 1 and the resist 4 becomes completely transparent to the illumination light 1 by bleaching, the layer consisting of the resist 4 and the film 11 from the top surface of the resist 4 The optimum value of the relative maximum movement amount d of the image plane relative to
is given by Therefore, when printing a pattern on the wafer shown in FIG. 4, the pattern is printed on the wafer shown in FIG.
There are times when it is necessary to perform exposure control that is different from that used when printing images. Also, in the case of the wafer shown in FIG. 4, the optimum value actually deviates slightly from this value of d due to the influence of basic absorption represented by the B parameter.

【0032】従って、基板上のレジストやSiO2等の
透光層の厚さをそれらの屈折率で割った値以下にレジス
ト上面からの像面の相対的な移動量を納めれば、レジス
トにコントラストの良いパタ−ンをプリントできる。
Therefore, if the amount of relative movement of the image plane from the top surface of the resist is kept below the value obtained by dividing the thickness of the resist on the substrate or the light-transmitting layer such as SiO2 by their refractive index, the contrast of the resist will be reduced. You can print good patterns.

【0033】即ち、図3及び図4のウエハ−を例に取る
と、夫々、レジストの厚さと屈折率を各々t0 、n0
とする時、レジスト膜内の設定される像面位置のレジス
トの上面からの距離dが、0<d≦t0 /n0を満た
すこと、レジストの厚さと屈折率を各々t0 、n0、
SiO2膜の厚さと屈折率を各々tS、nS、とする時
、レジストとSiO2膜より成る透光層とを含む層内に
設定される像面位置のレジストの上面からの距離dが、
0<d≦t0 /n0+tS/nSを満たすこと、が好
ましい。
That is, taking the wafers shown in FIGS. 3 and 4 as an example, the thickness and refractive index of the resist are set to t0 and n0, respectively.
When, the distance d of the set image plane position in the resist film from the top surface of the resist satisfies 0<d≦t0/n0, and the thickness and refractive index of the resist are respectively t0, n0,
When the thickness and refractive index of the SiO2 film are tS and nS, respectively, the distance d from the top surface of the resist to the image plane position set in the layer containing the resist and the light-transmitting layer made of the SiO2 film is:
It is preferable to satisfy 0<d≦t0/n0+tS/nS.

【0034】上記実施例では、Zステ−ジ8を駆動して
ウエハ−上下動することによりウエハ−に対する像面位
置を変化させていたが、投影レンズ系3の像面とレジス
ト4の相対位置を変化させる方法は他にもある。例えば
、(1)不図示のレチクルステ−ジを駆動してレチクル
2を投影レンズ系3の光軸方向に動かすことにより像面
位置を調整したり、(2)投影レンズ系3に空気レンズ
やプリズム機構の光路長変更部材を設け、この部材で光
路長を変えることにより像面位置を調整したり、(3)
照明系10からの照明光1の波長を変えることにより像
面位置を調整したり、(4)投影レンズ系3の少なくと
も一部のレンズを光軸方向に動かすことにより像面位置
を調整したり、(5)パタ−ンの投影を相異なる波長の
光を同時に使用して行なったり、(6)同じパタ−ンを
備える複数のレチクルを投影光学系の光軸方向に沿って
近接配置し、各レチクルのパタ−ン像を同時に投影した
りする。方法(2)の空気レンズは投影レンズ系3を構
成するレンズアセンブリの内の一対のレンズ間の空間を
密閉し、この空間の圧力を変えるものである。 又、方法(2)のプリズム機構は、一対のプリズムを互
いに斜面が対向するよう近接して配置し相対移動させる
ものである。又、方法(3)を、照明光1としてi線や
g線を用いる投影露光装置に適用する場合には、照明系
10中に可回転の干渉フィルタ−等を設け、照明光1の
波長を調整するといい。又、照明光1としてエキシマレ
−ザ−からのレ−ザ−光を用いる投影露光装置に適用す
る場合には、レ−ザ−共振器内の回折格子やエタロン等
を回転可能に支持し、照明光1の波長を調整するといい
。又、方法(5)、(6)は、双方とも、相異なる像面
位置で同時に回路パタ−ン像を投影する場合に適用され
る手法である。
In the above embodiment, the position of the image plane with respect to the wafer was changed by driving the Z stage 8 to move the wafer up and down, but the relative position of the image plane of the projection lens system 3 and the resist 4 There are other ways to change the. For example, (1) the image plane position can be adjusted by driving a reticle stage (not shown) to move the reticle 2 in the optical axis direction of the projection lens system 3, or (2) using an air lens or prism in the projection lens system 3. The optical path length changing member of the mechanism is provided, and by changing the optical path length with this member, the image plane position can be adjusted, (3)
Adjusting the image plane position by changing the wavelength of the illumination light 1 from the illumination system 10; (4) adjusting the image plane position by moving at least some lenses of the projection lens system 3 in the optical axis direction; (5) projecting a pattern using light of different wavelengths simultaneously; (6) arranging a plurality of reticles with the same pattern close to each other along the optical axis direction of the projection optical system; The pattern images of each reticle are projected simultaneously. The air lens of method (2) seals the space between a pair of lenses in the lens assembly constituting the projection lens system 3, and changes the pressure in this space. Further, in the prism mechanism of method (2), a pair of prisms are arranged close to each other so that their slopes face each other and are moved relative to each other. When method (3) is applied to a projection exposure apparatus that uses i-line or g-line as illumination light 1, a rotatable interference filter or the like is provided in illumination system 10 to adjust the wavelength of illumination light 1. It's good to adjust. In addition, when applied to a projection exposure apparatus that uses laser light from an excimer laser as the illumination light 1, a diffraction grating, an etalon, etc. in the laser resonator are rotatably supported, and the illumination light is It is best to adjust the wavelength of light 1. Furthermore, methods (5) and (6) are both methods that are applied when circuit pattern images are simultaneously projected at different image plane positions.

【0035】本発明において、パタ−ン像の投影は、超
高圧水銀等、レ−ザ−、X線源などからの放射された光
を、パタ−ンを備える被投影原板に照射し、この原板で
パタ−ンに従って透過又は反射せしめて投影光学系の瞳
に向けることにより行なう。この投影光学系は、上記実
施例の投影レンズ系3のようにレンズアセンブリより構
成されるものに限定されない。つまり、ミラ−アセンブ
リより構成されるもの、レンズ及びミラ−により構成さ
れるものも使用されうる。
In the present invention, a pattern image is projected by irradiating light emitted from ultra-high pressure mercury, a laser, an X-ray source, etc. onto a patterned original plate. This is done by transmitting or reflecting the light according to the pattern on the original plate and directing it to the pupil of the projection optical system. This projection optical system is not limited to one composed of a lens assembly like the projection lens system 3 of the above embodiment. In other words, a mirror assembly or a lens and mirror may be used.

【0036】又、本発明は、上述した如く、相異なる像
面位置で同時に回路パタ−ン像を投影するような形態も
含み、要は、投影光学系の像面に対するウエハ−等の基
板の相対位置を該投影光学系の光軸方向に複数設定し、
各々の位置で所定パタ−ンの像を基板上に投影して基板
を露光する場合、基板の感光層の光軸方向の複数位置又
は基板の感光層及び透明層より成る層の光軸方向の複数
位置に前記像面を一致させて露光すれば良い。
Furthermore, as described above, the present invention also includes a form in which circuit pattern images are simultaneously projected at different image plane positions; setting a plurality of relative positions in the optical axis direction of the projection optical system;
When exposing a substrate by projecting an image of a predetermined pattern onto the substrate at each position, multiple positions in the optical axis direction of the photosensitive layer of the substrate or in the optical axis direction of the layer consisting of the photosensitive layer and the transparent layer of the substrate are used. Exposure may be performed by aligning the image plane at a plurality of positions.

【0037】[0037]

【発明の効果】以上、本発明によれば、フォ−カスした
パタ−ン像で感光層を露光する割合を従来法よりも増加
させることができ、感光層に鮮明なパタ−ンをプリント
することが可能になる。従って、本露光方法を半導体デ
バイスの製造に適用することにより、良質の半導体デバ
イスを製造することが可能になる。
[Effects of the Invention] As described above, according to the present invention, the ratio of exposing the photosensitive layer with a focused pattern image can be increased compared to the conventional method, and a clear pattern can be printed on the photosensitive layer. becomes possible. Therefore, by applying this exposure method to the manufacture of semiconductor devices, it becomes possible to manufacture high quality semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】基板上のレジスト膜を露光した時のレジストの
光学特性の経時変化を示す説明図である。
FIG. 1 is an explanatory diagram showing changes over time in optical properties of a resist when a resist film on a substrate is exposed to light.

【図2】本発明の露光方法が適用される半導体デバイス
を製造する為の投影露光装置の一例を示す図である。
FIG. 2 is a diagram showing an example of a projection exposure apparatus for manufacturing semiconductor devices to which the exposure method of the present invention is applied.

【図3】図2の装置を使用し本発明の露光方法によるパ
タ−ンのプリントを行なう例を示す説明図であり、(A
)は像面とレジスト上面とを一致させた状態で投影露光
を行なう様子を示す図、(B)は像面とレジスト内の真
ん中とを一致させた状態で投影露光を行なう様子を示す
図、(C)は像面とレジスト下面とを一致させた状態で
投影露光を行なう様子を示す図である。
3 is an explanatory diagram showing an example of printing a pattern by the exposure method of the present invention using the apparatus shown in FIG.
) is a diagram showing how projection exposure is performed with the image plane and the top surface of the resist aligned; (B) is a diagram showing how projection exposure is performed with the image plane and the center of the resist aligned; (C) is a diagram showing how projection exposure is performed with the image plane and the lower surface of the resist aligned.

【図4】ウエハ−の他の構造例を示す図である。FIG. 4 is a diagram showing another example of the structure of the wafer.

【符号の説明】[Explanation of symbols]

2  レチクル 3  投影レンズ系 4  レジスト 5  ウエハ−基板 11  SiO2 40  レジスト上面 50  レジスト下面 2 Reticle 3 Projection lens system 4 Resist 5 Wafer substrate 11 SiO2 40 Top surface of resist 50 Bottom surface of resist

Claims (23)

【特許請求の範囲】[Claims] 【請求項1】  投影光学系の像面に対する被露光基板
の相対位置を該投影光学系の光軸方向に複数設定し、各
々の位置で所定パタ−ンの像を該被露光基板上に投影し
て該被露光基板を露光する方法において、前記被露光基
板の感光層の前記光軸方向の複数位置に前記像面を一致
させて露光することを特徴とする露光方法。
1. A plurality of relative positions of the exposed substrate with respect to the image plane of the projection optical system are set in the optical axis direction of the projection optical system, and an image of a predetermined pattern is projected onto the exposed substrate at each position. An exposure method characterized in that the image plane is aligned with a plurality of positions in the optical axis direction of a photosensitive layer of the exposed substrate to expose the exposed substrate.
【請求項2】  前記感光層の光軸方向の複数位置は前
記感光層の上面側から順に第1、第2位置を含み、前記
所定パタ−ン像を、該第1、第2位置の順に順次投影す
ることを特徴とする請求項1の露光方法。
2. The plurality of positions in the optical axis direction of the photosensitive layer include first and second positions in order from the upper surface side of the photosensitive layer, and the predetermined pattern image is placed in the first and second positions in order. 2. The exposure method according to claim 1, wherein the projections are performed sequentially.
【請求項3】  前記感光層の光軸方向の複数位置の少
なくとも一つが前記感光層内に設定され、該少なくとも
一つの位置の前記感光層の上面からの距離をd、前記感
光層の厚さと屈折率を各々t0 、n0とする時、0<
d≦t0 /n0 なる条件を満たすことを特徴とする請求項1、2の露光
方法。
3. At least one of a plurality of positions in the optical axis direction of the photosensitive layer is set within the photosensitive layer, and the distance of the at least one position from the upper surface of the photosensitive layer is d, and the thickness of the photosensitive layer is When the refractive index is t0 and n0, respectively, 0<
The exposure method according to claim 1 or 2, characterized in that the following condition is satisfied: d≦t0 /n0.
【請求項4】  前記感光層の下面を前記像面に一致さ
せて前記所定パタ−ン像の投影を行うことなく露光する
ことを特徴とする請求項1−3の露光方法。
4. The exposure method according to claim 1, wherein the exposure is performed without projecting the predetermined pattern image while aligning the lower surface of the photosensitive layer with the image plane.
【請求項5】  前記感光層の上面を前記像面に一致さ
せて前記所定パタ−ン像の投影を行うことなく露光する
ことを特徴とする請求項1−4の露光方法。
5. The exposure method according to claim 1, wherein the exposure is performed without projecting the predetermined pattern image while aligning the upper surface of the photosensitive layer with the image plane.
【請求項6】  前記第1位置が前記感光層の上面であ
ることを特徴とする請求項2の露光方法。
6. The exposure method according to claim 2, wherein the first position is an upper surface of the photosensitive layer.
【請求項7】  前記第1、第2位置が前記感光層内に
あることを特徴とする請求項2の露光方法。
7. The exposure method according to claim 2, wherein the first and second positions are within the photosensitive layer.
【請求項8】  投影光学系の像面に対するウエハ−の
相対位置を該投影光学系の光軸方向に複数設定し、各々
の位置で回路パタ−ン像を該ウエハ−上に投影して該ウ
エハ−を露光した後、該ウエハ−を現像し、半導体デバ
イスを製造する方法において、前記ウエハ−のレジスト
膜の前記光軸方向の複数位置に前記像面を一致させて露
光することを特徴とする半導体デバイスの製造方法。
8. A plurality of relative positions of the wafer with respect to the image plane of the projection optical system are set in the optical axis direction of the projection optical system, and a circuit pattern image is projected onto the wafer at each position. After exposing a wafer, the wafer is developed to produce a semiconductor device, in which the image plane is aligned with a plurality of positions in the optical axis direction of the resist film of the wafer, and the exposure is performed. A method for manufacturing semiconductor devices.
【請求項9】  前記レジスト膜の光軸方向の複数位置
は前記レジスト膜の上面側から順に第1、第2位置を含
み、前記回路パタ−ン像を、該第1、第2位置の順に順
次投影することを特徴とする請求項8の半導体デバイス
の製造方法。
9. The plurality of positions in the optical axis direction of the resist film include first and second positions in order from the upper surface side of the resist film, and the circuit pattern image is formed in the order of the first and second positions. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the projections are performed sequentially.
【請求項10】  前記レジスト膜の光軸方向の複数位
置の少なくとも一つが前記レジスト膜内に設定され、該
少なくとも一つの位置の前記レジスト膜の上面からの距
離をd、前記レジスト膜の厚さと屈折率を各々t0 、
n0とする時、 0<d≦t0 /n0 なる条件を満たすことを特徴とする請求項8、9の半導
体デバイスの製造方法。
10. At least one of a plurality of positions in the optical axis direction of the resist film is set within the resist film, and a distance of the at least one position from the upper surface of the resist film is d, and a thickness of the resist film is set. The refractive index is t0,
10. The method of manufacturing a semiconductor device according to claim 8, characterized in that when n0, the following condition is satisfied: 0<d≦t0/n0.
【請求項11】  前記レジスト膜の下面を前記像面に
一致させて前記回路パタ−ン像の投影を行うことなく露
光することを特徴とする請求項8−10の半導体デバイ
スの製造方法。
11. The method of manufacturing a semiconductor device according to claim 8, wherein the exposure is performed without projecting the circuit pattern image with the lower surface of the resist film aligned with the image plane.
【請求項12】  前記レジスト膜の上面を前記像面に
一致させて前記回路パタ−ン像の投影を行うことなく露
光することを特徴とする請求項8−11の半導体デバイ
スの製造方法。
12. The method of manufacturing a semiconductor device according to claim 8, wherein the exposure is performed without projecting the circuit pattern image while aligning the upper surface of the resist film with the image plane.
【請求項13】  前記第1位置が前記レジスト膜の上
面であることを特徴とする請求項9の半導体デバイスの
製造方法。
13. The method of manufacturing a semiconductor device according to claim 9, wherein the first position is an upper surface of the resist film.
【請求項14】  前記第1、第2位置が前記レジスト
膜内にあることを特徴とする請求項9の半導体デバイス
の製造方法。
14. The method of manufacturing a semiconductor device according to claim 9, wherein the first and second positions are within the resist film.
【請求項15】  投影光学系の像面に対するウエハ−
の相対位置を該投影光学系の光軸方向に複数設定し、各
々の位置で回路パタ−ン像を該ウエハ−上に投影して該
ウエハ−を露光した後、該ウエハ−を現像し、半導体デ
バイスを製造する方法において、前記ウエハ−のレジス
ト膜及び透明膜を含む層の前記光軸方向の複数位置に前
記像面を一致させて露光することを特徴とする半導体デ
バイス製造方法。
15. The wafer on the image plane of the projection optical system.
A plurality of relative positions are set in the optical axis direction of the projection optical system, and a circuit pattern image is projected onto the wafer at each position to expose the wafer, and then the wafer is developed; 1. A method of manufacturing a semiconductor device, wherein exposure is performed by aligning the image plane with a plurality of positions in the optical axis direction of a layer including a resist film and a transparent film of the wafer.
【請求項16】  前記層の光軸方向の複数位置は前記
層の上面側から順に第1、第2位置を含み、前記回路パ
タ−ン像を、該第1、第2位置の順に順次投影すること
を特徴とする請求項15の半導体デバイスの製造方法。
16. The plurality of positions in the optical axis direction of the layer include first and second positions in order from the upper surface side of the layer, and the circuit pattern image is sequentially projected at the first and second positions. 16. The method of manufacturing a semiconductor device according to claim 15.
【請求項17】  前記層の光軸方向の複数位置の少な
くとも一つが前記層内に設定され、該少なくとも一つの
位置の前記層の上面からの距離をd、前記レジスト膜の
厚さと屈折率を各々t0 、n0、前記透明膜の厚さと
屈折率を各々tS、nS、とする時、 0<d≦t0 /n0+tS/nS なる条件を満たすことを特徴とする請求項15、16の
半導体デバイスの製造方法。
17. At least one of a plurality of positions in the optical axis direction of the layer is set within the layer, the distance of the at least one position from the upper surface of the layer is d, and the thickness and refractive index of the resist film are 17. The semiconductor device according to claim 15, characterized in that when t0 and n0 respectively, and the thickness and refractive index of the transparent film are tS and nS, respectively, the following condition is satisfied: 0<d≦t0/n0+tS/nS Production method.
【請求項18】  前記層の下面を前記像面に一致させ
て前記回路パタ−ン像の投影を行うことなく露光するこ
とを特徴とする請求項15−17の半導体デバイスの製
造方法。
18. The method of manufacturing a semiconductor device according to claim 15, wherein the exposure is performed without projecting the circuit pattern image while aligning the lower surface of the layer with the image plane.
【請求項19】  前記層の上面を前記像面に一致させ
て前記回路パタ−ン像の投影を行うことなく露光するこ
とを特徴とする請求項15−18の半導体デバイスの製
造方法。
19. The method of manufacturing a semiconductor device according to claim 15, wherein the exposure is performed without projecting the circuit pattern image with the upper surface of the layer aligned with the image plane.
【請求項20】  前記第1位置が前記層の上面である
ことを特徴とする請求項16の半導体デバイスの製造方
法。
20. The method of manufacturing a semiconductor device according to claim 16, wherein the first location is a top surface of the layer.
【請求項21】  前記第1、第2位置が前記層内にあ
ることを特徴とする請求項16の半導体デバイスの製造
方法。
21. The method of manufacturing a semiconductor device according to claim 16, wherein the first and second locations are within the layer.
【請求項22】  前記第1、第2位置が前記レジスト
膜内にあることを特徴とする請求項21の半導体デバイ
スの製造方法。
22. The method of manufacturing a semiconductor device according to claim 21, wherein the first and second positions are within the resist film.
【請求項23】  前記透明膜がSiO2を含むことを
特徴とする請求項22の半導体デバイス製造方法。
23. The method of manufacturing a semiconductor device according to claim 22, wherein the transparent film contains SiO2.
JP3085385A 1991-04-17 1991-04-17 Exposure method and manufacture of semiconductor device using that method Pending JPH04318913A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3085385A JPH04318913A (en) 1991-04-17 1991-04-17 Exposure method and manufacture of semiconductor device using that method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3085385A JPH04318913A (en) 1991-04-17 1991-04-17 Exposure method and manufacture of semiconductor device using that method

Publications (1)

Publication Number Publication Date
JPH04318913A true JPH04318913A (en) 1992-11-10

Family

ID=13857276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3085385A Pending JPH04318913A (en) 1991-04-17 1991-04-17 Exposure method and manufacture of semiconductor device using that method

Country Status (1)

Country Link
JP (1) JPH04318913A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104062853A (en) * 2013-03-21 2014-09-24 上海微电子装备有限公司 Vertically dynamic exposure method and apparatus of lithography equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104062853A (en) * 2013-03-21 2014-09-24 上海微电子装备有限公司 Vertically dynamic exposure method and apparatus of lithography equipment

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