JPH04317593A - Controller for motor - Google Patents

Controller for motor

Info

Publication number
JPH04317593A
JPH04317593A JP3080151A JP8015191A JPH04317593A JP H04317593 A JPH04317593 A JP H04317593A JP 3080151 A JP3080151 A JP 3080151A JP 8015191 A JP8015191 A JP 8015191A JP H04317593 A JPH04317593 A JP H04317593A
Authority
JP
Japan
Prior art keywords
phase
pwm signal
time
driver
pulse width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3080151A
Other languages
Japanese (ja)
Inventor
Masaki Tanaka
雅樹 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Corp
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Corp, Omron Tateisi Electronics Co filed Critical Omron Corp
Priority to JP3080151A priority Critical patent/JPH04317593A/en
Publication of JPH04317593A publication Critical patent/JPH04317593A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Control Of Ac Motors In General (AREA)
  • Inverter Devices (AREA)

Abstract

PURPOSE:To provide a motor controller in which inconvenience such as an increase in an irregularity of a torque caused by a current waveform distortion, an increase in an irregularity of a rotating speed, etc., is eliminated by preventing simultaneous occurrence of periods of dead times in two or more phases. CONSTITUTION:A central arithmetic processor 10 calculates an A-phase PWM signal, a B-phase PWM signal, a C-phase PWM signal to be supplied to phases, sequentially shift them by a short-circuiting preventing time (dead time), and adds them to an A-phase driver 11, a B-phase driver 12, a C-phase driver 13. The drivers 11, 12, 13 respectively form drive signals UA and DA, UB and DB, UC and DC having dead times corresponding to the A-phase, B-phase, C-phase signals.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は同期モータ、誘導モー
タなどの制御に好適なモータ制御装置に関し、特に直流
電源短絡を防止するために各層のパルス幅変調信号に設
けられた短絡防止時間の重なりによる電流波形の歪みに
起因して生じるトルクむら、速度むらの改善されたモー
タ制御装置に関する。
[Industrial Application Field] This invention relates to a motor control device suitable for controlling synchronous motors, induction motors, etc., and in particular, the present invention relates to a motor control device suitable for controlling synchronous motors, induction motors, etc. The present invention relates to a motor control device that improves torque unevenness and speed unevenness caused by distortion of current waveform.

【0002】0002

【従来の技術】従来、例えば3相モータを制御するモー
タ制御装置としては、3相電圧形PWMインバータ(直
流−交流変換回路)が知られているが、この3相電圧形
PWMインバータは各相の直流電源短絡を防止するため
に各相のパルス幅変調信号に短絡防止時間(以下デッド
タイムという)が設けられている。すなわち、3相電圧
形PWMインバータにおいては、各相に対して2個の計
6個のトランジスタからなるスイッチが設けられており
、各相の2個のトランジスタは各相に加えられるPWM
(パルス幅変調)信号に対応して交互にオンオフするが
、各トランジスタのオンオフ時間のばらつきのために各
層の2個のトランジスタが同時にオンして直流電源短絡
が発生することを防止するために、各相の2個のトラン
ジスタを同時にオフにするための短絡防止時間、すなわ
ちデッドタイムが各相のPWM信号に設けられている。
[Prior Art] Conventionally, a three-phase voltage type PWM inverter (DC-AC conversion circuit) has been known as a motor control device for controlling, for example, a three-phase motor. In order to prevent short-circuiting of the DC power supply, a short-circuit prevention time (hereinafter referred to as dead time) is provided in the pulse width modulation signal of each phase. That is, in a three-phase voltage source PWM inverter, a switch consisting of six transistors, two for each phase, is provided, and the two transistors for each phase control the PWM applied to each phase.
(Pulse Width Modulation) They are turned on and off alternately in response to the signal, but in order to prevent two transistors in each layer from turning on at the same time due to variations in the on/off time of each transistor, causing a short circuit in the DC power supply. A short-circuit prevention time, ie, a dead time, for turning off two transistors of each phase simultaneously is provided in the PWM signal of each phase.

【0003】0003

【発明が解決しようとする課題】しかしながら、上記の
如き従来のモータ制御装置においてはデッドタイムの期
間が2つ以上の相で同時に起こると、電流波形の歪みが
大きくなり、この電流波形歪みに起因してトルクむらの
増大、回転速度むらの増大などの種々の不都合が発生す
るという問題があった。
[Problems to be Solved by the Invention] However, in the conventional motor control device as described above, when the dead time period occurs in two or more phases at the same time, distortion of the current waveform becomes large. However, there has been a problem in that various problems such as an increase in torque unevenness and an increase in rotational speed unevenness occur.

【0004】そこで、この発明はデッドタイムの期間が
2つ以上の相で同時に起こらにようにすることにより電
流波形歪みに起因するトルクむらの増大、回転速度むら
の増大などの不都合を抑止したモータ制御装置を提供す
ることを目的とする。
Therefore, the present invention provides a motor that suppresses disadvantages such as increased torque unevenness and increased rotational speed unevenness caused by current waveform distortion by preventing dead time periods from occurring simultaneously in two or more phases. The purpose is to provide a control device.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、この発明は、複数相モータの各相にそれぞれパルス
幅変調信号を供給するとともに、各相のパルス幅変調信
号に直流電源短絡を防止するための短絡防止時間を設け
たモータ制御装置において、前記各相のパルス幅変調信
号を前記短絡防止時間だけ順次ずらす制御手段を設けた
ことを特徴とする。
[Means for Solving the Problems] In order to achieve the above object, the present invention supplies a pulse width modulation signal to each phase of a multi-phase motor, and also provides a direct current power supply short circuit to the pulse width modulation signal of each phase. The motor control device is provided with a short circuit prevention time for preventing short circuits, characterized in that a control means is provided for sequentially shifting the pulse width modulated signals of each phase by the short circuit prevention time.

【0006】[0006]

【作用】各相に供給されるパルス幅変調信号は、制御手
段により、それぞれ短絡防止時間だけ順次ずらされ、こ
れにより2つ以上の相で短絡防止時間が同時に生じるこ
とはなくなり、電流波形歪みに起因するトルクむらの増
大、回転速度むらの増大などを抑止する。
[Operation] The pulse width modulation signals supplied to each phase are sequentially shifted by the short-circuit prevention time by the control means, so that the short-circuit prevention time does not occur simultaneously in two or more phases, resulting in current waveform distortion. This suppresses the resulting increase in torque unevenness and rotational speed unevenness.

【0007】[0007]

【実施例】以下、この発明を図面に基いて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below with reference to the drawings.

【0008】図1は、この発明のモータ制御装置の一実
施例をブロック図で示したものである。この実施例のモ
ータ制御装置は3相モータを制御対象としており、この
3相の制御回路が図2に示される。
FIG. 1 is a block diagram showing an embodiment of a motor control device according to the present invention. The motor control device of this embodiment controls a three-phase motor, and a three-phase control circuit is shown in FIG.

【0009】図1において、中央演算処理装置(CPU
)10は、所望のモータ速度、あるいはモータトルクを
得るために必要な各相のPWM(パルス幅変調)信号、
すなわち、A相PWM信号、B相PWM信号、C相PW
M信号を計算し、A相PWM信号をA相ドライバ11に
加え、B相PWM信号をB相ドライバ12に加え、C相
PWM信号をC相ドライバ13に加える。
In FIG. 1, a central processing unit (CPU
) 10 is a PWM (pulse width modulation) signal for each phase necessary to obtain the desired motor speed or motor torque;
That is, A-phase PWM signal, B-phase PWM signal, C-phase PW
The M signal is calculated, and the A-phase PWM signal is applied to the A-phase driver 11, the B-phase PWM signal is applied to the B-phase driver 12, and the C-phase PWM signal is applied to the C-phase driver 13.

【0010】A相ドライバ11は、A相PWM信号から
デッドタイムを有する2つの駆動信号UAおよびDAを
形成し、これをパワー増幅して出力する。
The A-phase driver 11 forms two drive signals UA and DA having a dead time from the A-phase PWM signal, amplifies their power, and outputs them.

【0011】また、B相ドライバ12は、B相PWM信
号からデッドタイムを有する2つの駆動信号UBおよび
DBを形成し、これをパワー増幅して出力する。
Further, the B-phase driver 12 forms two drive signals UB and DB having a dead time from the B-phase PWM signal, amplifies their power, and outputs them.

【0012】また、C相ドライバ13は、C相PWM信
号からデッドタイムを有する2つの駆動信号UCおよび
DCを形成し、これをパワー増幅して出力する。
Further, the C-phase driver 13 forms two drive signals UC and DC having a dead time from the C-phase PWM signal, amplifies their power, and outputs them.

【0013】図2において、この実施例の制御回路は、
3相交流電源21、この3相交流電源21から出力され
る3相交流を直流に整流する6個のダイオードからなる
ダイオードブリッジ回路22、ダイオードブリッジ回路
22の出力を平滑するための平滑コンデンサ23、6個
のトランジスタTR1,TR2,TR3,TR4,TR
5,TR6からなるスイッチング回路24、このスイッ
チング回路24により各相の電流が制御される3相モー
タ25から構成されている。
In FIG. 2, the control circuit of this embodiment is as follows:
3-phase AC power supply 21, a diode bridge circuit 22 consisting of six diodes that rectifies the 3-phase AC output from the 3-phase AC power supply 21 into DC, a smoothing capacitor 23 for smoothing the output of the diode bridge circuit 22, 6 transistors TR1, TR2, TR3, TR4, TR
5 and TR6, and a three-phase motor 25 in which the current of each phase is controlled by the switching circuit 24.

【0014】ここで、図1に示したA相ドライバ11か
ら出力される2つの駆動信号UAおよび及びDAは図2
に示したスイッチング回路24のトランジスタTR1,
TR2のベースにスイッチング信号としてそれぞれ加え
られ、図1に示したB相ドライバ12から出力される2
つの駆動信号UB及びDBは図2に示したスイッチング
回路24のトランジスタTR3,TR4のベースにスイ
ッチング信号としてそれぞれ加えられ、図1に示したC
相ドライバ13から出力される2つの駆動信号UC及び
DCは図2に示したスイッチング回路24のトランジス
タTR5,TR6のベースにスイッチング信号としてそ
れぞれ加えられる。
Here, the two drive signals UA and DA output from the A-phase driver 11 shown in FIG. 1 are as shown in FIG.
The transistor TR1 of the switching circuit 24 shown in FIG.
2 is added as a switching signal to the base of TR2 and output from the B-phase driver 12 shown in FIG.
The two drive signals UB and DB are applied as switching signals to the bases of transistors TR3 and TR4 of the switching circuit 24 shown in FIG.
Two drive signals UC and DC output from the phase driver 13 are applied as switching signals to the bases of transistors TR5 and TR6 of the switching circuit 24 shown in FIG. 2, respectively.

【0015】次に、この実施例の動作を図3に示したタ
イミングチャートを参照してさらに説明する。
Next, the operation of this embodiment will be further explained with reference to the timing chart shown in FIG.

【0016】図1に示したCPU10は、各層のPWM
信号、すなわち、A相PWM信号、B相PWM信号、C
相PWM信号を形成出力するが、ここで、CPU10は
各相のPWM信号のパルス幅を調べて、そのパルス幅が
短い順にデッドタイムに相当する時間ずつ順次ずらして
出力する。この状態が図3の(a),(d),(g)に
示される。なお、図3において、TA ,TB ,TC
はA相PWM信号、B相PWM信号、C相PWM信号の
それぞれのパルス幅を示し、図3の前半のPWM周期に
おいては各PWM信号のパルス幅がTA <TB <T
C の場合を示し、後半のPWM周期においては各PW
M信号のパルス幅がTB <TC <TA の場合を示
している。
The CPU 10 shown in FIG.
signals, i.e., A-phase PWM signal, B-phase PWM signal, C
A phase PWM signal is formed and output. Here, the CPU 10 examines the pulse width of the PWM signal of each phase, and sequentially shifts the pulse width by a time corresponding to the dead time and outputs the signal in descending order of the pulse width. This state is shown in FIGS. 3(a), (d), and (g). In addition, in FIG. 3, TA, TB, TC
indicates the pulse width of each of the A-phase PWM signal, B-phase PWM signal, and C-phase PWM signal, and in the first half PWM period of FIG. 3, the pulse width of each PWM signal is TA < TB < T
In the latter half of the PWM cycle, each PWM
The case where the pulse width of the M signal is TB < TC < TA is shown.

【0017】図3から明らかなように、前半のPWM周
期においては各PWM信号のパルス幅がTA <TB 
<TC の関係にあるので、この前半のPWM周期の開
始時点で、まず、A相PWM信号が出力され(図3(a
)参照)、続いて、このA相PWM信号からデッドタイ
ムに相当する時間tだけ遅延してB相PWM信号が出力
され(図3(d)参照)、続いて、このB相PWM信号
からデッドタイムに相当する時間tだけ遅延して、すな
わち、A相PWM信号からデッドタイムに相当する時間
tの2倍の時間2tだけ遅延してC相PWM信号が出力
される(図3(g)参照)。
As is clear from FIG. 3, in the first half PWM cycle, the pulse width of each PWM signal is TA < TB
<TC, so at the start of this first half PWM cycle, the A-phase PWM signal is first output (see Figure 3(a)).
), then the B-phase PWM signal is output with a delay of time t corresponding to the dead time from this A-phase PWM signal (see Fig. 3(d)), and then the B-phase PWM signal is The C-phase PWM signal is output with a delay of a time t corresponding to the dead time, that is, a delay of a time 2t, which is twice the time t corresponding to the dead time, from the A-phase PWM signal (see Fig. 3 (g)). ).

【0018】また、後半のPWM周期においては各PW
M信号のパルス幅がTB <TC <TA の関係にあ
るので、この後半のPWM周期の開始時点で、まず、B
相PWM信号が出力され(図3(d)参照)、続いて、
このB相PWM信号からデッドタイムに相当する時間t
だけ遅延してC相PWM信号が出力され(図3(g)参
照)、続いて、このC相PWM信号からデッドタイムに
相当する時間tだけ遅延して、すなわち、B相PWM信
号からデッドタイムに相当する時間tの2倍の時間2t
だけ遅延してA相PWM信号が出力される(図3(a)
参照)。
[0018] Also, in the latter half of the PWM cycle, each PWM
Since the pulse width of the M signal is in the relationship TB < TC < TA, at the start of this second half PWM cycle, the B
A phase PWM signal is output (see FIG. 3(d)), and then,
The time t corresponding to the dead time from this B-phase PWM signal
The C-phase PWM signal is output with a delay of 100 min (see Fig. 3 (g)), and then the C-phase PWM signal is delayed by a time t corresponding to the dead time, that is, the dead time is output from the B-phase PWM signal. A time 2t which is twice the time t corresponding to
The A-phase PWM signal is output with a delay of
reference).

【0019】このA相PWM信号、B相PWM信号、C
相PWM信号はそれぞれA相ドライバ11、B相ドライ
バ12、C相ドライバ13に供給され、A相ドライバ1
1ではA相PWM信号に対応する2つの駆動信号UAお
よびDAを形成し(図3(b),(c)参照)、B相ド
ライバ12ではB相PWM信号に対応する2つの駆動信
号UBおよびDBを形成し(図3(e),(f)参照)
、C相ドライバ13ではC相PWM信号に対応する2つ
の駆動信号UCおよびDCを形成する(図3(h),(
i)参照)。ここで、A相ドライバ11で形成される2
つの駆動信号UAおよびDAには、この2つの駆動信号
UAおよびDAが同時にローレベルとなるデットタイム
が形成され、B相ドライバ12で形成される2つの駆動
信号UBおよびDBには、この2つの駆動信号UBおよ
びDBが同時にローレベルとなるデットタイムが形成さ
れ、また、C相ドライバ13で形成される2つの駆動信
号UCおよびDCにも、この2つの駆動信号UCおよび
DCが同時にローレベルとなるデットタイムが形成され
る。
[0019] The A-phase PWM signal, the B-phase PWM signal, and the C
The phase PWM signals are respectively supplied to an A-phase driver 11, a B-phase driver 12, and a C-phase driver 13.
1 forms two drive signals UA and DA corresponding to the A-phase PWM signal (see FIGS. 3(b) and (c)), and the B-phase driver 12 forms two drive signals UB and DA corresponding to the B-phase PWM signal. Form a DB (see Figures 3(e) and (f))
, the C-phase driver 13 forms two drive signals UC and DC corresponding to the C-phase PWM signal (Fig. 3(h), (
(see i)). Here, 2 formed by the A-phase driver 11
A dead time is formed in the two drive signals UA and DA in which the two drive signals UA and DA become low level at the same time, and a dead time is formed in the two drive signals UB and DB formed by the B-phase driver 12. A dead time is formed in which the drive signals UB and DB are at low level at the same time, and also in the two drive signals UC and DC generated by the C-phase driver 13, these two drive signals UC and DC are at low level at the same time. A dead time is formed.

【0020】したがって、このような構成によると、各
相のデットタイムが同時に生じることはなく、これによ
り2つ以上の相でデットタイムが同時に生じることによ
る電流波形の歪みも生じない。そして、この電流波形の
歪みに起因するトルクむらの増大、速度むらの増大も抑
制される。
[0020] Therefore, according to such a configuration, dead time of each phase does not occur simultaneously, and therefore, distortion of the current waveform due to simultaneous occurrence of dead time of two or more phases does not occur. Further, increases in torque unevenness and speed unevenness due to distortion of this current waveform are also suppressed.

【0021】[0021]

【発明の効果】以上説明したように、この発明によれば
、各相に供給されるパルス幅変調信号をそれぞれ短絡防
止時間だけ順次ずらすように構成したので、、これによ
り2つ以上の相で短絡防止時間が同時に生じることはな
くなり、電流波形歪みに起因するトルクむらの増大、回
転速度むらの増大などを確実に抑止することができると
いう効果を奏する。
[Effects of the Invention] As explained above, according to the present invention, the pulse width modulation signals supplied to each phase are sequentially shifted by the short circuit prevention time. The short-circuit prevention time no longer occurs at the same time, and it is possible to reliably suppress increases in torque unevenness, rotational speed unevenness, etc. caused by current waveform distortion.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】この発明のモータ制御装置の一実施例を示すブ
ロック図。
FIG. 1 is a block diagram showing an embodiment of a motor control device of the present invention.

【図2】図1に示した実施例で用いる制御回路の一例を
示す回路図。
FIG. 2 is a circuit diagram showing an example of a control circuit used in the embodiment shown in FIG. 1;

【図3】図1に示した実施例の動作を説明するタイミン
グチャート。
FIG. 3 is a timing chart explaining the operation of the embodiment shown in FIG. 1;

【符号の説明】[Explanation of symbols]

10    中央演算処理装置(CPU)11    
A相ドライバ 12    B相ドライバ 13    C相ドライバ 21    3相交流電源 22    ダイオードブリッジ 23    平滑コンデンサ 24    スイッチング回路 25    3相モータ
10 Central processing unit (CPU) 11
A-phase driver 12 B-phase driver 13 C-phase driver 21 3-phase AC power supply 22 Diode bridge 23 Smoothing capacitor 24 Switching circuit 25 3-phase motor

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】複数相モータの各相にそれぞれパルス幅変
調信号を供給するとともに、各相のパルス幅変調信号に
直流電源短絡を防止するための短絡防止時間を設けたモ
ータ制御装置において、前記各相のパルス幅変調信号を
前記短絡防止時間だけ順次ずらす制御手段を設けたこと
を特徴とするモータ制御装置。
1. A motor control device that supplies a pulse width modulation signal to each phase of a multi-phase motor, and provides a short circuit prevention time for the pulse width modulation signal of each phase to prevent short circuits in the DC power supply. A motor control device comprising a control means for sequentially shifting the pulse width modulation signal of each phase by the short circuit prevention time.
JP3080151A 1991-04-12 1991-04-12 Controller for motor Withdrawn JPH04317593A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3080151A JPH04317593A (en) 1991-04-12 1991-04-12 Controller for motor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3080151A JPH04317593A (en) 1991-04-12 1991-04-12 Controller for motor

Publications (1)

Publication Number Publication Date
JPH04317593A true JPH04317593A (en) 1992-11-09

Family

ID=13710292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3080151A Withdrawn JPH04317593A (en) 1991-04-12 1991-04-12 Controller for motor

Country Status (1)

Country Link
JP (1) JPH04317593A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100466445C (en) * 2004-05-26 2009-03-04 上海磁浮交通工程技术研究中心 Encoding circuit for triggering signals of PWM three level inverter and control of compensation of its dead zone
JP2013034334A (en) * 2011-08-03 2013-02-14 Denso Corp Controller for rotary machine

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100466445C (en) * 2004-05-26 2009-03-04 上海磁浮交通工程技术研究中心 Encoding circuit for triggering signals of PWM three level inverter and control of compensation of its dead zone
JP2013034334A (en) * 2011-08-03 2013-02-14 Denso Corp Controller for rotary machine

Similar Documents

Publication Publication Date Title
JP3716534B2 (en) Motor control device and electric vehicle
JP2002247888A (en) Torque ripple reduction method for motor
JP4226224B2 (en) Inverter device
JPH11155297A (en) Motor driving device
JP2000350476A (en) Dc-ac power conversion circuit
JPH04317593A (en) Controller for motor
JP3567440B2 (en) Inverter-driven AC motor braking method
JPH05308778A (en) Inverter for driving electric car
JP3611075B2 (en) Single-phase input 3-phase output power conversion circuit
KR100308005B1 (en) Position sensing device of sensorless and brushless direct current(bldc) motor without sensor
JP3549312B2 (en) Inverter device
JP2003324986A (en) Control method for three-phase brushless dc motor
JP2004364443A (en) Pulse-width modulated inverter device
JP2841879B2 (en) Inverter DC braking control method
JP2781288B2 (en) AC electric vehicle control device
JP2004312822A (en) Two-phase modulation controlling inverter
JP3775553B2 (en) Control method of brushless DC motor
JPS611289A (en) Controller for motor
JP2003339189A (en) Control apparatus, method, and control program for three-phase induction motor
JP3633564B2 (en) Inverter device for induction machine drive
JPH0824426B2 (en) Pulse width modulation type inverter device
JPH09252593A (en) Inverter device
JPH0638539A (en) Power source
JP2000116173A (en) Brushless dc motor and its speed-control method
JP2002034279A (en) Method for controlling brushelss motor and device thereof

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19980711