JPH04315894A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent a sense amplifier from giving damage to data caused by a multiple selection at a time of an address switching. CONSTITUTION:This memory is provided with an address decoder 2 for making selection signals YS 1 and YS 2 from the power source of a power source voltage Vdd 1 inputted via a MOS transistor Q 25 at the time of a writing operation and for making the selection signals YS 1 and YS 2 from the power source of a power source voltage Vdd 2 whose power source voltage are lower than those of the power source voltage Vdd 1 inputted via a MOS transistor Q 26 at the time of a reading operation.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory configured to selectively input and output data on a plurality of bit lines via one input/output bus.

0002

2. Description of the Related Art Conventionally, a semiconductor memory of this type has a plurality of pairs of bit lines for respectively transmitting write data and read data of a plurality of memory cells, as shown in FIG. 5 as a first example. BL11, BL12, BL21,
BL22 and their paired bit lines BL11 and BL1
2. A plurality of sense amplifiers SA1, SA2 that respectively amplify the data transmitted to BL21, BL22, and each bit line BL11, BL12, BL21 from the outside.
, BL22 and each of these bit lines BL
11, BL12, BL21, BL22 and input/output buses B1, B2 that transmit the read data to the outside, and respective bit lines BL11, BL12, BL21, BL2 that form pairs.
2 and a corresponding selection signal YS1 provided in correspondence with each other.
, YS2 to turn on and off to control the connection between the corresponding bit line and the input/output buses B1, B2.
4, an input/output gate circuit 1 having an address signal (A1
A2, .

[0003] Each address decoder 2c is a MOS
It is formed of a plurality of basic decoding circuits consisting of transistors Q21 to Q24 and outputting corresponding selection signals YS1 and YS2, and each of these basic decoding circuits is directly and commonly supplied with a power supply voltage Vdd from the outside. . Therefore, the active levels of selection signals YS1 and YS2 are:
The level was the same during both write and read operations.

As a second example, instead of the input/output gate circuit 1, the gate is connected to each bit line BL11, BL12,
A plurality of first transistors are connected to BL21 and BL22, respectively, and one of their sources and drains are connected to input/output buses B1 and B2, respectively, and selection signals YS1 and YS2 are input to their gates, respectively. There are configurations that include a plurality of second transistors that are turned on and off by the corresponding first transistor and connect the other of the source and drain of the corresponding first transistor to a power supply (Symposium on
VLSI Circuits, Digest
of technical papers (Symposiu
m on VLSI Circuits. Dig
Est of Technical Paper
s) 1990, pp. 17-18).

[0005]

[Problems to be Solved by the Invention] In the first example of the conventional semiconductor memory described above, the active levels of the selection signals YS1 and YS2 output from the address decoder 2c are the same regardless of whether it is a write operation or a read operation. Therefore, during write operation, the selection signals YS1, Y
It is necessary to set S2 to a high level such that the on-resistance of each MOS transistor Q11 to Q14 of the input/output gate 1 is low enough to invert the data of the sense amplifiers SA1 and SA2 with the data of the input/output buses B1 and B2. , when such a level is set, when multiple selection signals instantaneously rise due to switching timing of external address signals during data reading, multiple sense amplifiers are connected to input/output buses B1 and B2, If the data in the sense amplifiers were different, there was a risk that these data would be destroyed.

In the second example, even if a plurality of sense amplifiers are selected, the sense amplifiers are separated from each other, so data is not destroyed, but a large number of transistors are required for this purpose. Therefore, there was a problem that the chip area increased.

The objects of the present invention are, firstly, that even if a plurality of sense amplifiers become selected at the same time during a read operation, data in each sense amplifier is not destroyed, and secondly, that the number of transistors is increased. It is an object of the present invention to provide a semiconductor memory that can prevent data destruction of sense amplifiers in a simultaneous selection state without causing damage.

[0008]

[Means for Solving the Problems] A semiconductor memory of the present invention has a plurality of bit lines that respectively transmit write data and read data of a plurality of memory cells, and a plurality of bit lines that respectively transmit data transmitted to these bit lines. a plurality of sense amplifiers for amplifying the bit lines; an input/output bus for externally transmitting data written to each bit line from the outside and data read from each bit line; an input/output gate circuit including a plurality of switching transistors which are provided in a plurality of switches and turn on and off in response to a corresponding selection signal to control the connection between the corresponding bit line and the input/output bus; In a semiconductor memory having an address decoder that sets one of selection signals to an active level, the address decoder outputs the selection signal whose active level is a first voltage during a write operation, and outputs the selection signal whose active level is a first voltage during a read operation. is configured as a circuit that outputs the selection signal having a second voltage lower than the first voltage.

Further, the address decoder includes a plurality of basic decoding circuits that output corresponding selection signals in accordance with address signals, and one resistor that commonly supplies power to each of these basic decoding circuits.

0010

[Operation] In the present invention, firstly, the level of the selection signal is changed during the write operation and the read operation, and the on-resistance of each MOS transistor of the input/output gate circuit is increased during the read operation. Even if the sense amplifiers are connected to each other, the resistance that connects them becomes large, so that the data in these sense amplifiers will not be destroyed.

Second, by commonly supplying power to each basic decoding circuit that outputs each selection signal through one resistor, the current flowing through this resistor increases when multiple selections are made. As the signal level decreases, the on-resistance of each MOS transistor in the input/output gate circuit increases,
As in the first case described above, data in the sense amplifier is not destroyed, and only one resistor needs to be added.

0012

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment is different from the conventional semiconductor memory shown in FIG. The power supply voltage Vdd1 is supplied through the MOS transistor Q25 which is turned on by the signal R/W, and during the read operation, the power supply voltage Vdd1 is supplied through the MOS transistor Q26 which is turned on by the inverted signal of the read/write signal R/W.
The point is that power is supplied at a lower power supply voltage Vdd2.

With this configuration, the on-resistance of each MOS transistor Q11 to Q14 of the input/output gate circuit 1 is small during a write operation, so that data on the input/output bus B1B2 is transmitted to the sense amplifiers SA1 and SA2. Since writing is possible and the resistance increases during read operation, even if sense amplifiers SA1 and SA2 are simultaneously selected, the resistance value connecting these sense amplifiers SA1 and SA2 is large, and therefore, each one destroys the data of the other sense amplifier. There's nothing left to do.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, each basic decoding circuit is supplied with a power supply voltage Vdd from one power supply, and during a write operation, it is connected to approximately the power supply voltage Vdd through a P-type MOS transistor Q25.
During read operation, the power supply voltage (
It is designed to supply power of Vdd-Vt).

This embodiment has the advantage that, unlike the first embodiment, there is no need to prepare power supplies with different power supply voltages Vdd1 and Vdd2, and there is no need for the inverter IV21.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

In this embodiment, the address decoder 2b is
This circuit is configured to commonly supply a power supply voltage Vdd to each basic decoding circuit through one resistor R1.

Next, the operation of this embodiment will be explained. FIG. 4 shows a selection signal Y for explaining the operation of this embodiment.
It is a waveform diagram of S1.

[0022] When multiple selection occurs during a read operation, the voltage drop across resistor R1 becomes large due to the current flowing through the basic decoding circuit which is the multiple selection, and the level of the selection signal (for example, YS1) in this multiple selection state increases. , the level Vb at which the data in the sense amplifier is destroyed is not reached, or even if it is reached, it takes a considerable amount of time. Since the multiple selection is for a short time while the address is switched, when the multiple selection is canceled at time t1, the selection signal YS1 becomes the power supply voltage Vdd.
and becomes the normal single selection state. In this way, even if a multiple selection state occurs, the data in each sense amplifier will not be mutually destroyed.

In this embodiment, the purpose can be achieved by simply adding one resistor R1 to the conventional semiconductor memory shown in FIG. 5, and the chip area is almost the same as in the conventional example. There is an advantage.

[0024]

[Effects of the Invention] As explained above, the present invention has the following advantages:
By configuring the selection signal level to be low during a read operation and high during a write operation, the resistance between each sense amplifier increases during multiple selection during a read operation, so that data in each sense amplifier is not destroyed. Second, by configuring a configuration in which power is commonly supplied to each basic decoding circuit of the address decoder through one resistor, the level of the selection signal is lower than that of the sense amplifier during multiple selection during read operation. Since this does not reach a level that would destroy data, it is possible to prevent the data in the sense amplifier from being destroyed without increasing the chip area.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a waveform diagram of a selection signal for explaining the operation of the embodiment shown in FIG. 3;

FIG. 5 is a circuit diagram showing an example of a conventional semiconductor memory.

[Explanation of symbols]

1 Input/output gate circuit 2, 2a to 2c Address decoder B1, B2
Input/output bus BL11, BL12, BL21, BL22 Bit line IV21 Inverter Q11-Q14, Q21-Q27 MOS transistor R1 Resistor SA1, SA2 Sense amplifier

Claims (2)

[Claims] 1. A plurality of bit lines that respectively transmit write data and read data of a plurality of memory cells, a plurality of sense amplifiers that respectively amplify the data transmitted to these bit lines, and an external An input/output bus is provided for externally transmitting data written to each bit line and read data from each bit line, and an input/output bus is provided corresponding to each bit line and turned on and off by a corresponding selection signal. an input/output gate circuit including a plurality of switching transistors for controlling connection between the corresponding bit line and the input/output bus, and setting one of the selection signals to an active level in accordance with an address signal. In a semiconductor memory having an address decoder, the address decoder outputs the selection signal whose active level is a first voltage during a write operation, and a second voltage whose active level is lower than the first voltage during a read operation. A semiconductor memory characterized in that the circuit outputs the selection signal as a voltage. Claim 2: A claim in which the address decoder is configured to include a plurality of basic decoding circuits each outputting a corresponding selection signal in accordance with an address signal, and one resistor that commonly supplies power to each of these basic decoding circuits. Item 1
The semiconductor memory described.