JPH04315315A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To obtain an output buffer circuit in which an 'H' read time and an 'L' read time are equal to each other. CONSTITUTION:A pulse generating circuit 100 imparts an 'L' level to a node (c) for a prescribed period from the data inversion time of a node (a). A PMOS transistor(TR) P1 is turned on in response to the 'L' level and an NMOS TR N1 is turned on. Thus, the off-time of the NMOS TR N1 at 'L' read is delayed and the on-time of the NMOS TR N1 at 'H' read is quickened. The 'H' read time and the 'L' read time are made equal to each other by adjusting the width of the 'L' pulse from the pulse generating circuit 100.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention provides a first N-channel transistor connected between a high potential point and an output terminal;
a second N-channel transistor connected between the low potential point and the output terminal, the first and second N-channel transistors are selectively turned on, and the output terminal is set to "H" or "L". The present invention relates to an output buffer circuit that selectively outputs output.

0002

2. Description of the Related Art FIG. 5 is a circuit diagram showing a conventional output buffer circuit used in a semiconductor memory device. node a
is a node to which read data inside the device is given. Inverter I outputs inverted data of node a to node b. The data of nodes a and b are complementary data, and if one is "L", the other is "H". Data at node a is input to one input of NOR circuit 1, and data at node b is input to one input of NOR circuit 1.
The data are respectively input to one input of the NOR circuit 2. Data OE (“L”) is input to the other input of NOR circuits 1 and 2.
” or fixed to “H”) is input.Data O
When E is “L”, that is, in output enabled mode, N
OR circuits 1 and 2 function as inverters, and nodes h,
The data of i becomes the inverted data of the data of nodes a and b. When the data OE is "H", that is, in the output disabled mode, the NOR circuits 1 and 2 force the data on both nodes h and i to "L".

N-channel MOS transistor (hereinafter referred to as NM
N1 and N2 (referred to as OS transistors) are connected in series between the power supply Vcc and ground. A common connection point between the source of the NMOS transistor N1 and the drain of the NMOS transistor N2 is connected to a node DO. NMOS
The data of the node h, which is the output of the NOR circuit 1, is input to the gate of the transistor N1, and the data of the node i, which is the output of the NOR circuit 2, is input to the gate of the NMOS transistor N2. In output enabled mode, node h
and the data of node i are complementary data.

The cases of "L" reading and "H" reading will be explained using FIG. 6(a). First, "H" reading will be explained. Assume that the data at node a is inverted from "H" to "L" at time t1. Stray capacitance C
1, the arrival of "H" at the gate of NMOS transistor N1 is delayed, and the presence of stray capacitance C2 delays the arrival of "L" at the gate of NMOS transistor N2, at time t2. NMOS at time t2
Transistor N1 is turned on and NMOS transistor N2 is turned off. Therefore, the potential of the node DO starts to rise from time t2 and when it becomes higher than the threshold voltage VTH1, it is recognized as "H" by the next stage circuit. This time is t5. N.M.O.
When the S transistor N1 is on, the source potential (node D
Since the potential of the node DO gradually increases and the output impedance decreases, the potential of the node DO gradually increases. The potential of node DO (source potential) is Vcc-VTH2 (V
When TH2 reaches the threshold voltage of the NMOS transistor N1), the NMOS transistor N1 is completely turned off. At this time, since both NMOS transistors N1 and N2 are turned off, the node DO remains at "H".

Next, "L" reading will be explained. At time t1, the data of node a changes from “L” to “H”
Suppose that it is reversed. Due to the presence of stray capacitance C1, NMO
The arrival of "L" at the gate of the S transistor N1 is delayed, and due to the presence of stray capacitance C2, the arrival of "H" at the gate of the NMOS transistor N2 is delayed.
It becomes 2. At time t2, the NMOS transistor N1 is turned off and the NMOS transistor N2 is turned on. Therefore, the potential of the node DO starts to fall from time t2 to the threshold voltage VT
When it becomes smaller than H1, it is recognized as "L" by the next stage circuit. This time is t6.

When the NMOS transistor N2 is on, there is always a potential difference of Vcc between the gate and the source, so NM
Since OS transistor N2 is always on, it is “H”
The output impedance does not become small as it does during reading.

[0007]

[Problems to be Solved by the Invention] The conventional output buffer circuit is configured as described above, and when the NMOS transistor N1 is turned on, the potential of the node DO rises and the voltage between the node DO and the gate of the NMOS transistor N1 increases. As the potential difference decreases, the output impedance decreases, and "H" reading becomes delayed at time t5. Therefore, “H
There was a problem that there was a difference between the read time t5 and the "L" read time t6.

The present invention has been made to solve the above-mentioned problems, and its object is to obtain an output buffer circuit in which the "H" read time and the "L" read time are equal.

[0009]

[Means for Solving the Problems] The present invention provides a first N-channel transistor connected between a high potential point and an output terminal, and a second N-channel transistor connected between a low potential point and the output terminal. N-channel transistors, the first and second N-channel transistors
The present invention is applied to an output buffer circuit in which an N-channel transistor is selectively turned on and selectively outputs "H" or "L" to the output terminal.

The output buffer circuit according to the present invention includes a pull-up means connected to the gate of the first N-channel transistor and for pulling up the gate potential of the first N-channel transistor, and a pull-up means of the second N-channel transistor. It is characterized by comprising at least one of pull-down means connected to the gate and pulling down the gate potential of the second NMOS transistor, and turning on the pull-up means or the pull-down means for a predetermined time when the output of the output terminal is inverted. do.

[0011]

[Operation] The pull-up means in this invention
It is connected to the gate of the MOS transistor, turns on when the output of the output terminal is inverted, and pulls up the gate potential of the first N-channel transistor. Therefore, when reading "H", the turn-on time of the first N-channel transistor becomes faster, and when reading "L", the turn-off time of the first N-channel transistor becomes slower. The pull-down means is a second N
It is connected to the gate of the channel transistor, turns on when the output of the output terminal is inverted, and pulls down the gate potential of the second N-channel transistor. Therefore, when reading "L", the turn-on time of the second N-channel transistor is delayed.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing a first embodiment of an output buffer circuit according to the present invention. In the figure, the difference from the conventional circuit shown in FIG. 5 is that a P-channel MOS transistor (hereinafter referred to as PMOS transistor) P1 is newly provided. The PMOS transistor P1 has a source connected to the power supply Vcc and a drain connected to the NMOS transistor N1.
The gate is connected to the ATD (Address Tran) gate.
They are each connected to a pulse generating circuit 100 such as a pulse generator (situation detector) or the like. The other configurations are the same as the conventional circuit.

Note that the output buffer circuit has the role of outputting and transmitting internal data to the outside. The output buffer circuit is made up of transistors with large driving capability, that is, large dimensions, so that when mounted on a board, the output buffer circuit can sufficiently drive load capacitance generated by input buffers of other devices, board wiring, etc. Therefore,
The dimensions of NMOS transistors N1 and N2 become larger, and nodes h and i have a relatively large stray capacitance C1.
, C2 will exist. However, stray capacitance C
The capacitance value of C2 is considered to be sufficiently small compared to the capacitance value of the stray capacitance C3 attached to the node DO (external).

Next, the operation will be explained using FIG. 6(b). Data OE is fixed at "L". When data arrives at node a at time t1, data at node b begins to be inverted almost simultaneously, and data at nodes h and i also begin to invert. Since there is a stray capacitance C1 at the node h, the inversion time of the data at the node h is slightly delayed from the data arrival time at the node a, and as a result, the inversion time of the output data of the output buffer circuit is also delayed.

The pulse generating circuit 100 applies "L" data (pulse) to the node c only from the time when the data at the node a is inverted (time t1) to the time t3, turns on the PMOS transistor P1, and turns on the NMOS transistor N1. Pull up the gate potential of As the gate potential is pulled up, the NMOS transistor N1 is at time t1.
It is forcibly turned on from time t3 to time t3.

Therefore, in the case of "L" reading, the NMOS transistor N1 is turned off at time t2, but the off time is extended to time t3.

On the other hand, in the case of "H" reading, conventional time t
2, the NMOS transistor N1 was turned on until time t1.

In this manner, in the case of "L" reading, the off time of the NMOS transistor N1 is delayed, and "
In the case of H” reading, the NMOS transistor N
The on time of pulse generation circuit 1 can be made faster.
By adjusting the pulse width of "L" from 00, the output reversal time of the output buffer circuit (the time when the voltage at node DO reaches the threshold voltage VTH1) is determined as shown in FIG. 6(b).
can be made equal. In FIG. 6(b), it is time t7. As a result, the "L" read time and the "H" read time can be made equal.

Note that since the capacitance value of the stray capacitance C3 is larger than the capacitance value of the stray capacitances C1 and C2, the nodes h,
The potential change of i becomes faster than the potential change of node DO. In other words, when the PMOS transistor P1 is on, the gate potential of the NMOS transistor N1 is pulled up and the NMOS
Even when transistor N1 is turned on, node DO does not change much. Therefore, there are almost no sudden fluctuations (output glitches) in the node DO.

FIG. 2 is a circuit diagram showing a second embodiment of the invention. In this embodiment, the PMOS shown in the embodiment of FIG.
The transistor P1 is replaced with an NMOS transistor N3. In this case, node c is set to “H” from time t1 to t3.
By turning on the NMOS transistor N1, the same effect as in the above embodiment can be obtained.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention. In the figure, the difference from the conventional circuit shown in FIG. 5 is that a PMOS transistor P2 is newly provided. The PMOS transistor P2 has a gate connected to the pulse generation circuit 100, a drain connected to ground, and a source connected to the gate of the NMOS transistor N1. The other configurations are the same as the conventional circuit.

Next, the operation will be explained. Similarly to the embodiment of FIG. 1, from data inversion time t1 of node a to time t3
During this period, the pulse generating circuit 100 applies "L" to the node c and turns on the PMOS transistor P2 at time t1. By turning on the PMOS transistor P2, the gate potential of the NMOS transistor N2 is pulled down, and the NMOS transistor N2 changes from time t1 to time t3.
It is forced to turn off for a while. Therefore, when reading "L", the ON time of the NMOS transistor N2 is later than the conventional time t2. Therefore, the "L" read time can be made later than the conventional time t6. On the other hand, when reading "H", the off time of the NMOS transistor N2 is faster than the conventional time t2, but the on time of the NMOS transistor N1 remains the conventional time (t2).
The “H” read time is the same as the conventional one (t5). As a result, by adjusting the "L" pulse width from the pulse generating circuit 100, the "L" read time and the "H" read time can be made the same.

Note that the PMOS transistor P2 is replaced by an NMOS transistor P2.
Instead of using an S transistor, the gate is set to “
Even if the structure is configured to provide H'', the same effect as in the third embodiment can be obtained.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention. This embodiment is similar to the first embodiment shown in FIG.
This embodiment is a combination of the third embodiment shown in . The operation is similar to that of the first and second embodiments, and the effects are also the same.

[0025]

As described above, according to the present invention, the first N-channel transistor connected to the gate of the first N-channel transistor
Inverting the output of the output terminal includes at least one of a pull-up means for pulling up the gate potential of the channel transistor and a pull-down means connected to the gate of the second N-channel transistor for pulling down the gate potential of the second NMOS transistor. Since the pull-up means or pull-down means is turned on for a predetermined period of time, the turn-on time of the first N-channel transistor becomes faster when reading "H", and the turn-on time of the first N-channel transistor becomes faster when reading "L". Become slow. Also,
The turn-on time of the second N-channel transistor when reading "L" is delayed. As a result, “L” read time and “
This has the effect of making the read times equal to each other.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an output buffer circuit according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of an output buffer circuit according to the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of an output buffer circuit according to the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of an output buffer circuit according to the present invention.

FIG. 5 is a circuit diagram showing a conventional output buffer circuit.

FIG. 6 is a diagram for explaining the operation of the conventional output buffer circuit and the output buffer circuit according to the present invention.

[Explanation of symbols]

Vcc power supply P1, P2 PMOS transistor N1, N2 NMOS transistor 100 Pulse generation circuit

Claims (1)

[Claims] 1. A first N-channel transistor connected between a high potential point and an output terminal, and a second N-channel transistor connected between a low potential point and the output terminal, In an output buffer circuit in which the first and second N-channel transistors are selectively turned on and selectively output "H" or "L" to the output terminal, the output buffer circuit is connected to the gate of the first N-channel transistor. and at least a pull-up means for pulling up the gate potential of the first N-channel transistor and a pull-down means connected to the gate of the second N-channel transistor for pulling down the gate potential of the second N-channel transistor. 1. An output buffer circuit characterized in that the pull-up means or the pull-down means is turned on for a predetermined period of time when the output of the output terminal is inverted.