JPH04314397A - Manufacture of multi-layer printed wiring board - Google Patents
Manufacture of multi-layer printed wiring boardInfo
- Publication number
- JPH04314397A JPH04314397A JP7995291A JP7995291A JPH04314397A JP H04314397 A JPH04314397 A JP H04314397A JP 7995291 A JP7995291 A JP 7995291A JP 7995291 A JP7995291 A JP 7995291A JP H04314397 A JPH04314397 A JP H04314397A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- printed wiring
- adhesive layer
- copper
- electroless
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000010949 copper Substances 0.000 claims abstract description 51
- 229910052802 copper Inorganic materials 0.000 claims abstract description 50
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 49
- 238000007747 plating Methods 0.000 claims abstract description 29
- 239000010410 layer Substances 0.000 claims abstract description 26
- 239000012790 adhesive layer Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005553 drilling Methods 0.000 claims abstract description 10
- 239000003054 catalyst Substances 0.000 claims abstract description 8
- 239000011347 resin Substances 0.000 claims abstract description 7
- 229920005989 resin Polymers 0.000 claims abstract description 7
- 238000007772 electroless plating Methods 0.000 claims abstract description 4
- 239000011229 interlayer Substances 0.000 claims abstract 4
- 239000002184 metal Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 21
- 238000007788 roughening Methods 0.000 claims description 21
- 238000000576 coating method Methods 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 230000003197 catalytic effect Effects 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052745 lead Inorganic materials 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052702 rhenium Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052725 zinc Inorganic materials 0.000 claims description 3
- 229910000990 Ni alloy Inorganic materials 0.000 claims 1
- 230000002950 deficient Effects 0.000 abstract 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 8
- KRVSOGSZCMJSLX-UHFFFAOYSA-L chromic acid Substances O[Cr](O)(=O)=O KRVSOGSZCMJSLX-UHFFFAOYSA-L 0.000 description 6
- AWJWCTOOIBYHON-UHFFFAOYSA-N furo[3,4-b]pyrazine-5,7-dione Chemical compound C1=CN=C2C(=O)OC(=O)C2=N1 AWJWCTOOIBYHON-UHFFFAOYSA-N 0.000 description 6
- 238000004080 punching Methods 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000006386 neutralization reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は多層プリント配線板の製
造方法に関し、特に無電解銅メッキで回路を形成する多
層プリント配線版の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board, and more particularly to a method for manufacturing a multilayer printed wiring board in which circuits are formed by electroless copper plating.
【0002】0002
【従来の技術】近年、プリント配線板の高密度化や実装
方式の変化に対応して、いわゆるフルアディティブ法を
用いた多層プリント配線板の製造方法が注目されている
。2. Description of the Related Art In recent years, in response to the increasing density of printed wiring boards and changes in mounting methods, a method of manufacturing multilayer printed wiring boards using a so-called full additive method has been attracting attention.
【0003】これは、触媒入り接着剤層付樹脂基板をパ
ンチまたはドリルで穴明け後、スミヤ処理をし,レジス
トを印刷後さらに粗化液で接着剤層を粗化し、無電解銅
めっきで回路を形成したり、あるいは接着剤層付樹脂基
板をパンチまたはドリルで穴明け後、粗化液で接着剤層
を粗化し、触媒化処理を行い、レジストを印刷後、無電
解銅めっきで回路を形成するという方法である。[0003] This involves punching or drilling holes in a resin substrate with a catalyst-containing adhesive layer, then smearing the resin substrate, printing a resist, then roughening the adhesive layer with a roughening liquid, and applying electroless copper plating to the circuit. Alternatively, after punching or drilling holes in a resin substrate with an adhesive layer, roughen the adhesive layer with a roughening liquid, perform catalytic treatment, print a resist, and then form a circuit with electroless copper plating. The method is to form.
【0004】0004
【発明が解決しようとする課題】しかしながら、上記の
如き従来のフルアディティブ法を用いた多層プリント配
線板の製造方法にあっては、、粗化工程で使用する粗化
液のほとんどが強酸性酸化液であり、銅がこれに比較的
侵されやすいので、内層銅がエッチバックされて、無電
解銅めっきで回路を形成する際、スルホール内めっき銅
と内層銅の接続信頼性の低下や接続不良が発生するとい
う不具合があった。[Problems to be Solved by the Invention] However, in the method of manufacturing multilayer printed wiring boards using the conventional fully additive method as described above, most of the roughening liquid used in the roughening process is a strong acid oxidizer. It is a liquid and copper is relatively easily attacked by it, so when the inner layer copper is etched back and a circuit is formed using electroless copper plating, the connection reliability between the plated copper inside the through hole and the inner layer copper may be reduced or there may be a connection failure. There was a problem that occurred.
【0005】本発明は、上記の如き従来の課題に鑑みて
なされたもので、その目的とするところは、フルアディ
ティブ法を用いた製造方法であって、しかも粗化工程に
おける内層銅のエッチバックを抑制することのできる多
層プリント配線板の製造方法を提供することにある。The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide a manufacturing method using a fully additive method, and moreover, which eliminates the etch-back of the inner layer copper in the roughening process. It is an object of the present invention to provide a method for manufacturing a multilayer printed wiring board that can suppress the above problems.
【0006】[0006]
【課題を解決するための手段】本発明の内層銅のエッチ
バック抑制法は、金属皮膜による内層銅の保護であり,
金属皮膜としては,Ni,Au,Pd,Sn,Cu,C
o,Pb,Cr,Zn,Ag,Rh,Pt,Re,In
や,あるいはこれらの金属を1種類以上含有する合金で
あることを特徴としている。[Means for Solving the Problems] The method of suppressing etchback of inner layer copper of the present invention is to protect inner layer copper with a metal film,
Metal coatings include Ni, Au, Pd, Sn, Cu, and C.
o, Pb, Cr, Zn, Ag, Rh, Pt, Re, In
It is characterized by being an alloy containing one or more of these metals.
【0007】本発明に用いる金属皮膜の種類は上記以外
でも,粗化液に対し侵されにくいものであればよい。ま
た金属皮膜としてCuをも用いる理由は、内層銅壁に保
護用銅の金属皮膜を形成することにより、まず銅金属皮
膜がエッチングされ、内層銅のエッチバック量を抑制す
るためである。The metal coating used in the present invention may be of any type other than those mentioned above as long as it is resistant to attack by the roughening solution. Further, the reason why Cu is also used as the metal film is that by forming a protective copper metal film on the inner layer copper wall, the copper metal film is first etched, thereby suppressing the amount of etchback of the inner layer copper.
【0008】金属皮膜の形成は、穴明け後,粗化工程の
前に行なう。金属皮膜の形成法としては,無電解めっき
が望ましい。また金属皮膜の形成は1段階以上のめっき
工程を必要としてもかまはない。また,金属皮膜が内層
銅壁に形成されていれば目的は達成されるので、スルホ
ール穴内全域を金属皮膜でおおっても、また内層銅壁の
みでもかまわない。なお、基板表面は粗化工程後でなけ
れば、無電解めっきにより金属めっき層が形成されるこ
とはない。従って、内層銅保護用の金属皮膜はスルホー
ル穴内のみに形成される。[0008] The metal film is formed after drilling and before the roughening step. Electroless plating is the preferred method for forming the metal film. Further, the formation of the metal film may require one or more plating steps. Furthermore, since the purpose is achieved if the metal coating is formed on the inner layer copper wall, it does not matter whether the entire inside of the through hole is covered with the metal coating or only the inner layer copper wall is covered. Note that a metal plating layer is not formed on the surface of the substrate by electroless plating unless it is subjected to a roughening process. Therefore, the metal film for protecting the inner layer copper is formed only within the through hole.
【0009】[0009]
【作用】穴明け後,粗化工程の前に金属被覆を行なうこ
とにより、粗化工程での内層銅のエッチバックはまった
く発生しないか,あるいはかなり抑制される。従って,
無電解銅めっきにより回路を形成する際,スルホール内
めっき銅と内層銅との接続不良はまったく発生せず,ま
た接続信頼性も向上する。[Operation] By performing metal coating after drilling and before the roughening process, etchback of the inner copper layer during the roughening process does not occur at all or is considerably suppressed. Therefore,
When forming a circuit using electroless copper plating, no connection failure occurs between the plated copper inside the through-hole and the inner layer copper, and connection reliability is also improved.
【0010】0010
【実施例】以下、本発明を実施例に基づい説明する。
(実施例1)触媒入り接着剤層付多層基板をパンチまた
はドリルで穴明け後、スミヤ処理を行い,その後置換P
dめっきを室温で3〜5分間で行い、さらに水洗後無電
解Niめっきを75〜80℃で5分間行なった。そして
、レジストを印刷後、クロム酸・硫酸混液系粗化液を用
いて36℃で5分間接着剤層を粗化し、さらに中和及び
めっき前処理を行なった後,無電解銅めっきで回路を形
成し、多層プリント配線板を作成した。内層銅とスルホ
ール銅間の抵抗の測定を行い、断線発生までのホットオ
イル試験(260℃で5秒、水5秒)のサイクル数を求
めた。結果を表に示す。
(実施例2)触媒入り接着剤層付多層基板をパンチまた
はドリルで穴明け後、スミヤ処理を行い,無電解Niめ
っきを75〜80℃で5分間行なった。つぎに、レジス
トを印刷後、クロム酸・硫酸混液系粗化液を用いて36
℃で5分間接着剤層を粗化し、中和及びめっき前処理を
行なった後,無電解銅めっきで回路を形成し、多層プリ
ント配線板を作成した。内層銅とスルホール銅間の抵抗
の測定を行い、断線発生までのホットオイル試験(26
0℃で5秒、水5秒)のサイクル数を求めた。結果を表
に示す。
(実施例3)触媒入り接着剤層付多層基板をパンチまた
はドリルで穴明け後、スミヤ処理を行い,無電解Auめ
っきを行なった。つぎに、レジストを印刷後、クロム酸
・硫酸混液系粗化液を用いて36℃で5分間接着剤層を
粗化し、中和及びめっき前処理を行なった後,無電解銅
めっきで回路を形成し、多層プリント配線板を作成した
。内層銅とスルホール銅間の抵抗の測定を行い、断線発
生までのホットオイル試験(260℃で5秒、水5秒)
のサイクル数を求めた。結果を表に示す。
(実施例4)触媒入り接着剤層付多層基板をパンチまた
はドリルで穴明け後、スミヤ処理を行い、レジストを印
刷後、無電解Niめっきを75〜80℃で5分間行った
。つぎに、クロム酸・硫酸混液系粗化液を用いて36℃
で5分間接着剤層を粗化し、中和及びめっき前処理を行
い,さらに無電解銅めっきで回路を形成し、多層プリン
ト配線板を作成した。内層銅とスルホール銅間の抵抗の
測定を行い、断線発生までのホットオイル試験(260
℃で5秒、水5秒)のサイクル数を求めた。結果を表に
示す。
(実施例5)接着剤層付多層基板をパンチまたはドリル
で穴明け後、スミヤ処理を行い,その後置換Pdめっき
を室温で3〜5分間行い,さらに水洗後無電解Niめっ
きを75〜80℃で5分間行なった。そして、クロム酸
・硫酸混液系粗化液を用いて36℃で5分間接着剤層を
粗化し、中和を行なった。つぎに、触媒化処理を行い、
レジストを印刷後、無電解銅めっきで回路を形成し、多
層プリント配線板を作成した。内層銅とスルホール銅間
の抵抗の測定を行い、断線発生までのホットオイル試験
(260℃で5秒、水5秒)のサイクル数を求めた。結
果を表に示す。
(比較例)触媒入り接着剤層付多層基板をパンチまたは
ドリルで穴明け後、スミヤ処理を行なった。そして、レ
ジストを印刷後、クロム酸・硫酸混液系粗化液を用いて
36℃で5分間接着剤層を粗化し、中和及びめっき前処
理を行なった後,無電解銅めっきで回路を形成し、多層
プリント配線板を作成した。内層銅とスルホール銅間の
抵抗の測定を行い、断線発生までのホットオイル試験(
260℃で5秒、水5秒)のサイクル数を求めた。結果
を表に示す。
(以下、余白)EXAMPLES The present invention will be explained below based on examples. (Example 1) After punching or drilling holes in a multilayer substrate with a catalyst-containing adhesive layer, smearing was performed, and then P was replaced.
d plating was performed at room temperature for 3 to 5 minutes, and after washing with water, electroless Ni plating was performed at 75 to 80° C. for 5 minutes. After printing the resist, the adhesive layer was roughened using a chromic acid/sulfuric acid mixed roughening solution at 36°C for 5 minutes, and after further neutralization and plating pretreatment, the circuit was formed using electroless copper plating. A multilayer printed wiring board was fabricated. The resistance between the inner layer copper and the through-hole copper was measured, and the number of cycles of the hot oil test (260° C. for 5 seconds, water for 5 seconds) until disconnection occurred was determined. The results are shown in the table. (Example 2) A multilayer substrate with a catalyst-containing adhesive layer was punched or drilled, smeared, and electroless Ni plated at 75 to 80°C for 5 minutes. Next, after printing the resist, use a roughening solution of chromic acid/sulfuric acid mixture to
After roughening the adhesive layer at ℃ for 5 minutes, performing neutralization and pre-plating treatment, a circuit was formed by electroless copper plating to create a multilayer printed wiring board. The resistance between the inner layer copper and the through-hole copper was measured, and a hot oil test (26
The number of cycles (5 seconds at 0°C, 5 seconds at water) was determined. The results are shown in the table. (Example 3) A multilayer substrate with a catalyst-containing adhesive layer was punched or drilled, then smeared and electroless Au plating was performed. Next, after printing the resist, the adhesive layer was roughened using a chromic acid/sulfuric acid mixed roughening solution at 36°C for 5 minutes, neutralized and pre-plated, and then the circuit was formed using electroless copper plating. A multilayer printed wiring board was fabricated. Measure the resistance between the inner layer copper and through-hole copper, and conduct a hot oil test (260°C for 5 seconds, water for 5 seconds) until disconnection occurs.
The number of cycles was calculated. The results are shown in the table. (Example 4) A multilayer substrate with a catalyst-containing adhesive layer was punched or drilled, then smeared, a resist was printed, and electroless Ni plating was performed at 75 to 80° C. for 5 minutes. Next, a roughening solution of chromic acid/sulfuric acid mixture was used at 36°C.
The adhesive layer was roughened for 5 minutes, neutralized and pre-plated, and a circuit was formed by electroless copper plating to create a multilayer printed wiring board. The resistance between the inner layer copper and the through-hole copper was measured, and a hot oil test (260
The number of cycles (5 seconds at °C, 5 seconds at water) was determined. The results are shown in the table. (Example 5) After punching or drilling holes in a multilayer substrate with an adhesive layer, smearing is performed, followed by displacement Pd plating at room temperature for 3 to 5 minutes, and then electroless Ni plating after washing with water at 75 to 80°C. I did it for 5 minutes. Then, the adhesive layer was roughened using a chromic acid/sulfuric acid mixture roughening solution at 36° C. for 5 minutes to perform neutralization. Next, perform catalytic treatment,
After printing the resist, a circuit was formed by electroless copper plating to create a multilayer printed wiring board. The resistance between the inner layer copper and the through-hole copper was measured, and the number of cycles of the hot oil test (260° C. for 5 seconds, water for 5 seconds) until disconnection occurred was determined. The results are shown in the table. (Comparative Example) A multilayer substrate with a catalyst-containing adhesive layer was punched or drilled, and then smeared. After printing the resist, the adhesive layer is roughened using a chromic acid/sulfuric acid mixed roughening solution at 36°C for 5 minutes, neutralized and pre-plated, and a circuit is formed by electroless copper plating. Then, a multilayer printed wiring board was created. The resistance between the inner layer copper and through-hole copper is measured, and a hot oil test (
The number of cycles (5 seconds at 260°C, 5 seconds at water) was determined. The results are shown in the table. (Hereafter, margin)
【0011】[0011]
【表1】[Table 1]
【0012】0012
【発明の効果】以上説明してきたように、本発明では,
内層接続不良はまったく発生せず,これによって接続信
頼性も著しく向上するなど,高品質の多層プリント配線
板を得ることができるという効果を有する。[Effects of the Invention] As explained above, in the present invention,
This method has the effect that a high-quality multilayer printed wiring board can be obtained, with no inner layer connection failure occurring at all, and connection reliability being significantly improved.
Claims (6)
ための穴明け後、スミヤ処理を行い,レジストを印刷後
、粗化液で接着剤層を粗化し、無電解銅めっきで回路を
形成する工程、あるいは接着剤層付樹脂基板を層間接続
のための穴明け後、粗化液で接着剤層を粗化し、触媒化
処理を行い、レジストを印刷後、無電解銅めっきで回路
を形成する工程よりなる多層プリント配線板の製造方法
において、穴あけ工程後、粗化工程前に、少なくともス
ルホールに露出する内層銅壁に金属皮膜を形成すること
を特徴とする多層プリント配線板の製造方法。Claim 1: After drilling holes in a resin base plate with a catalyst-containing adhesive layer for interlayer connection, smearing is performed, a resist is printed, the adhesive layer is roughened with a roughening liquid, and electroless copper plating is applied. In the process of forming a circuit, or after drilling holes in a resin substrate with an adhesive layer for interlayer connection, the adhesive layer is roughened with a roughening liquid, catalyzed, and after printing a resist, electroless copper plating is performed. A method for manufacturing a multilayer printed wiring board comprising a step of forming a circuit, which comprises forming a metal film on at least the inner layer copper wall exposed in the through-holes after the hole-drilling step and before the roughening step. Production method.
u,Co,Pb,Cr,Zn,Ag,Rh,Pt,Re
,Inよりなるか,あるいはこれらの金属を1種類以上
含有する合金よりなることを特徴とする請求項1に記載
の多層プリント配線板の製造方法。[Claim 2] The metal film is Ni, Au, Pd, Sn, C.
u, Co, Pb, Cr, Zn, Ag, Rh, Pt, Re
, In, or an alloy containing one or more of these metals.
u,Co,Pb,Cr,Zn,Ag,Rh,Pt,Re
,Inよりなるか,あるいはこれらの金属を1種類以上
含有する合金よりなり、かつ無電解めっき法で形成され
ることを特徴とする請求項1に記載の多層プリント配線
板の製造方法。[Claim 3] The metal film is Ni, Au, Pd, Sn, C.
u, Co, Pb, Cr, Zn, Ag, Rh, Pt, Re
, In, or an alloy containing one or more of these metals, and is formed by electroless plating.
触媒化処理後,無電解Niめっき法で形成されることを
特徴とする請求項1に記載の多層プリント配線板の製造
方法。Claim 4: The metal film is made of Ni or Ni alloy,
2. The method of manufacturing a multilayer printed wiring board according to claim 1, wherein the multilayer printed wiring board is formed by electroless Ni plating after the catalytic treatment.
めっき法であることを特徴とする請求項1に記載の多層
プリント配線板の製造方法。5. The catalytic treatment in claim 4 comprises substituted Pd
The method for manufacturing a multilayer printed wiring board according to claim 1, characterized in that the method is a plating method.
iを被覆した後,無電解Auめっき法で形成されること
を特徴とする請求項1に記載の多層プリント配線板の製
造方法。[Claim 6] The metal film is made of Au, and the metal film is made of N on the inner layer copper wall.
2. The method of manufacturing a multilayer printed wiring board according to claim 1, wherein after coating the layer i, the layer is formed by electroless Au plating.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7995291A JPH04314397A (en) | 1991-04-12 | 1991-04-12 | Manufacture of multi-layer printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7995291A JPH04314397A (en) | 1991-04-12 | 1991-04-12 | Manufacture of multi-layer printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04314397A true JPH04314397A (en) | 1992-11-05 |
Family
ID=13704647
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7995291A Pending JPH04314397A (en) | 1991-04-12 | 1991-04-12 | Manufacture of multi-layer printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04314397A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996017503A1 (en) * | 1994-12-01 | 1996-06-06 | Ibiden Co., Ltd. | Multilayer printed wiring board and process for producing the same |
-
1991
- 1991-04-12 JP JP7995291A patent/JPH04314397A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996017503A1 (en) * | 1994-12-01 | 1996-06-06 | Ibiden Co., Ltd. | Multilayer printed wiring board and process for producing the same |
US5827604A (en) * | 1994-12-01 | 1998-10-27 | Ibiden Co., Ltd. | Multilayer printed circuit board and method of producing the same |
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