JPH04314092A - Superlong digit display device and its display system - Google Patents

Abstract

PURPOSE:To obtain a superlong digit display device and its display system capable of preventing a transmission clock from being deviated or a waveform from being deformed at the time of displaying superlong digits and attaining precise display free from flickering without setting up the transmission clock to high frequency only by changing the arrangement of a display unit and adding a simple circuit to the superlong digit display device. CONSTITUTION:The superlong digit display device and its display system are constituted of dividing the display area of a display part 9, forming a display RAM address from a screen controller 2 to a display RAM 7 so as to output display data to the divided display areas in parallel, fetching the display data read out from the display RAM 7 to P/S converters 8a, 8b corresponding to the divided display areas at the timing of 1st and 2nd signals outputted from the controller 2 through a buffer 11, and outputting the outputs of the converters 8a, 8b to the divided display areas in parallel. The display data are successively shifted to the display unit in the vertical direction in each column of the display unit.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a display device such as an LED dot matrix display device in which light emitting bodies are arranged in a dot matrix, and in particular, the display portion has a super long digit size configuration. By dividing the compatible display RAM and treating it as a short digit size display section, and sending the display data on the display RAM for each divided display section in parallel, it can be displayed on a super long digit size display section. The present invention relates to a super-long digit display device and its display method.

0002

[Prior Art] Regarding conventional dot matrix display devices, taking an LED dot matrix display device as an example,
This will be explained using the circuit configuration block diagram of FIG. 11.

[0003] To explain each component in the LED dot matrix display device, the CPU 1 specifies a device to be accessed via an address bus, accesses data in a storage device or the like (not shown), and further C
PU1 is connected to multiplexer (MPX) by address bus.
) 3, open the bus driver 4, and transfer the display data from the storage device etc. to the display RAM (V-RAM
)7.

[0004] The MPX3 is a switch between the CPU 1 and the screen controller 2, and when the CPU 1 operates on the V-RAM 7, the bus driver 4 is open and the V-RAM
7, and when the screen controller 2 operates on the V-RAM 7, the bus driver 4 is closed, and at this time, the MPX3 writes the display data to the screen controller 2.
and V-RAM7 are connected.

The clock oscillated from the oscillator 5 is multiplied by 1/8 by a transmission frequency divider 10, and then one is output to a parallel/serial converter (P/S converter) 8, and the other is output to a screen controller. The frequency divider 6 converts the signal into a 1/8 clock and outputs it to the screen controller 2. The screen controller 2 outputs the display address given from the CPU 1 to the V-RAM 7 via the MPX 3 according to the timing of the input clock.

[0006] The V-RAM 7 receives a display address corresponding to the content to be displayed on the LED display unit 9 from the screen controller 2 through the MPX 3, and then transmits display data corresponding to the display address at the output timing of the transmission frequency divider 10. Output to the LED display section 9 via the P/S converter 8,
It is to be displayed.

The conventional LED dot matrix display device has one or two planes in the V-RAM 7 with the same capacity as the LED display section 9, as shown in FIG.
The display contents were held as dot images. In order to switch the display contents, the contents of this plane are written to the V-RAM 7, and the CPU 1 instructs the address of the plane to the V-RAM 7 via the screen controller 2, thereby changing the display screen of the LED display section 9. The idea was to switch.

[0008]

[Problems to be Solved by the Invention] However, in the conventional LED dot matrix display device, even while one plane is being displayed on the LED display section 9, the CPU 1 is always V-RA
Since it is necessary to write a plane in M7, the CPU
1, most of the work being done within that certain period of time will be occupied by plane creation, and if the display screen of the LED display section 9 is large, the plane creation process by the CPU 1 will not be able to keep up with the screen switching process. There was a problem.

[0009] Another problem is that once a plane has been displayed, it can be rewritten immediately, so if you try to display it repeatedly, you have to rewrite the plane again, making it impossible to display it repeatedly. was there.

[0010] Therefore, an LED display device shown in FIG. 6 has been proposed. FIG. 6 is a general circuit configuration block diagram of an LED display device, in which the LED display section 9 is configured with an LED dot matrix display. It is a display device that allows you to freely configure the size of the display section with any number of rows and columns.

The LED display section 9 includes a display RAM (V-R
AM) 7 contents (display data) are displayed, and V-RAM
7 converts the display data in the V-RAM 7 into parallel/serial (P/S) by sequentially receiving addresses corresponding to the content to be displayed from the screen controller 2 to the LED display section 9 through the MPX (multiplexer) 3. The data is transmitted to the LED display section 9 via the device 8 in the form of serial data.

The LED display section 9 side has a shift register for one horizontal raster corresponding to the number of display dots inside, and by scanning this for all rasters, the entire display screen is constructed. .

The screen controller 2 transmits a display address to the V-RAM 7 in synchronization with the timing of the LED display section 9, and also transmits a latch signal for switching the clock and raster to the LED display section 9, so that the LED display Part 9
This is to control the display screen.

The operation of the LED dot matrix display device will be described in detail below with reference to FIG. 7 showing the relationship between the LED display section and V-RAM, and FIG. 8 showing the relationship between the V-RAM address and transmission clock.

The address (V-RAM address) on the V-RAM (memory) shown in FIG. 7(d) corresponds to the LED display section 9 as shown in FIG. 7(c). 1 raster 8 dots corresponds to 8 bits of display data, and by sending out the display data of the V-RAM address in the horizontal direction of FIG. 7(d), the LED display section 9
1 to 16 rasters are displayed. In other words, as shown in FIGS. 7(a) and 7(b), the LED display unit 9 creates one screen by sequentially scanning the transmitted display data for 1 to 16 rasters in the horizontal direction. .

As shown in the unit configuration circuit diagram of FIG. 9, the display data (serial data) is taken into the shift register that constitutes the inside of the unit of the LED dot matrix display, and in the shift register, the display data is The data is sequentially transmitted to the LED dot matrix display constituting the LED display unit 9 in synchronization with the transmission clock, as shown in the relationship between display data and transmission clock in FIG. 10(b). This is similar to the CRT scanning method, and display data (8 bits) output from the V-RAM is sequentially input to the LED display section 9.

The V-RAM address shown in FIG. 8 is the display data 8b shown in FIG. 10(b) after eight transmission clocks.
Send it and change the V-RAM address from 0000H to 0.
Switch to 001H and repeat this operation to set V-RA.
The M address is switched to 00FFH to display one screen.

However, in the above-mentioned LED display device, when the display section is configured to have a very long digit size of tens or hundreds of digits, there are the following problems.

First, since the LED display section 9 is configured by connecting LED dot matrix displays in a daisy chain, the transmitted display data, latch signal, and transmission clock signal are transmitted as shown in FIG. First, the signal is transmitted to the next stage (next digit) LED dot matrix display after passing through a buffer that forms the inside of the LED dot matrix display unit. The signal that has passed through the buffer is input to the next stage LED dot matrix display, and the output signal is sent to the next stage to control one unit (1 unit of 16 x 16 dots) of the LED dot matrix display. Each time it passes, it passes through each buffer. For this reason, when configuring an LED display section with extremely long digits, the
As shown in (d), this will cause a shift in the timing for transmission, and as shown in Fig. 10(e), this will cause significant waveform deformation, resulting in distorted display or, in the worst case, no display at all. There was a problem that the function of the display device could no longer be fulfilled.

The above problem will be explained in detail. Figure 10 (
b) is a diagram showing the relationship between display data and transmission clock; inside the LED dot matrix display,
Display data is taken into the shift register as shown in FIG. 9 at the rising edge of the transmission clock. However, as shown in Figure 10(c) for the first digit of the display, the transmission clock captures the display data at the normal timing, but the nth digit is about to switch the raster of the very long digit display. Then, the timing shown in FIG. 10(d) is reached, and the transmission clock rises when the display data is switched. This is because while the transmit clock is transmitting up to n digits, each digit is passed through a buffer, which causes a large delay (delay time) between the input and output waveforms, which is a characteristic of buffers, due to the extremely long digits. At the n-th digit, which is about to change the raster shown in FIG. 10(a), the timing shown in FIG. 10(d) is reached. When it becomes as shown in FIG. 10(d), display data cannot be read at the timing of the transmission clock, and display becomes impossible.

Furthermore, due to the characteristic of the buffer that the rise time and fall time of the waveform are different, the transmission clock passes through the buffer many times, causing
), the waveform gradually becomes thinner and disappears at the n-th digit, making it impossible to read the display data and make it impossible to display.

[0022] In either case of FIG. 10(d) or FIG. 10(e), the problem is that it becomes difficult to import display data into a display with very long digits and display it appropriately. was there.

[0023] Second, LED display devices perform horizontal scanning in the same way as CRTs to create and display one screen, but in order to display an extremely long digit LED display, a large amount of Since display data must be transmitted and displayed, if the display data is transmitted using the same transmission clock as a display with several digits (short digits), the frame frequency, which is the time it takes to create one screen, will increase. , for very long digits, the commercial frequency (60
Hz) or lower, causing flickering.

[0024] In order to solve the above phenomenon, increasing the transmission clock makes it possible to transmit a large amount of display data and also increases the frame frequency, which eliminates flickering. Nico's LED
If the noise emitted from the display device increases and if the maximum frequency within the specifications of the transmission clock for the LED dot matrix display is exceeded, the operation of the LED dot matrix display cannot be guaranteed.

The present invention has been made in view of the above-mentioned circumstances, and can be applied to ultra-long digit display devices by simply dividing the display section, changing the arrangement of the display units, and adding a simple circuit. When displaying long digits, it is possible to prevent timing shifts or waveform distortions of the transmission clock that occur through many buffers to ensure proper display, and also to prevent flickering without increasing the frequency of the transmission clock. An object of the present invention is to provide a super-long digit display device and its display method that can display a clear display even if the number of digits is small.

[0026]

[Means for Solving the Problems] The invention according to claim 1 for solving the above-mentioned problem provides a very long digit display device that includes:
A display RAM into which display data is written, and the display RAM
A screen controller that gives the address of the display data to M and a display unit that displays the display data in the display RAM are arranged horizontally so as to scan in the vertical direction, and a plurality of aggregates of the display units are arranged. A super-long digit display section divided into display areas, and display data output from the display RAM are sent to the first
The display data is read from the display RAM or the buffer at the timing of the second signal from the screen controller, and the display data is read as serial data into the display section, corresponding to the divided display area. It is characterized by having a parallel/serial converter for transmitting data to.

[0027] In order to solve the above problem, the invention as set forth in claim 2 provides a display system for a super-long digit display device as set forth in claim 1, in which the display data is shifted vertically to the display unit of the display section. Generate a display RAM address for the display data from the screen controller to the display RAM so that the display data is sequentially output from the display RAM to the divided display areas, sequentially for each column of the display unit, and
The display data output from the screen controller is taken into a buffer at the timing of the first signal from the screen controller, and the display data is transferred from the display RAM or the buffer at the timing of the second signal from the screen controller to the parallel/serial converter. The data is captured by the parallel/serial converter and transmitted as serial data to the display unit.

[0028]

[Operation] According to the invention as claimed in claim 1, the display section with extremely long digits is divided into a plurality of display areas, and the conventional display unit is further rotated by 90 degrees so that the display unit in the display section can be scanned in the vertical direction. parallel/serial converters are arranged in the horizontal direction, and a number of parallel/serial converters corresponding to the display area are provided, and the display RAM is a buffer that takes in display data output from the display RAM at the timing of the first signal from the screen controller. A parallel/serial converter that is installed between the parallel/serial converters, captures display data at the timing of the second signal from the screen controller, and transmits it as serial data to the divided display areas of the display section in parallel. Since it is a long digit display device, the display section for very long digits can be divided and handled in the same way as short digit display, which prevents timing shifts or waveform distortions of the transmission clock and provides proper display. It is also possible to eliminate flickering without lowering the frame frequency.

According to the invention described in claim 2, in the ultra-long digit display device described in claim 1, the display data is shifted to the display units of the display section in the vertical direction sequentially in units of columns of each display unit. A display RAM address is generated from the screen controller to the display RAM so that display data is output continuously in each divided display area, and a buffer is used to capture the display data at the timing of the first signal from the screen controller. A display of a super-long digit display device in which the display data corresponding to the display areas divided from the display RAM is taken into each parallel/serial converter at the timing of the second signal from the screen controller, and output in parallel to the display area. By using this method, the display section with very long digits can be divided and treated in the same way as displaying short digits. Therefore, it is possible to prevent timing shifts or waveform distortions of the transmission clock and perform proper display. , it is also possible to eliminate flickering without lowering the frame frequency.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a super long beam L according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the basic circuit configuration of the ED display device, and FIG. 2 is a block diagram showing the basic circuit configuration of the ED display device.
FIG. 3 is a diagram showing the relationship between the ED display section and V-RAM, and FIG. 3 is a diagram showing the relationship between the transmission clock and V-RAM address in the ultra-long digit LED display device of this embodiment. Note that parts having the same configuration as those in FIGS. 6 and 11 will be described with the same reference numerals.

The ultra-long digit LED display device of this embodiment is shown in FIG.
The single display area shown in the relationship diagram between the LED display section and V-RAM is divided into multiple display areas, and each divided display area is sent to multiple display areas at the same time using the same transmission clock. The display data is transmitted, and the LED dot matrix display unit is generally arranged as shown in Fig. 5(a), as shown in Fig. 5(b).
This is a circuit that configures a 16×16 dot display unit with the arrangement rotated by 90 degrees as shown in the figure, and displays very long digits. The display RAM (V-
RAM) uses single-port-RAM.

To specifically explain the configuration of the ultra-long digit LED display device of this embodiment, the basic configuration is the same as the circuit configuration of the general LED display device shown in FIG. 6, but the differences are as follows. In this embodiment, since the display section is divided into two display areas, two P/S converters are provided, and the LE
The D display section is also divided into a display area a and a display area b, and 8-bit data output from the V-RAM 7 is divided and input to a P/S converter 8a and a P/S converter 8b. A buffer 11 is provided only between the V-RAM 7 and the P/S converter 8a, and display data is taken in by the buffer 11 at the timing of strobe signal 1, and display data is read in at the timing of strobe signal 2. is selectively taken into the P/S converter 8a and the P/S converter 8b, and the P/S converter 8a is sent to the P/S converter 8a at the timing of the transmission clock.
The data is converted into serial data by the P/S converter 8b and output to display area a and display area b.

V-RA in the V-RAM shown in FIG. 2(c)
As shown in FIG. 2(b)(b'), the M address is
It corresponds to display area a and display area b of the D display section. In other words, as shown in FIG. 2(c), if the V-RAM addresses in the V-RAM are divided into two stages, upper and lower, the upper V-RAM address is
Corresponding to display area a of the ED display section, the lower V-RAM
The address corresponds to display area b of the LED display section.

Furthermore, although the V-RAM addresses are continuous in the horizontal direction within the V-RAM in FIG. The 8-bit data is displayed twice in the vertical direction above to form one column display, first the first column of the first digit is displayed, then the first column of the second digit is displayed, and then The first column of the nth digit of the last digit in display area a is displayed, then the second column of digits 1 to n is displayed, and from then on, the display up to the 16th column is performed. It has become. This is done in the same way in both display area a and display area b, which are the LED display section divided.

Next, a display method in the ultra-long digit LED display device of this embodiment will be explained. FIG. 3 is a diagram showing the relationship between the transmission clock and the V-RAM address of the ultra-long digit LED display device of this embodiment, and the timing shown in FIG. 3 is a characteristic operation of this embodiment.

The V-RAM address shown in FIG. 3 is output from the screen controller (LED controller) 2 shown in FIG. The output V-RAM addresses are 0000H, 0400H, 0001H, 040 as shown in FIG.
1H, 0002H, 0402H, etc., Figure 2
(c) An address corresponding to the upper display area a and an address corresponding to the lower display area b are output alternately.

[0037] The output address is designed so that the display data of the address is taken in twice out of 8 transmission clocks, that is, every 4 clocks, and the address is 00 first.
It is designed to switch from 0H to 0400H. In this way, the display data corresponding to the V-RAM address is output alternately to display area a and display area b, and data for display area a is input to the P/S converter 8a. The data for display area b is input to the P/S converter 8b.

[0038] That is, the V-RAM address is 0000H.
, 0001H, 0002H, 0003H...
8 bits of display data for display area a is input from V-RAM 7 to P/S converter 8a via buffer 11, and V
-RAM address is 0400H, 0401H, 0402
In the case of H..., 8 bits of display data for display area b
is input from the V-RAM 7 to the P/S converter 8b.

As shown in FIG. 1, P/S converter a and V-
A buffer 11 is built in between the RAM 7 and the buffer 11. This buffer 11 takes in display data for display area a using strobe signal 1, and P/S converts the display data for display area a using strobe signal 2. The display data for the display area b is loaded from the V-RAM 7 into the P/S converter 8b by the strobe signal 2.

Next, with the same transmission clock, from the P/S converters 8a and 8b to the display areas a and b,
Display data for b is transmitted at the same timing. As a result, display data is displayed in each of the divided display areas a and b. In FIG. 3, a white arrow indicates strobe signal 1, and a black arrow indicates strobe signal 2.

FIG. 2(a) is a diagram showing the data shift direction of this embodiment. As shown in FIGS. 2(a) and 2(a'), by using one unit of 16×16 dots of an LED dot matrix display and arranging them by rotating them by 90 degrees, it is possible to create a single horizontal However, each digit is oriented vertically. Therefore, as shown in Figure 2(a), after data is transmitted to the first column of the first digit, the digits are sequentially changed to the second digit and the first column, and the data is shifted vertically. Therefore, after the display data of the first column of all digits is sent, the display data is sent sequentially to the second column of the first digit, the second column of the second digit, and then the display data of the second column of all digits is sent. In this way, display data for all columns of all digits is transmitted, and the display data is displayed on the LED dot matrix display. For this reason, Fig. 2(b)(b'
), the V in the V-RAM 7 is sent to the LED display section 9.
-RAM addresses are made to correspond.

As a result, since display data for each area can be transmitted from one V-RAM 7 to two divided display areas a and b using the same transmission clock, the divided display It becomes possible to display areas at the same timing, and since the display screen of very long digits can be treated as a divided display section of short digits, it becomes possible to display very long digits. Further, data shift will be performed in the form shown in FIG. 2(a).

The block diagram in FIG. 4 shows the ultra-long digit LED in FIG.
It is a circuit configuration block diagram of a super long digit LED display device connected to a CPU 1 and other circuits, based on a block diagram of the basic configuration of a display circuit. The LED display section 9 in FIG.
As shown in (a), this is an embodiment of a one-line super-long digit type display section. Incidentally, FIG. 2(b) shows the V-RAM addresses for 64 units in one row horizontally in the embodiment shown in FIG. 4, in which the display section is constituted by a dot matrix display.

An embodiment of the ultra-long digit LED display device shown in FIG. 4 will be described below. address bus from CPU1,
A screen controller (LED controller) 2 and an MPX (multiplexer) 3 are connected to the data bus. The V-RAM address from the screen controller 2 or the address from the CPU 1 is input to the V-RAM (display RAM) 7 by switching the MPX3.
7 outputs display data to P/S converters 8a and 8b at the timing of strobe signals 1 and 2 output from the screen controller 2. The display data taken into the P/S converter 8 is transmitted to the LED display section 9 in synchronization with the shift clock.

[0045] Then, the LEDs shown in FIGS. 2(b) and 2(b')
The display section 9 has 64 units per line horizontally, and these 6
This is an example in which the display section is divided into 32 units x 2 instead of 4 units.

The display method in the ultra-long digit LED display device of the embodiment shown in FIG. 4 will be explained in detail. The first V-RAM address of the first raster of all digits in display area a in FIG. 2(b') is 0000H, the last V-RAM address is 003FH, and the second raster start address is 00.
It will be 40H. In display area b, the start address of the first raster starts from 0400H and ends at 041HF, and the start address of the second raster starts from 0420H.

Since the V-RAM address is switched twice for one vertical raster of one unit (one digit), the first address of the display area a is the V-RAM address.
When it becomes 0000H above, the end address of the first column of display area a becomes 003FH. By scanning this one column address from the 1st column to the 16th column by switching all the digits, the display will show from 0000H to 03FFH.
The display data up to this point will be displayed. In display area b, the start address of the 32nd unit is 0400H.
The end address of the 32nd unit is 07FFH.

The above embodiment is the simplest embodiment because the start address 0400H of display area b is located at a well-defined position in hexadecimal.

Furthermore, in the above embodiment, when the start address of display area b is at a position unrelated to hexadecimal, for example, when the start address is 0403H, the LED controller (LEDC) 2 in FIG. By adding an adder between the controller and MPX3, it is possible to add a specific number to the V-RAM address value input from the controller to the adder and adjust and determine the start address of display area b. Become.

According to this embodiment, in a dot matrix display device such as an LED dot matrix display device, a lamp dot matrix display device, or a fluorescent tube dot matrix display device, an LE with a super long digit size in the horizontal direction can be used.
When configuring the D display section, it is possible to suppress the increase in the frequency of the transmission clock, and although it was difficult to increase the frame frequency with conventional technology, by dividing the display section with very long digits, it is possible to suppress the increase in the frequency of the transmission clock. Since it can be treated as a display, it is possible to increase the frame frequency, which has the effect of eliminating flickering.

Furthermore, since the display section for very long digits can be divided to perform the same operation as the display for short digits, there is no need to go through many buffers, and there is no need to go through a large number of buffers. This has the effect of preventing waveform deformation, eliminating display disturbances, and making it possible to perform appropriate display.

Furthermore, as shown in FIG. 2, the V-RAM address corresponding to the extremely long digit display section is adjusted to the timing shown in FIG. By performing switching and obtaining (generating) a V-RAM address, display data corresponding to different display positions on the same screen can be transmitted in 8 transmission clocks, making it possible to display extremely long digits. It is effective and also
The circuit configuration for the divided display areas requires only the divided number of P/S converters 8, buffers 11, and strobe signals, and is advantageous in that it can be realized with a simple configuration.

[0053]

According to the invention as claimed in claim 1, the display section with extremely long digits is divided into a plurality of display areas, and the display unit in the display section is further divided into 90 parts so that the display unit in the display part can be scanned in the vertical direction.゜It is rotated and arranged horizontally, and a number of parallel/serial converters corresponding to the display area are provided, and a buffer is displayed that captures the display data output from the display RAM at the timing of the first signal from the screen controller. A parallel/serial converter that is installed between the RAM and the parallel/serial converter, captures display data at the timing of a second signal from the screen controller, and transmits the data in parallel to the divided display areas of the display unit as serial data. Since this is a super-long digit display device, the super-long digit display section can be divided and handled in the same way as short digit display, which prevents transmission clock timing shifts or waveform distortions and ensures proper display. It also has the effect of eliminating flickering without lowering the frame frequency.

According to the invention set forth in claim 2, in the ultra-long digit display device set forth in claim 1, the display data is shifted to the display units of the display section in the vertical direction sequentially in units of columns of each display unit. A display RAM address is generated from the screen controller to the display RAM so that display data is output continuously in each divided display area, and a buffer is used to capture the display data at the timing of the first signal from the screen controller. A display of a super-long digit display device in which the display data corresponding to the display areas divided from the display RAM is taken into each parallel/serial converter at the timing of the second signal from the screen controller, and output in parallel to the display area. By using this method, the display section with very long digits can be divided and treated in the same way as displaying short digits. Therefore, it is possible to prevent timing shifts or waveform distortions of the transmission clock and perform proper display. , which also has the effect of eliminating flickering without lowering the frame frequency.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration block diagram of a super long digit LED display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the relationship between the LED display section and V-RAM of the ultra-long digit LED display device of this embodiment.

FIG. 3 is a diagram showing the relationship between the transmission clock and V-RAM address of the ultra-long digit LED display device of this embodiment.

FIG. 4 is a circuit configuration block diagram of a specific example of a super long digit LED display device.

FIG. 5 is a diagram showing a data shift direction of an LED dot matrix display.

FIG. 6 is a circuit configuration block diagram of a general LED display device.

FIG. 7 is a diagram showing the relationship between the LED display section and V-RAM in FIG. 6;

FIG. 8 is a diagram showing the relationship between the transmission clock to the LED display section and the V-RAM address in FIG. 6;

FIG. 9 is a circuit diagram of a unit configuration inside the LED dot matrix display.

FIG. 10 is a diagram showing the configuration of a display section and the timing of display data and transmission clocks in a super-long digit display device.

FIG. 11 is a circuit configuration block diagram of a conventional LED dot matrix display device.

FIG. 12 is a diagram showing the configuration relationship between a conventional LED display capacity and a V-RAM.

[Explanation of symbols]

1 CPU 2 Screen controller 3 Multiplexer 4 Bus driver 5 Oscillator 6 Screen controller frequency divider 7 Screen RAM 8 P/S converter 9 LED display section 10 Transmission frequency divider 11 Buffer

Claims (2)

[Claims] [Claim 1] Display RAM into which display data is written.
A screen controller that gives the address of the display data to the display RAM, and a display unit that displays the display data in the display RAM are arranged in the horizontal direction so as to scan in the vertical direction, and a plurality of the display units are a super-long digit display section that divides the aggregate into a plurality of display areas; a buffer that captures display data output from the display RAM at the timing of a first signal from the screen controller; It is characterized by comprising a parallel/serial converter that corresponds to each of the above, captures display data from the display RAM or the buffer at the timing of a second signal from the screen controller, and transmits it to the display section as serial data. Ultra-long digit display device. 2. The ultra-long digit display device according to claim 1, wherein the display data is sequentially shifted to the display units of the display section in the vertical direction column by column of the display units,
A display RAM address of the display data is generated from the screen controller to the display RAM so that the display data is sequentially output from the display area divided from M, and the display data output from the display RAM is transferred to the first address from the screen controller. The display data is fetched into a buffer at the timing of a signal, the display data is fetched from the display RAM or the buffer into a parallel/serial converter at the timing of a second signal from the screen controller, and the display data is displayed as serial data by the parallel/serial converter. A display method for a super-long digit display device characterized by transmitting data to the department.