JPH04313276A - Semiconductor strain gauge - Google Patents

Semiconductor strain gauge

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Publication number
JPH04313276A
JPH04313276A JP7799191A JP7799191A JPH04313276A JP H04313276 A JPH04313276 A JP H04313276A JP 7799191 A JP7799191 A JP 7799191A JP 7799191 A JP7799191 A JP 7799191A JP H04313276 A JPH04313276 A JP H04313276A
Authority
JP
Japan
Prior art keywords
gauge
crystal substrate
semiconductor strain
single crystal
gauge element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP7799191A
Other languages
Japanese (ja)
Inventor
Yasuhiro Koike
靖弘 小池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Industries Corp
Original Assignee
Toyoda Automatic Loom Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyoda Automatic Loom Works Ltd filed Critical Toyoda Automatic Loom Works Ltd
Priority to JP7799191A priority Critical patent/JPH04313276A/en
Publication of JPH04313276A publication Critical patent/JPH04313276A/en
Withdrawn legal-status Critical Current

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  • Measuring Fluid Pressure (AREA)
  • Pressure Sensors (AREA)

Abstract

PURPOSE:To provide a semiconductor strain gauge where a gauge element with a small change in output characteristics due to temperature increase is formed regarding a semiconductor strain gauge which is obtained by forming the gauge element with a piezo resistance effect on an Si single-crystal substrate as a high-impurity concentration region. CONSTITUTION:A high-impurity concentration region (low specific resistance) is provided at (high specific resistance) Si single-crystal substrates 2 and 7 which contain an n-type impurity at low concentration, thus forming gauge elements 3 and 8. Namely, the gauge elements 3 and 8 are formed according to a difference in specific resistance instead of pn junction, thus eliminating poor influence to output characteristics at a high-temperature region. Also, even if a high-impurity concentration region is formed at the Si single-crystal substrate which does not contain impurities at all, semiconductor strain gauges 1 and 6 with less change in output characteristics due to temperature increase are obtained.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、ゲージ素子の有するピ
エゾ抵抗効果を利用して圧縮力の検出を行う半導体圧力
センサに用いられる半導体歪ゲージに係り、特に該ゲー
ジ素子をSi単結晶基板に高不純物濃度領域として形成
する半導体歪ゲージに関する。
[Field of Industrial Application] The present invention relates to a semiconductor strain gauge used in a semiconductor pressure sensor that detects compressive force by utilizing the piezoresistance effect of a gauge element, and more particularly, the present invention relates to a semiconductor strain gauge for use in a semiconductor pressure sensor that detects compressive force by utilizing the piezoresistance effect of a gauge element. The present invention relates to a semiconductor strain gauge formed as a high impurity concentration region.

【0002】0002

【従来の技術】従来の圧力センサとしては、加えられた
圧縮力に対応して生ずる起歪体の歪みを、接着剤を用い
て起歪体に複数個貼付し、ホイートストンブリッジ回路
を形成するよう電気的に結線した歪ゲージに伝達し、こ
の歪ゲージの抵抗変化に基づき生じる電圧出力の大きさ
を検出するように構成されていた。それに用いられる歪
ゲージも近年においてはシリコン(Silicon, 
以下Siとする) を中心とした半導体単結晶よりなる
半導体歪ゲージが主流を占めるようになってきた。しか
し、半導体歪ゲージを接着剤を用いて起歪体に複数個貼
付してホイートストンブリッジ回路を形成するよう結線
してなる半導体圧力センサは、その製造にあたり特に貼
付に際して複雑で高いノウハウを要することから、特性
のバラツキが大きくコスト高となり、また貼付に用いら
れる接着剤はクリープ、ヒステリシス等の悪影響を招く
上に歪みの伝達を確実になさず、半導体圧力センサの信
頼性を著しく低減させるという欠点があった。そこで、
半導体圧力センサに用いられる半導体歪ゲージを、Si
単結晶基板中に不純物をドープすることにより形成する
ことが行われてきた。
[Prior Art] Conventional pressure sensors use adhesives to form a Wheatstone bridge circuit by attaching a plurality of strain-generating bodies to a strain-generating body using an adhesive to measure the distortion of a strain-generating body that occurs in response to an applied compressive force. The voltage was transmitted to an electrically connected strain gauge, and the magnitude of the voltage output generated based on the resistance change of the strain gauge was detected. In recent years, the strain gauges used for this purpose have also been made of silicon (Silicon,
Semiconductor strain gauges made of semiconductor single crystals, mainly Si (hereinafter referred to as Si), have become mainstream. However, semiconductor pressure sensors, which are made by attaching multiple semiconductor strain gauges to a strain-generating body using an adhesive and connecting them to form a Wheatstone bridge circuit, are complicated and require a high level of know-how, especially when attaching them. The disadvantages are that the characteristics vary widely and the cost is high, and the adhesive used for pasting causes negative effects such as creep and hysteresis, and does not ensure strain transmission, which significantly reduces the reliability of the semiconductor pressure sensor. there were. Therefore,
Semiconductor strain gauges used in semiconductor pressure sensors are made of Si
Formation has been carried out by doping impurities into a single crystal substrate.

【0003】図2は従来のダイヤフラム型の半導体圧力
センサに用いられる半導体歪ゲージの構成例を示す。入
力電極、出力電極は省略している。同図に示すように半
導体歪ゲージ11は、単結晶Siの一部を薄く加工(数
十μm)したSi単結晶基板からなる受圧ダイヤフラム
12に、不純物をドープして一体的にゲージ素子13が
形成されている。このゲージ素子13はn型のSi単結
晶基板にイオン注入法や拡散法等を用いて、ボロン等の
p型の不純物がドープされて形成されている。受圧ダイ
ヤフラム12は支持部14に接合されている。また、こ
の逆に、ゲージ素子13はp型のSi単結晶基板にn型
の不純物がドープされて形成される場合もある。
FIG. 2 shows an example of the structure of a semiconductor strain gauge used in a conventional diaphragm type semiconductor pressure sensor. Input electrodes and output electrodes are omitted. As shown in the figure, the semiconductor strain gauge 11 includes a pressure receiving diaphragm 12 made of a Si single crystal substrate made by processing a portion of single crystal Si into a thin layer (several tens of μm), doped with impurities, and integrated with a gauge element 13. It is formed. This gauge element 13 is formed by doping an n-type Si single crystal substrate with a p-type impurity such as boron using an ion implantation method, a diffusion method, or the like. The pressure receiving diaphragm 12 is joined to the support portion 14. Conversely, the gauge element 13 may be formed by doping a p-type Si single crystal substrate with an n-type impurity.

【0004】受圧ダイヤフラム12の圧導入部12aに
圧導入口12bより気体や液体が導入され、受けた圧力
により生ずる歪みを、ゲージ素子13の抵抗変化から測
定する。圧導入部12aで受けた圧力によりダイヤフラ
ム12が変形し、ダイヤフラム12に形成されるゲージ
素子13にも応力が発生する。この応力による抵抗率変
化によって電気抵抗が変化するという半導体素子のピエ
ゾ抵抗効果、つまり、外部から加えられた力によって、
半導体結晶内のエネルギー構造が変化し、キャリアの相
対的変化に基づいて固有抵抗が変わる現象を利用してい
る。
Gas or liquid is introduced into the pressure introduction part 12a of the pressure receiving diaphragm 12 through the pressure introduction port 12b, and the strain caused by the received pressure is measured from the resistance change of the gauge element 13. The diaphragm 12 is deformed by the pressure received by the pressure introduction part 12a, and stress is also generated in the gauge element 13 formed on the diaphragm 12. The piezoresistance effect of the semiconductor element changes the electrical resistance due to the change in resistivity caused by this stress, that is, due to the force applied from the outside,
It utilizes the phenomenon that the energy structure within a semiconductor crystal changes and the specific resistance changes based on the relative change in carriers.

【0005】図3に、従来の直交型の半導体圧力センサ
に用いられる半導体歪ゲージの構成例を示す。入力電極
、出力電極、上部台座は省略している。同図に示すよう
に、半導体歪ゲージ16は厚めに形成されて支持基台を
兼ねる単結晶Si基板17に、不純物をドープして一体
的にゲージ素子18が形成されている。ダイヤフラム型
のゲージ素子13と同様に、この直交型のゲージ素子1
8も、n型のSi単結晶基板にイオン注入法や拡散法等
を用いて、ボロン等のp型の不純物がドープされて形成
されている。また、この逆に、p型のSi単結晶基板に
n型の不純物がドープされて形成される場合もある。
FIG. 3 shows an example of the structure of a semiconductor strain gauge used in a conventional orthogonal semiconductor pressure sensor. The input electrode, output electrode, and upper pedestal are omitted. As shown in the figure, the semiconductor strain gauge 16 has a gauge element 18 formed integrally with a monocrystalline Si substrate 17 that is formed thick and also serves as a support base, doped with impurities. Similar to the diaphragm type gauge element 13, this orthogonal type gauge element 1
8 is also formed by doping an n-type Si single crystal substrate with a p-type impurity such as boron using an ion implantation method, a diffusion method, or the like. Conversely, a p-type Si single crystal substrate may be doped with an n-type impurity.

【0006】直交型の半導体圧力センサに用いられる半
導体歪ゲージ16の場合、ゲージ素子18の結晶軸の方
向は感度を左右するので、予め目的に沿うような結晶面
を上面18aとするように形成される。例えば、ゲージ
素子18となるp型不純物層(あるいはn型不純物層)
はその上面18aが(110)面となるように形成され
た後、<001>方向と  外1  方向から各々45
°の方向に入力電極と出力
In the case of the semiconductor strain gauge 16 used in an orthogonal type semiconductor pressure sensor, since the direction of the crystal axis of the gauge element 18 affects the sensitivity, it is formed in advance so that the upper surface 18a is a crystal plane that meets the purpose. be done. For example, a p-type impurity layer (or an n-type impurity layer) that becomes the gauge element 18
is formed so that its upper surface 18a is a (110) plane, and then 45
Input electrode and output in the direction of °

【0007】[0007]

【外1】[Outside 1]

【0008】電極の対を設け、入力電極に電流を流しな
がらゲージ素子18の上面18aに垂直に圧縮力を作用
させ、上記電流の流れる方向と直交する方向から上記圧
縮力に対応した電圧を取り出すようにしている。
A pair of electrodes is provided, and a compressive force is applied perpendicularly to the upper surface 18a of the gauge element 18 while a current is flowing through the input electrode, and a voltage corresponding to the compressive force is extracted from a direction perpendicular to the direction in which the current flows. That's what I do.

【0009】上記のように形成される半導体歪ゲージの
ゲージ素子は、ダイヤフラム型及び直交型の半導体セン
サの別にかかわらず、n型Si単結晶基板中にp型不純
物がドープされることにより、あるいはp型Si単結晶
基板中にn型不純物がドープされることにより形成され
ているから、pn接合が形成されることになる。従って
、n型Si単結晶基板とp型不純物領域あるいはp型S
i単結晶基板とn型不純物領域との境界部には、pn接
合による電位バリアが形成されることになり、通常は電
流流路であるゲージ素子を流れる電流はバルク(n型S
i単結晶基板あるいはp型Si型結晶基板)中に漏れる
ことがない。
The gauge element of the semiconductor strain gauge formed as described above, regardless of whether it is a diaphragm type or an orthogonal type semiconductor sensor, is produced by doping an n-type Si single crystal substrate with a p-type impurity or Since it is formed by doping an n-type impurity into a p-type Si single crystal substrate, a pn junction is formed. Therefore, an n-type Si single crystal substrate and a p-type impurity region or a p-type S
i A potential barrier is formed by a pn junction at the boundary between the single crystal substrate and the n-type impurity region, and the current flowing through the gauge element, which is normally a current flow path, flows through the bulk (n-type S
There is no leakage into the i-single crystal substrate or p-type Si-type crystal substrate.

【0010】0010

【発明が解決しようとする課題】上記構成の半導体歪ゲ
ージでは、不純物をドープしてpn接合を設けることに
より、その境界部に生じる電位バリアを利用してゲージ
素子を形成している。ところが、このpn接合の境界部
に生じる電位バリアは温度の上昇とともに低くなるので
、高温領域(約150°C以上)ではここからの漏れ電
流が増大し電位バリアの効果が弱くなってしまい、その
ため出力特性に大きな悪影響が生ずるという不都合があ
った。
In the semiconductor strain gauge having the above structure, a pn junction is formed by doping impurities, and a potential barrier generated at the boundary is used to form a gauge element. However, the potential barrier that occurs at the boundary of this pn junction decreases as the temperature rises, so in high-temperature regions (above about 150°C), the leakage current increases and the potential barrier becomes less effective. This has the disadvantage that it has a large adverse effect on the output characteristics.

【0011】本発明は、上記従来の問題点に鑑み、温度
上昇によっても出力特性の変化が少ないゲージ素子が形
成された半導体歪ゲージを提供することを目的とする。
SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a semiconductor strain gauge in which a gauge element is formed whose output characteristics do not change much even when the temperature rises.

【0012】0012

【課題を解決するための手段】本発明の半導体歪ゲージ
は、上記目的を達成するために、Si単結晶基板に高不
純物濃度領域を設けてゲージ素子を形成し、該ゲージ素
子の有するピエゾ抵抗効果を利用して圧縮力の検出を行
う半導体歪ゲージにおいて、前記ゲージ素子を、低不純
物濃度のSi単結晶基板に該Si単結晶基板に含有され
る不純物と同型の高不純物濃度領域として形成したもの
であり、また前記ゲージ素子を、不純物を含まないSi
単結晶基板に高不純物濃度領域として形成したものであ
る。
[Means for Solving the Problems] In order to achieve the above object, the semiconductor strain gauge of the present invention includes a gauge element formed by providing a high impurity concentration region in a Si single crystal substrate, and a piezoresistance that the gauge element has. In a semiconductor strain gauge that detects compressive force by utilizing the effect, the gauge element is formed on a low impurity concentration Si single crystal substrate as a high impurity concentration region having the same type of impurity as the impurity contained in the Si single crystal substrate. and the gauge element is made of impurity-free Si.
It is formed as a high impurity concentration region on a single crystal substrate.

【0013】[0013]

【作用】ゲージ素子は、低不純物濃度(高比抵抗)のS
i単結晶基板に、該Si単結晶基板に含有される不純物
と同型の高不純物濃度(低比抵抗)領域として、比抵抗
の差異によって形成されることになる。pn接合によっ
てゲージ素子が形成されるときには、温度上昇による出
力特性への悪影響があるのに対し、比抵抗の差異によっ
てゲージ素子が形成されるから、温度上昇によってもゲ
ージ素子とSi単結晶基板の両者の抵抗比があまり変化
しないので、温度変化による出力特性の変化が少ない。 また、不純物を含有しないSi単結晶基板は、上記にお
いて低濃度に含んでいた不純物の濃度が零となった場合
と考えることができ、作用は同じである。
[Operation] The gauge element is made of S with low impurity concentration (high specific resistance).
A high impurity concentration (low resistivity) region of the same type as the impurity contained in the Si single crystal substrate is formed in the i single crystal substrate due to the difference in resistivity. When a gauge element is formed by a p-n junction, a rise in temperature has an adverse effect on the output characteristics, but since a gauge element is formed by a difference in resistivity, the difference between the gauge element and the Si single-crystal substrate can be affected even by a rise in temperature. Since the resistance ratio between the two does not change much, there is little change in output characteristics due to temperature changes. Further, a Si single crystal substrate containing no impurities can be considered as a case in which the concentration of impurities contained at a low concentration in the above case becomes zero, and the effect is the same.

【0014】[0014]

【実施例】以下、本発明の実施例について、図面を参照
しながら説明する。図1(a) 及び(b) は、各々
本発明の第1の実施例の半導体歪ゲージの構成を示す図
で、図1(a) は、ダイヤフラム型の半導体圧力セン
サに、図1(b) は、直交型の半導体圧力センサに用
いられる場合を示す。
Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1(a) and (b) are diagrams each showing the configuration of a semiconductor strain gauge according to a first embodiment of the present invention, and FIG. ) indicates the case where it is used in an orthogonal type semiconductor pressure sensor.

【0015】図1(a) において半導体歪ゲージ1は
、n型の不純物を低濃度に含有する(高比抵抗)Si単
結晶基板からなる受圧ダイヤフラム2に、n型の不純物
を高濃度にドープすることによりn型不純物領域(低比
抵抗)のゲージ素子3が形成されて、支持部4に接合さ
れている。受圧ダイヤフラム2の圧導入部2aに圧導入
口2bより気体や液体が導入される。また、これとは別
の例として、受圧ダイヤフラム2内部は基準圧力として
密封し、ダイヤフラム2に加わる外圧をセンスする方法
もある。
In FIG. 1(a), a semiconductor strain gauge 1 has a pressure receiving diaphragm 2 made of a Si single crystal substrate containing a low concentration of n-type impurities (high specific resistance) doped with a high concentration of n-type impurities. As a result, a gauge element 3 having an n-type impurity region (low resistivity) is formed and is bonded to the support portion 4. Gas or liquid is introduced into the pressure introduction portion 2a of the pressure receiving diaphragm 2 through the pressure introduction port 2b. As another example, there is a method in which the inside of the pressure receiving diaphragm 2 is sealed as a reference pressure and the external pressure applied to the diaphragm 2 is sensed.

【0016】不純物のドーピングは、イオン注入法や拡
散法が用いられるが、これに限られないことは勿論であ
り、以下同様に行われる。また、図1(b) において
、半導体歪ゲージ6は、支持基台を兼ねるn型の不純物
を低濃度に含有する(高比抵抗)厚めのSi単結晶基板
7に、n型の不純物を高濃度にドープすることによりn
型不純物領域(低比抵抗)のゲージ素子8が形成されて
いる。このとき、ゲージ素子8の上面は所定の結晶面と
なるように形成される。例えば、ゲージ素子8は(11
0)面を上面とし、且つ<001>方向と、  外2 
 方向から各々45°の方向に不図示の入力電極と出力
電極が形成さ
[0016] The impurity doping is performed using an ion implantation method or a diffusion method, but it is needless to say that it is not limited to these methods, and the same method can be used hereinafter. In addition, in FIG. 1(b), the semiconductor strain gauge 6 has a thick Si single crystal substrate 7 containing a low concentration of n-type impurities (high specific resistance) that also serves as a support base, and a semiconductor strain gauge 6 that has a high concentration of n-type impurities. By doping to a concentration n
A gauge element 8 of type impurity region (low resistivity) is formed. At this time, the upper surface of the gauge element 8 is formed to be a predetermined crystal plane. For example, the gauge element 8 is (11
0) The surface is the top surface, and the <001> direction, and the outer 2
Input electrodes and output electrodes (not shown) are formed at 45 degrees from the direction.

【0017】[0017]

【外2】[Outside 2]

【0018】れる。図1(a) 及び(b) の半導体
歪ゲージの動作は、従来例と同様である。以上のように
、本発明の第1の実施例では、電流流路であるゲージ素
子3,8を比抵抗の差異によって各々Si単結晶基板2
,7に形成している。この場合、常温でも多少境界部分
での漏れ電流があるが、温度が上昇しても両者の抵抗比
があまり変化しないため、従来のようにpn接合を用い
てゲージ素子を形成したときよりも、温度変化に対する
出力特性の変化が少ない、また、同型の不純物のドープ
によって、しかも不純物濃度の差異により(比抵抗の差
異により)Si単結晶基板にゲージ素子を形成すること
は、従来のpn接合によりゲージ素子を形成するのに比
べて、工程数は増えることがなく比較的楽といえる。
[0018] The operation of the semiconductor strain gauge shown in FIGS. 1(a) and 1(b) is similar to that of the conventional example. As described above, in the first embodiment of the present invention, the gauge elements 3 and 8, which are current flow paths, are connected to the Si single-crystal substrate 2 by the difference in resistivity.
, 7. In this case, there is some leakage current at the boundary even at room temperature, but the resistance ratio between the two does not change much even when the temperature rises, so it is more effective than when the gauge element is formed using a pn junction as in the past. It is possible to form a gauge element on a Si single crystal substrate by doping with the same type of impurity, and due to the difference in the impurity concentration (due to the difference in specific resistance), which has little change in output characteristics due to temperature changes. Compared to forming a gauge element, the number of steps does not increase and it can be said to be relatively easy.

【0019】また、図示しないが、第2の実施例として
、次のような例が考えられる。それは、図1(a) 及
び(b) において、Si単結晶基板2,7をp型の不
純物を低濃度に含有する(高比抵抗)基板とし、ゲージ
素子3,8をp型の不純物を高濃度にドープすることに
よりp型不純物領域(低比抵抗)として形成する例であ
る。 これは、第1の実施例と比べて、p型とn型が逆になっ
ている例である。
Although not shown, the following example can be considered as a second embodiment. In FIGS. 1(a) and 1(b), the Si single crystal substrates 2 and 7 are substrates containing p-type impurities at a low concentration (high specific resistance), and the gauge elements 3 and 8 are substrates containing p-type impurities at a low concentration. This is an example of forming a p-type impurity region (low resistivity) by doping at a high concentration. This is an example in which the p-type and n-type are reversed compared to the first embodiment.

【0020】さらに、図示しないが、第3の実施例とし
て、次のような例が考えられる。それは、第1の実施例
において、Si単結晶基板2,7を不純物を含まないS
i単結晶基板とする例である。これは、第1の実施例に
おけるSi単結晶基板の、もともと低濃度であったn型
の不純物濃度を無限に零に近づけていった場合に相当す
る。
Furthermore, although not shown, the following example can be considered as a third embodiment. In the first embodiment, the Si single crystal substrates 2 and 7 are replaced with impurity-free S
i This is an example of a single crystal substrate. This corresponds to the case where the n-type impurity concentration, which was originally a low concentration, in the Si single crystal substrate in the first embodiment is made infinitely close to zero.

【0021】さらにまた、図示しないが、第4の実施例
として、次のような例も考えられる。それは、第2の実
施例において、Si単結晶基板2,7を不純物を含まな
いSi単結晶基板とする例である。これは、第2の実施
例におけるSi単結晶基板の、もともと低濃度であった
p型の不純物濃度を無限に零に近づけていった場合に相
当する。
Furthermore, although not shown, the following example may be considered as a fourth embodiment. This is an example in which the Si single crystal substrates 2 and 7 in the second embodiment are Si single crystal substrates containing no impurities. This corresponds to the case where the p-type impurity concentration, which was originally low in the Si single crystal substrate in the second embodiment, is made infinitely close to zero.

【0022】以上のように、本発明の上記第2乃至第4
の実施例の半導体圧力センサも、濃度零を含む低不純物
濃度(高比抵抗)のSi単結晶基板中に同型の高不純物
濃度(低比抵抗)領域を設けてゲージ素子を形成してい
るのである。つまり、ゲージ素子をpn接合を用いずに
、比抵抗の差異によって形成しているのである。
As described above, the second to fourth aspects of the present invention
In the semiconductor pressure sensor of the embodiment, the gauge element is also formed by providing a high impurity concentration (low resistivity) region of the same type in a Si single crystal substrate with a low impurity concentration (high resistivity) including zero concentration. be. In other words, the gauge element is formed based on the difference in specific resistance without using a pn junction.

【0023】従って、上記第1乃至第4の何れの実施例
においても、pn接合の境界部に生ずる電位バリアを利
用する構成ではないから、温度上昇による出力特性への
悪影響は少ない。
Therefore, in any of the first to fourth embodiments described above, since the structure does not utilize the potential barrier generated at the boundary of the pn junction, there is little adverse effect on the output characteristics due to temperature rise.

【0024】[0024]

【発明の効果】上記のように、本発明によれば、半導体
歪ゲージのゲージ素子は比抵抗の差異によって形成され
ているので、温度変化による出力特性変化が少ない。ま
た、ゲージ素子を形成する工程が比較的楽になる。
As described above, according to the present invention, since the gauge elements of the semiconductor strain gauge are formed by differences in specific resistance, there is little change in output characteristics due to temperature changes. Furthermore, the process of forming the gauge element becomes relatively easy.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の実施例の半導体歪ゲージの構成例の断
面図で、(a) はダイヤフラム型、(b) は直交型
半導体圧力センサに用いられる場合を示す。
FIG. 1 is a cross-sectional view of a configuration example of a semiconductor strain gauge according to an embodiment of the present invention, in which (a) shows a diaphragm type, and (b) shows a case where it is used in an orthogonal type semiconductor pressure sensor.

【図2】従来のダイヤフラム型の半導体圧力センサに用
いられる半導体歪ゲージの構成例の断面図である。
FIG. 2 is a sectional view of a configuration example of a semiconductor strain gauge used in a conventional diaphragm type semiconductor pressure sensor.

【図3】従来の直交型の半導体圧力センサ用いられる半
導体歪ゲージの構成例を示す図で、(a) は平面図、
(b) は断面図である。
FIG. 3 is a diagram showing an example of the configuration of a semiconductor strain gauge used in a conventional orthogonal semiconductor pressure sensor, in which (a) is a plan view;
(b) is a cross-sectional view.

【符号の説明】[Explanation of symbols]

1,6      半導体歪ゲージ 2,7      Si単結晶基板 3,8      ゲージ素子 1,6 Semiconductor strain gauge 2,7 Si single crystal substrate 3,8 Gauge element

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  Si単結晶基板に高不純物濃度領域を
設けてゲージ素子を形成し、該ゲージ素子の有するピエ
ゾ抵抗効果を利用して圧縮力の検出を行う半導体歪ゲー
ジにおいて、前記ゲージ素子を、低不純物濃度のSi単
結晶基板に該Si単結晶基板に含有される不純物と同型
の高不純物濃度領域として形成することを特徴とする半
導体歪ゲージ。
1. A semiconductor strain gauge in which a gauge element is formed by providing a high impurity concentration region on a Si single crystal substrate, and compressive force is detected by utilizing the piezoresistance effect of the gauge element, the gauge element being A semiconductor strain gauge characterized in that it is formed in a low impurity concentration Si single crystal substrate as a high impurity concentration region of the same type as the impurity contained in the Si single crystal substrate.
【請求項2】  Si単結晶基板に高不純物濃度領域を
設けてゲージ素子を形成し、該ゲージ素子の有するピエ
ゾ抵抗効果を利用して圧縮力の検出を行う半導体歪ゲー
ジにおいて、前記ゲージ素子を、不純物を含まないSi
単結晶基板に高不純物濃度領域として形成することを特
徴とする半導体歪ゲージ。
2. A semiconductor strain gauge in which a gauge element is formed by providing a high impurity concentration region on a Si single crystal substrate, and compressive force is detected by utilizing the piezoresistance effect of the gauge element, wherein the gauge element is , impurity-free Si
A semiconductor strain gauge characterized by forming a high impurity concentration region on a single crystal substrate.
JP7799191A 1991-04-10 1991-04-10 Semiconductor strain gauge Withdrawn JPH04313276A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7799191A JPH04313276A (en) 1991-04-10 1991-04-10 Semiconductor strain gauge

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7799191A JPH04313276A (en) 1991-04-10 1991-04-10 Semiconductor strain gauge

Publications (1)

Publication Number Publication Date
JPH04313276A true JPH04313276A (en) 1992-11-05

Family

ID=13649295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7799191A Withdrawn JPH04313276A (en) 1991-04-10 1991-04-10 Semiconductor strain gauge

Country Status (1)

Country Link
JP (1) JPH04313276A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2013175636A1 (en) * 2012-05-25 2016-01-12 株式会社日立製作所 Mechanical quantity measuring device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2013175636A1 (en) * 2012-05-25 2016-01-12 株式会社日立製作所 Mechanical quantity measuring device

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