JPH04312122A - Program producing device - Google Patents

Abstract

PURPOSE:To attain the output of an object having a high executing cycle without changing the side of an instruction code when the optimization enable information, e.g. the branching instructions which have the different branchable ranges and different instructions executing cycles and have the same number of bytes of the instruction codes are present thereon. CONSTITUTION:An optimization information input 111 inputs the optimization enable information 301 through a code correction part 108. An optimization deciding part 112 desides where an instruction code is included or not in the branching range of the branching instructions of high executing cycles based on an absolute branching side address that undergone the connection/ arrangement processing with the information 301 and the symbol value inputted from a symbol solution part 107 and the branching side address. If so, an instruction conversion part 113 outputs the instruction code after converting it into another instruction code of the branching instruction of a high executing cycle.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION The present invention is utilized in a program creation device, and in particular relates to a linker which is a language processing program, and in which relocatable objects are created in units of segments, which are allocation units of the linker, specified at the time of assembling or compiling. The present invention relates to a program creation device that creates an executable object program by modifying a part of the object program with reference to the address where the object is located after determining the location.

0002

2. Description of the Related Art There is a processing method for optimizing branch instructions in conventional language processing programs aimed at reducing code size.

An example (1) is shown below in which there are two types of branch instructions: a relative branch instruction that has a short instruction code but a limited relative distance, and an absolute branch instruction that has a long instruction code but can branch to the entire address space.

[0004] A relocatable assembler or compiler performs optimization within a range that can be determined by analyzing one module. In other words, if the branch destination address and the branch source address are in the same segment within one module, or if both the branch destination address and the branch source address are already absolute at the time of assembly or compilation, the result of calculating the relative distance is that it is allowed. If the distance falls within the relative distance, a relative branch instruction code is output; if not, an absolute branch instruction code is output. This allows the language processing program user to create a program without being aware of the relative distance between the branch destination address and the branch source address, making it possible to obtain a shorter code size.

[0005] The following example (
2).

For example, suppose the following branch instruction exists. (a) Relative branch instruction with a short relative distance range (relative distance within -128 bytes to +127 bytes, instruction code size: 2 bytes) (b) Relative branch instruction with a longer relative distance range than (a) (relative distance -32768 bytes ~ +32767
(within byte, instruction code size: 3 bytes) (c) Absolute branch instruction into a bank, which is a unit of division into which the address space is divided (1 hunk 64
K bytes, instruction code size: 3 bytes) (d) Absolute branch instruction that can branch to all address spaces (instruction code size: 4 bytes)

At this time, in the relocatable assembler, as in the optimization processing method described above, first, if the branch destination address and the branch source address are in the same segment within one module, or if both the branch destination address and the branch source address are If it is already absolute at the time of compilation, if the relative distance is within the relative distance of (a) as a result of calculating the relative distance, then the branch instruction of (a) is used, and if it is within the relative distance of (b), the branch instruction of (b) is used. , otherwise outputs the code of the absolute branch instruction (d).

FIG. 6 shows an example of optimization using this method. Branch instruction 603 has a relative distance of 100 bytes, so instruction (a) and branch instruction 602 have a relative distance of 300 bytes and exceed the range of -128 bytes to +127 bytes, but -32768 bytes to +3
Since it falls within the range of 2767 bytes, the instruction (b)
The branch instruction 601 has a relative distance of 38000 bytes (b
), so an absolute branch instruction that can branch to the entire address space in (d) is generated. branch instruction 60
In 4, the branch source and destination are relocatable and are in separate modules, so the instruction in (d) is used in 605. In 605, the segment, which is the placement unit, is different, so where the linker will place it is undecided, so 604 Similarly, the instruction (d) is generated.

[0009]

[Problems to be Solved by the Invention] Recently, the functions of software have become more sophisticated and the scale of programs has expanded, and there is a trend toward expanding the conventional address space. Therefore, as a language processing program, the optimization method of conventional example (2) described above is effective. However, example (2
) optimization method causes the following problems.

[0010] The optimization method in example (2) generates three branch instructions (a), (b), and (d), and the intra-bank branch instruction (c) cannot be generated. . (a) is a short distance branch and (d)
is a long branch exceeding 64K bytes, so (b
) seems to have a high rate of generating medium-distance relative branch instructions.

By the way, the instruction (b) and the instruction (c) are compared from the following three points of view.

First, the instruction code size is (b) (
c) are also equal.

Second, in terms of execution cycles, the intra-bank absolute branch instruction (c) is faster. Because (c)
In (b), the bank has already been selected, so all you need to do is set the 16-bit branch destination address specified in the program counter, but in (b), the 16-bit relative distance in the object is added to the current address. This is because the branch destination address must be calculated and then set in the program counter.

Thirdly, the branchable range is -32768 bytes to +32767 bytes from the current address in (b), whereas in (c) it is within 64 kilobytes of one bank, but it is written in a relocatable manner. in case of,
Because segments are divided into functional units, and it is rare for a single functional unit to span 64 kilobytes, most of the relative branch instructions in (b) are used as intra-bank absolute branches in (c). It seems possible to replace it with a command.

As described above, when comparing the instructions in (b) and (c), most of the instructions are covered by the branch range in (c), and the instruction code size is the same, but the effective cycle is ( b) is slower. In other words, example (2
), as a result of the assembler's optimization, the problem arises that it generates many instructions with a slow execution cycle.

[0016] An object of the present invention is to solve the above problem, so that when a branch instruction as shown in the above example (2) exists, without changing the instruction code size,
An object of the present invention is to provide a program creation device that can generate objects with faster execution cycles.

[0017]

[Means for Solving the Problems] The present invention provides an input section for inputting relocatable objects, a coupling section for coupling modules, an arrangement section for arranging the coupled modules in an address space, and a reference relationship between symbols. It is equipped with a linker processing unit that includes a symbol resolution unit that corrects addresses determined during resolution and placement, a code correction unit that corrects relocatable instruction codes to absolute values, and an output unit that outputs the corrected object. In the program creation device, the linker processing unit inputs information that a branch instruction code having the same instruction code size but a slow execution cycle is issued, address information where the code is issued, and branch destination address information. The optimization information input unit performs a combination and placement process using the input information and the symbol value whose value has already been determined by the symbol resolution unit, and determines whether the instruction code falls within the branch range with the faster execution cycle. and an instruction conversion unit that converts the instruction code into the instruction code and outputs the instruction code to the output unit when it is determined that the instruction falls within the branch range with the faster execution cycle. shall be.

[0018]

[Operation] The optimization information input section inputs information that a branch instruction code having the same instruction code size but a slow execution cycle is issued, address information where the code is issued, and branch destination address information. The optimization judgment unit performs a combination and placement process using this input information and the symbol value whose value has already been determined by the symbol resolution unit, and judges whether the code in question falls within the branch range with the faster execution cycle. do. Then, the instruction converting section converts the instruction code into the instruction code when it is determined that the instruction falls within the branch range with the faster execution cycle, and outputs the converted instruction code to the output section.

Therefore, it is possible to output an object with a fast execution cycle without changing the instruction code size.

[0020]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. This example describes relocatable objects 10 output by a relocatable assembler or compiler.
1, an input unit 104 that inputs 1, a combination unit 105 that combines modules, a placement unit 106 that places the combined modules in the address space, and resolves symbol reference relationships and corrects addresses determined at the time of placement. and a code correction unit 10 that corrects relocatable instruction codes to absolute values.
8 and a linker processing unit 102 including an output unit 110 that outputs the corrected object 103,

A feature of the present invention is that the linker processing unit 102 generates information that a branch instruction code having the same instruction code size but a slow execution cycle is issued, address information where the code is issued, and the branch destination. an optimization information input unit 111 that inputs address information; and an optimization information input unit 111 that inputs address information; and the input information and symbol resolution unit 107;
an optimization determination unit 112 that determines whether the instruction code can enter the branch range with a faster execution cycle based on the symbol value whose value has already been determined; and an instruction conversion section 113 that converts the instruction code into the instruction code and outputs it to the output section 110 when it is determined that the instruction code is the instruction code. In addition,
The optimization information input section 111 , the optimization judgment section 112 , and the instruction conversion section 113 constitute an optimization processing section 109 .

Next, the operation of this embodiment will be explained. First, the input unit 104 inputs information necessary for combining multiple files from the relocatable object 101, and
A combining unit 105 performs a combining process. Next, the arrangement section 106
Then, the combined group is placed in the address space and the address is determined. The symbol resolution unit 107 resolves the symbol definition reference relationship, and also corrects and determines the value of the symbol whose value is undefined based on the address determined by the placement unit 106. In the code correction section 108, the input section 104
After inputting the code correction information 201 from the object code and correcting the part of the code that was not determined because the symbol value was undefined in the object code, the output unit 110
The object 103 is output via.

As shown in FIG. 2, the code correction information 201 includes a correction address 202, a correction type 203, a correction size 204, a reference symbol 205, and a constant value 2.
Contains 06. Optimization possibility information 301 indicating the possibility of optimization exists as one of the code correction information 201 and is determined from the correction type 203 .

When the code correction information 201 is the optimization possibility information 301 , the code correction section 108 inputs the optimization possibility information 301 to the optimization processing section 109 and transfers control thereto.

Next, the optimization processing section 109 to which control has been transferred
The detailed processing will be explained by taking as an example the case where the instruction group described in Example (2) of [Prior Art] exists as a branch instruction. Of these, (b) and (c) are relevant in the optimization process in the linker. (b)
The difference between (c) and (c) is that although the instruction code size is exactly the same, the branch range is different and the execution cycle is faster in (c) than in (b). (b) Relative branch instruction with a long range of relative distance (relative distance -32768 bytes to +32767 bytes or less Instruction code size: 3 bytes Execution cycle: slow) (c) One division unit in which the address space is divided into certain units Absolute branch instruction into bank (1 bank 64
KB instruction code size: 3 bytes Execution cycle: fast)

FIG. 3 shows the structure of the optimization possibility information 301 inputted by the optimization information input section 111. The field corresponding to the correction type 203 in FIG. 2 is set to the optimizable type 303. Further, the correction size 304 is set to "3" because the instruction code size of the branch instruction is 3 bytes. Note that 302 is a correction address, 305 is a reference symbol, and 306 is a constant value.

The details of the optimization process will be explained below according to the flowchart shown in FIG. First, the optimization information input section 111
, the correction address 302 , the reference symbol 305 , and the constant value 306 from the optimization possibility information 301
(Step 401). Optimization judgment unit 1
12 extracts the final fixed address of the read reference symbol 305 from the symbol that has already been corrected by the symbol resolution unit (step 402). Next, a constant value 306 is added to the retrieved symbol value to determine the branch destination address (step 403). Then, it is checked whether the bank to which the branch destination address belongs and the bank to which the correction address 302 belongs are equal (step 404).
. Whether the banks are equal is checked by comparing the masked values of the lower 16 bits of the address. If they are equal, the instruction conversion unit 113 generates an object for intra-bank branch instruction (c), and outputs it from the output unit 110 (
Step 405), if they are not equal, the object of the original relative branch instruction is output as is from the output unit 110.
(Step 406).

FIG. 5 shows which branch instructions are converted as a result of the linker performing optimization processing along with link processing. In the assembler optimization of FIG. 6, the branch instruction 503 is changed from the relative branch instruction (b) to the intra-bank branch instruction (c).

Through the above processing, the optimization possibility information 30
By inputting 1, it is possible to convert the instruction code into a branch instruction with a faster execution cycle and output the object without changing the instruction code size.

[0031]

[Effects of the Invention] As explained above, the present invention enables a linker to input optimization possibility information, and to obtain a fast execution cycle from the absolute branch source address and branch destination address after performing combination and placement processing. By determining whether the branch instruction is within the branch range and outputting the instruction code if it is within the range, an object with a fast execution cycle is output without changing the instruction code size, improving speed performance. This has the effect of providing better objects.

In particular, according to the present invention, a branch instruction with a slow execution cycle is When a large number of instructions are output, optimization with the linker can improve the performance of the object by converting them to branch instructions with faster execution cycles. It is possible to output an object that takes full advantage of the characteristics of the hardware instruction set, which has multiple types of branch instructions, which is very effective.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of the code correction information.

FIG. 3 is a configuration diagram of the optimization possibility information.

FIG. 4 is a flowchart showing the processing procedure of the optimization processing section.

FIG. 5 is an explanatory diagram showing an example of optimization of branch instructions after linker processing.

FIG. 6 is an explanatory diagram showing an example of optimization of branch instructions after assembler processing according to a conventional example.

[Explanation of symbols]

101 Relocatable object 102
Linker processing section 103 Object 104 Input section 105 Combining section 106 Placement section 107 Symbol resolution section 108 Code correction section 109 Optimization processing section 110 Output section 111 Optimization information input section 112 Optimization judgment section 113 Instruction conversion section 201 Code correction information 202 , 302 Correction address 203
Correction type 204, 304 Correction size 205, 30
5 Reference symbols 206, 306
Constant value 301 Optimizability information 303 Optimizable type 401 to 406 Steps

Claims (1)

[Claims] Claim 1: An input section for inputting relocatable objects, a coupling section for coupling modules, a placement section for locating the coupled modules in an address space, and an address determined at the time of resolution and placement of symbol reference relationships. A program creation device comprising a linker processing section including a symbol resolution section that corrects a relocatable instruction code to an absolute value, a code correction section that corrects a relocatable instruction code to an absolute value, and an output section that outputs a corrected object. The processing unit includes an optimization information input unit that inputs information that a branch instruction code having the same instruction code size but a slow execution cycle is issued, address information from which the code is issued, and branch destination address information; an optimization determination unit that performs a combination and placement process using the information obtained by the above-described information and the symbol value whose value has already been determined by the symbol resolution unit, and determines whether the instruction code falls within a branch range with a faster execution cycle; A program creation device comprising: an instruction conversion unit that converts the instruction code into the instruction code and outputs the instruction code to the output unit when it is determined that the cycle falls within a faster branch range.