JPH04309015A - Digital phase locked loop circuit - Google Patents

Abstract

PURPOSE:To automatically recover the circuit by detecting automatically the pseudo synchronization state of the digital phase locked loop circuit. CONSTITUTION:The circuit is provided with a voltage controlled oscillator means 100 generating an output signal of a frequency depending on an inputted control voltage, a phase comparator means 200 comparing the phase of an output signal and that of an input signal of the voltage controlled oscillator means and generating a control signal inputted to the voltage controlled oscillator means, an input signal monitor means 300 monitoring whether or not the phase of the input signal is in existence for a prescribed period within a limit area of a phase synchronization confirmation range decided based on the output signal and an input signal interrupt means 400 interrupting the input of the input signal to the phase comparator means when the phase of the input signal is in existence for a prescribed period within the limit area.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase synchronization circuit that generates an output signal that is phase synchronized with an input signal.

0002

6 is a diagram showing an example of a conventional digital phase synchronization circuit, FIG. 7 is a diagram showing an example of the signal waveform (center frequency) in FIG. 6, and FIG. 8 is a diagram showing the signal waveform in FIG. 6. FIG. 9 is a diagram showing an example (lower limit frequency) of
7 is a diagram showing an example of a signal waveform (upper limit frequency) in FIG. 6. FIG.

In FIG. 6, the digital phase synchronization circuit includes a differential circuit (DIF) 1 and a flip-flop (FF) 2.
, low pass filters (LPF) 3 and 4, differential amplifier (A
) 5, voltage controlled oscillator (VCO) 6, and frequency divider (F
DV) consists of 7.

In FIG. 6, for example, when an input signal i whose frequency changes around 8 kilohertz is input to a digital phase synchronization circuit, a differentiation circuit (DIF) 1 differentiates the input signal i, and a differential signal d is transferred to a flip-flop circuit. (FF)
Input to reset terminal R of No.2.

On the other hand, the voltage controlled oscillator (VCO) 6 operates when the voltage of the control signal a input from the differential amplifier (A) 5 is "0".
” volts to “7” volts changes the frequency of the output signal v, but when the control signal a is set to “3.5” volts, the output signal v has a center frequency of 16 .384 MHz.

The frequency divider (FDV) 7 is a voltage controlled oscillator (
The output signal v output from VCO) 6 is divided by 1/2048.
The signal is frequency-divided into a frequency-divided signal o having a frequency of 8 kilohertz and inputted to a clock terminal CK of a flip-flop (FF) 2.

As a result, the flip-flop (FF) 2 is
It is reset every time the differential signal d is input to the reset terminal R, and the output terminals Q and QN are reset in synchronization with the divided signal o.
Invert the output signals q and qN output from the inverter.

The low-pass filter (LPF) 3 smoothes the output signal q output from the flip-flop (FF) 2 and inputs it as an output signal p to the inverting input terminal (-) of the differential amplifier (A) 5. , and the low-pass filter (LPF) 4 receives the output signal qN output from the flip-flop (FF) 2.
is smoothed, and the differential amplifier (A) 5 is used as the output signal pN.
Input to the non-inverting input terminal (+) of

The differential amplifier (A) 5 has a non-inverting input terminal (
The output signal pN input to the +) and the inverting input terminal (-
) is compared in magnitude with the output signal p input to
The control signal a to be output after the response time has elapsed from the time when pN Input to controlled oscillator (VCO) 6.

[0010] Note that a low-pass filter (L
The delay in inversion of the output signals p and pN of PF) 3 and 4 is expressed as 3/8π when expressed in terms of the phase of input signal i, and the response time of differential amplifier (A) 5 is expressed in terms of the phase of input signal i. It is assumed to be 3π/4.

Here, the frequency of input signal i is the center frequency (
8 kilohertz), each signal waveform of the digital phase-locked circuit is as shown in FIG. 0'' volts are equal, and the frequency-divided signal o is phase-locked to the input signal i, with the frequency of the output signal v averaging 16.384 MHz.

Next, when the frequency of the input signal i decreases below the center frequency and becomes near the lower limit of the range (so-called lock range) in which the digital phase-locked circuit can establish phase synchronization, the frequency of the digital phase-locked circuit decreases. As shown in FIG. 8, each signal waveform has a phase difference of 3π/
4, the period in which the control signal a is set to ``7'' volts is shorter than the period in which it is set to ``0'' volts, and the frequency of the output signal v drops below 16.384 MHz on average. The frequency signal o is phase-locked to the input signal i.

Next, when the frequency of the input signal i rises above the center frequency and becomes near the upper limit of the lock range of the digital phase-locked circuit, each signal waveform of the digital phase-locked circuit becomes as shown in FIG. Input signal i and divided signal o
The phase difference between the control signal and
When the frequency is increased above 4 MHz, the frequency-divided signal o is phase-locked to the input signal i.

Here, when comparing the phase of the frequency division signal o in FIGS. 8 and 9 with the phase of the frequency division signal o in FIG. 7, the phase of the frequency division signal o in FIG. 8 is advanced by π/4, Further, the reason why the phase of the frequency-divided signal o in FIG. 9 is delayed by π/4 is due to the fact that the response time of the differential amplifier (A) 5 is 3π/4 as described above.

In such a digital phase locked circuit,
Once the frequency of input signal i is near the lower or upper limit of the lock range and the phase synchronization of divided signal o is established, even if the frequency of input signal i returns to the center frequency (8 kHz), the frequency of divided signal o will remain unchanged. A phenomenon has been observed in which the frequency does not follow the input signal i and continues to maintain the established phase synchronization state (hereinafter referred to as pseudo synchronization state).

It has been experimentally confirmed that such a pseudo-synchronous state is likely to occur when the frequency of the input signal i is suddenly changed. When the digital phase-locked circuit falls into a pseudo-synchronized state, a maintenance person detects the digital phase-synchronized circuit that has entered the pseudo-synchronized state, temporarily cuts off the input signal i, and causes the voltage-controlled oscillator (VCO) 6 to run freely. After oscillating at the same frequency, the only option was to input the input signal i again to reestablish phase synchronization.

[0017]

[Problems to be Solved by the Invention] As is clear from the above explanation, in conventional digital phase synchronization circuits,
Once the frequency of input signal i reaches the lower or upper limit of the lock range and phase synchronization is established, from then on input signal i
Even if returns to the center frequency, the frequency of the output signal v cannot be followed, and the digital phase-locked circuit enters a pseudo-synchronized state.The maintenance person detects the digital phase-synchronized circuit in the pseudo-synchronized state and temporarily adjusts the input signal i. There was a problem in that the reliability of the digital phase synchronized circuit was reduced because it could not be recovered unless it was shut down.

SUMMARY OF THE INVENTION An object of the present invention is to realize a digital phase synchronization circuit that automatically detects the occurrence of a pseudo synchronization state and automatically recovers the state.

[0019]

Means for Solving the Problems FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, the digital phase synchronization circuit is comprised of voltage controlled oscillation means 100, phase comparison means 200, input signal monitoring means 300, and input signal cutoff means 400.

[0020]

Operation: The voltage controlled oscillation means 100 generates an output signal having a frequency determined by the input control voltage.

The phase comparison means 200 compares the phase of the output signal generated by the voltage controlled oscillation means 100 and the input signal, and generates a control signal to be input to the voltage controlled oscillation means 100.

The input signal monitoring means 300 detects that the phase of the input signal is within the limit range of the phase synchronization establishment range defined with reference to the output signal generated by the voltage controlled oscillation means 100.
The presence or absence is monitored for a predetermined period of time.

The input signal blocking means 400 is configured so that the input signal monitoring means 300 detects that the phase of the input signal is within a predetermined period.
When it is detected that the signal exists within the limit region, the input of the input signal to the phase comparison means 200 is cut off.

It is considered that the aforementioned limit range monitored by the input signal monitoring means 300 is set based on the phase of the output signal generated by the voltage controlled oscillation means 100 and the response time of the phase comparison means 200.

[0025] Therefore, the digital phase synchronization circuit automatically detects that it has entered a pseudo-synchronized state, automatically cuts off the input signal temporarily, and resynchronizes, so that the pseudo-synchronized state can be automatically recovered. , the convenience and reliability of the digital phase-locked circuit are improved.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a digital phase synchronization circuit according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of the window monitoring circuit and frequency divider in FIG. 2, and FIG.
5 is a diagram showing an example of a window signal generation process in FIG. 5, and FIG. 5 is a diagram showing an example of a signal waveform in FIG. 2. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, a voltage controlled oscillator (VCO) 6 and a frequency divider (FDV) 7 are provided as the voltage controlled oscillation means 100 in FIG. 1, and a differential circuit (DIF) is provided as the phase comparison means 200 in FIG. 1, a flip-flop (FF) 2, low-pass filters (LPF) 3 and 4, and a differential amplifier (A) 5 are provided, and a window monitoring circuit (WDS) 8 is provided as the input signal monitoring means 300 in FIG. A gate 9 is also provided as input signal blocking means 400 in FIG.

In FIGS. 2 to 5, a differential circuit (DIF
) 1, flip-flop (FF) 2, low-pass filter (L
PF) 3 and 4, differential amplifier (A) 5, voltage controlled oscillator (VCO) 6, and frequency divider (FDV) 7 operate in the same process as described above, and generate a frequency-divided signal phase-synchronized with input signal i. o is output.

Note that also in FIGS. 2 to 5, the input signal i
The center frequencies of output signal v are 8 kilohertz and 16.384 megahertz, respectively, and the response time of differential amplifier (A) 5 is 3π/4 when expressed in terms of the phase of input signal i.

The frequency divider (FDV) 7 is composed of eleven stages of flip-flops (FF) 70 to 710 as shown in FIG. 16.384 MHz) is sequentially divided into two, and from flip-flops (FF) 77, 78, and 79, the frequency is divided by 256, 512, and 10, respectively.
The frequency-divided signals q7, q8, and q9, which are frequency-divided by 24, are outputted to the next-stage flip-flops (FF) 78,
79 and 710, and also to the window monitoring circuit (WDS) 8.

In the window monitoring circuit (WDS) 8, the frequency-divided signal q7 is input to the clock terminal CK of a flip-flop (FF) 84 via an inverter 81.
Furthermore, the frequency divided signal q8 is passed through the inverter 82 to the gate 8.
3 and directly input to the gate 83.
9 is input to the data terminal D of the flip-flop (FF) 84.

As a result, the flip-flop (FF) 84
A window signal w and a non-window signal wN are output from the output terminals Q and QN of
are output and input to gates 85 and 86, respectively.

Here, the window signal w indicates a region where the differential signal d is input when synchronized with the input signal i having a frequency near the lower limit or upper limit of the lock range, and the non-window signal wN is the window signal w Indicates an area other than the area indicated by.

Therefore, the gate 85 is set to a conductive state in the region indicated by the window signal w, and the gate 86 is set to a conductive state in a region other than the region indicated by the window signal w. On the other hand, the differential signal d output from the differential circuit (DIF) 1
is input to the reset terminal R of the flip-flop (FF) 2 via the gate 9, and is also input to the gates 85 and 8.
6 to a counter (CNT) 87.

Therefore, the digital phase-locked circuit enters a so-called pseudo-synchronized state, the frequency of the divided signal o remains near the lower limit or upper limit of the lock range, and the differential signal d remains within the region indicated by the window signal w. If it occurs continuously, the counter (CNT) 87 is incremented via the gate 85 which is in a conductive state.

Note that FIG. 5 shows a case where phase synchronization is achieved near the lower limit of the lock range, and when phase synchronization is achieved near the upper limit of the lock range, the differential signal d is not generated in FIG. A differential signal d will be generated in this region.

The counter (CNT) 87 counts the differential signals d continuously generated in the area indicated by the window signal w, and when a predetermined count value is reached, outputs a cutoff signal c from the overflow terminal O. Gate 9 is set to a blocked state.

When the gate 9 is set to the cutoff state, the differential signal d is no longer input to the reset terminal of the flip-flop (FF) 2, so the flip-flop (FF) 2 is synchronized only with the divided signal o. In order to invert the output signals q and qN and set the control signal a to "7" volts and "0" volts at equal intervals in synchronization with the output signal p, the differential amplifier (A) 5 also uses a voltage controlled oscillator (VCO). ) 6 is free running and outputs an output signal v having a center frequency of 16.384 MHz.

As a result, the digital phase synchronization circuit eliminates the pseudo synchronization state, and the differential signal d becomes the non-window signal w.
This occurs in the region indicated by N, and the counter (CNT) 87 is generated through the conductive gate 86.
is input to the reset terminal R of the counter (CNT) 87.
to be reset.

As a result, the counter (CNT) 87 stops inputting the cutoff signal c that had been input to the gate 9, so the gate 9 is set to conductive state again, and the differential signal d is reset to the flip-flop (FF) 2. Input to terminal R.

As described above, the digital phase synchronization circuit again starts the operation of phase-synchronizing the frequency-divided signal o with the input signal i. As is clear from the above description, according to this embodiment, when the digital phase locked circuit enters a pseudo locked state and the differential signal d is input a predetermined number of times within the area indicated by the window signal w, the gate 9 is activated. After cutting off the input signal i and letting the voltage controlled oscillator (VCO) 6 run freely to set the frequency of the output signal v to the center frequency of 16.384 MHz, in order to synchronize the phase of the divided signal o with the input signal i again. , the pseudo synchronization state of the digital phase synchronization circuit is automatically canceled and the phase synchronization operation for the input signal i is started again.

Note that FIGS. 2 to 5 are only one embodiment of the present invention, and for example, the center frequencies of the input signal i and the output signal v, and the response time of the differential amplifier (A) 5 are illustrated. Although the present invention is not limited to this and many other modifications may be considered, the effects of the present invention remain the same in any case.

[0043]

[Effects of the Invention] As described above, according to the present invention, the digital phase synchronization circuit automatically detects that it is in a pseudo-synchronization state, automatically cuts off the input signal temporarily, and re-establishes synchronization. The state can be automatically recovered, improving the convenience and reliability of the digital phase-locked circuit.

[Brief explanation of drawings]

[Figure 1] Diagram showing the principle of the present invention

[Fig. 2] Digital phase synchronization circuit according to an embodiment of the present invention

[Figure 3] Diagram showing an example of the window monitoring circuit and frequency divider in Figure 2

[Figure 4] A diagram showing an example of the window signal generation process in Figure 3.

[Figure 5] Diagram showing an example of the signal waveform in Figure 2

[Figure 6] Diagram showing an example of a conventional digital phase synchronization circuit

[Figure 7] Diagram showing an example of the signal waveform (center frequency) in Figure 6

[Figure 8] Diagram showing an example of the signal waveform (lower limit frequency) in Figure 6

[Figure 9] Diagram showing an example of the signal waveform (upper limit frequency) in Figure 6

[Explanation of symbols]

1 Differential circuit (DIF) 2, 70,..., 79, 710, 84 Flip-flop (FF) 3, 4 Low-pass filter (LPF) 5 Differential amplifier (A) 6 Voltage-controlled oscillator (VCO) 7 Frequency divider ( FDV) 8 Window monitoring circuit (WDS) 9, 83, 85, 86 Gates 81, 82 Inverter 87 Counter (CNT) 100 Voltage controlled oscillation means 200 Phase comparison means 300 Input signal monitoring means 400 Input signal cutting means

Claims (2)

[Claims] 1. Voltage controlled oscillation means (10) for generating an output signal having a frequency determined by an input control voltage.
0), the output signal generated by the voltage controlled oscillation means (100), and the input signal; a comparison means (200); the phase of the input signal exists within a limit region of a phase synchronization establishment range determined based on the output signal generated by the voltage controlled oscillation means (100) for a predetermined period; input signal monitoring means (300) for monitoring whether or not the input signal is present in the limit region for the predetermined period; In this case, the digital phase synchronization circuit is further provided with an input signal cutoff means (400) for cutting off input of the input signal to the phase comparison means (200). 2. The limit region monitored by the input signal monitoring means (300) is defined by the voltage controlled oscillation means (100).
) and the phase of the output signal generated by the phase comparing means (2).
2. The digital phase synchronization circuit according to claim 1, wherein the setting is made based on the response time of 00).