JPH04306880A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a channel region formed through a diffusion difference in a lateral direction between a source region and a base region to be prevented from fluctuating in concentration peak. CONSTITUTION:An ion implantation process is carried out through a lower gate electrode 16 for forming a base using an upper gate electrode 17 as a mask, and ions are implanted using a lower gate electrode 16 larger than the upper gate electrode in gate length as a mask to form a source. The concentration peak of a channel region 14 can be determined by the amount of ion implanted for the formation of a base and is hardly affected by thermal treatment, so that a transistor can be stabilized in threshold control.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor device using a double-diffused insulated gate field effect transistor, and more specifically, a channel region is formed by the difference in lateral diffusion length between a source region and a base region. It is related to transistors.

0002

2. Description of the Related Art FIG. 8 shows a double diffused insulated gate field effect transistor constructed using a conventional technique. In FIG. 8, the transistor is connected to the first conductivity type semiconductor substrate 2.
1, a gate electrode 26 disposed on the gate insulating film 25, a second conductive type impurity diffusion layer (base) 22 having a channel region 22a, and a first conductive layer constituting a source region 23 and a drain region 24, respectively. type impurity diffusion layer. 28 is a LOCOS oxide film, and 29 and 30 are a field insulating film and an electrode, respectively.

0003

[Problems to be Solved by the Invention] In order to form the base region 22 and the source region 23 using the conventional technique, after ion-implanting impurities of the second conductivity type using the source side gate electrode end ES as a diffusion mask end, Impurity ions of the first conductivity type are implanted from the same position. At this time, the channel region of the transistor remains due to the difference in lateral diffusion length between the two layers.
This becomes a conductivity type impurity diffusion layer region, and its threshold value is determined by the peak concentration of the second conductivity type impurity diffusion layer 22. However, as shown in FIG. 9, both of the two impurity diffusion layers have a concentration gradient, and the peak concentration Cpeak of the channel region 22a changes due to variations in heat treatment during diffusion, making it difficult to control the threshold value. ing. Symbol EP in Figures 8 and 9
indicates the channel side base end. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can prevent fluctuations in the peak concentration of a channel region.

0004

[Means for Solving the Problems] The present invention provides a gate electrode portion disposed on a first conductivity type semiconductor substrate with an insulating film interposed therebetween, and a channel formed by ion implantation using the gate electrode portion as a mask. A double diffusion type insulated gate field effect comprising a second conductivity type impurity diffusion layer having a region and a first conductivity type impurity diffusion layer formed by ion implantation in a self-aligned manner using the gate electrode part as a mask. The transistor is a semiconductor device having a double gate electrode structure in which a gate electrode portion is composed of a lower layer gate electrode and an upper layer gate electrode disposed on the lower layer gate electrode and having a narrower width than the lower layer gate electrode. In addition, the present invention provides a method (
i) After sequentially laminating a lower gate electrode layer, an upper gate electrode layer made of a different material, and a photoresist layer on the first conductivity type semiconductor substrate via an insulating film, and (ii) forming a photoresist pattern. Using this as a mask, the upper gate electrode layer is etched to form an upper layer gate electrode having a gate length shorter than the horizontal width of the pattern, and (iii) using the photoresist pattern as a mask, the lower gate electrode layer is etched. After etching to form a lower layer gate electrode having a gate length longer than the gate length of the upper layer gate electrode and removing the photoresist pattern, (iv) next, a second layer having a channel region is etched.
A window is opened only in the conductive type impurity diffusion layer formation region, and ions are implanted at a predetermined ion implantation energy using the upper gate electrode as a mask. A method for manufacturing a semiconductor device is provided, which comprises implanting ions through the lower gate electrode using the lower gate electrode as a mask at an ion implantation energy of . That is, the present invention implants second conductivity type impurity ions through the lower gate electrode with acceleration energy reaching the first conductivity type semiconductor substrate, and implants the second conductivity type impurity ions under the source side gate electrode of the double diffused insulated gate field effect transistor. , forming a second conductivity type impurity diffusion layer with a constant surface concentration;
This is intended to eliminate variations in heat treatment due to fluctuations in the peak concentration of the channel region, thereby stabilizing the threshold value of the transistor.

[0005]

[Operation] By using the above means, a second conductivity type impurity diffusion layer is formed under the source side gate electrode of the double diffused insulated gate field effect transistor with the width of the retreat of the upper layer gate electrode. Since the first conductivity type impurity diffusion layer is formed, the peak concentration of the second conductivity type impurity in the channel region is determined by the ion implantation amount, and is not easily affected by heat treatment, making it possible to stabilize the threshold control of the transistor. .

[0006]

Embodiment FIGS. 3 to 7 show the main steps of an embodiment of the present invention. First, as shown in FIG. 3, after forming a gate oxide film 5 using a well-known technique, a lower layer gate electrode material (polycrystalline silicon, etc.) and an upper layer gate electrode material (tungsten silicide, etc.) are successively deposited using a CVD method. deposited,
A lower gate electrode layer 6 and an upper gate electrode layer 7 are formed. Next, a photoresist layer is laminated on the entire surface, and a photoresist pattern 11 with a width H is left in the gate electrode and wiring forming part F by a photolithography process, and the upper gate electrode layer 7 is etched, and the upper gate electrode layer 7 with a gate length L1 is etched. Electrodes 17 are formed (see FIG. 4). The etching at this time is assumed to have isotropic characteristics, and as shown in FIG.
Retreat further inward by a distance D. Further, the photoresist pattern 11 is left. Subsequently, the lower gate electrode layer 6 is etched using the photoresist pattern 11 to form the lower gate electrode 16 having a gate length L2 (see FIG. 5). The etching at this time is assumed to have anisotropic characteristics and reflects the shape of the photoresist as shown in FIG. That is, the position of the lower layer gate electrode end Q matches that of the photoresist end G. Next, pattern 1
After removing 1, a photoresist layer is laminated on the entire surface, and a window is opened only in the second conductivity type impurity diffusion layer forming region (base region) K by a photolithography process, leaving the photoresist pattern 20 in other regions. Upper layer gate electrode 17
The lower gate electrode 16 and the gate oxide film 5 are formed using the mask as a mask.
Ions 18 are implanted through (see FIG. 6). Next, pattern 20 is removed. Subsequently, after performing base diffusion to form the base 2, only the first conductivity type impurity diffusion layer formation region (source/drain region) is opened by a photolithography process to form the pattern 13 and the lower gate electrode 16.
After implanting ions 19 using the mask as a mask, source and drain diffusion is performed to form a source 3 and a drain 4 (see FIG. 7). At this time, the gate electrode side of the source/drain region is determined by the lower gate electrode end EG. Thereafter, a field insulating film 9 having a contact hole 9a and an electrode metal 10 are formed using a well-known technique to produce the device shown in FIG. As described above, in this embodiment, the gate electrode portion is divided into the lower layer gate electrode 16 and the upper layer gate electrode 1 having a narrower width.
7, implantation of ions 18 for forming the inner base of the source/base double diffusion layer is performed using the upper layer gate electrode 17 having the gate end E at a position retreated by a distance D from the lower layer gate electrode end EG as a mask. Furthermore, the ions 19 for forming the source are implanted in a self-aligned manner using the lower gate electrode 16 as a mask. The variation in the peak concentration of the channel region 14 is
This can be prevented because the surface concentration of the base can be kept constant. FIG. 2 shows the surface concentration characteristics of the base 2 and source 3, which are formed by diffusion after implantation of the ions 18 and 19, respectively. It can be seen that in the concentration curve A of base 2, the peak concentration (Cpeak) does not change as compared to the concentration curve B of base 22 shown in FIG. 9 and remains constant between EG and E. Therefore, the peak concentration of the second conductivity type impurity in the channel region 14 can be determined by the ion implantation amount. In addition, in FIGS. 2 and 9, curves X indicate the surface concentration curves of sources 3 and 23, respectively, and curves Y1 and Y1 indicated by dotted lines
Y2 is a curve that is a composite of curves A, X, B, and X, and curve Z is a surface concentration characteristic diagram of the semiconductor substrates 1 and 21.

[0007]

[Effects of the Invention] As described above, according to the present invention, a second conductivity type impurity diffusion layer is formed under the source side gate electrode of a double diffused type insulated gate field effect transistor with the width of the retreat of the upper layer gate electrode. Since the first conductivity type impurity diffusion layer is formed in this region, the peak concentration of the second conductivity type impurity in the channel region is determined by the ion implantation amount, is less affected by heat treatment, and stabilizes the threshold control of the transistor. make it possible to

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention.

FIG. 2 is a characteristic diagram showing the surface concentration of each impurity diffusion layer in the above example.

FIG. 3 is a configuration explanatory diagram showing the first step of the manufacturing process in the above embodiment.

FIG. 4 is a configuration explanatory diagram showing the second step of the manufacturing process in the above embodiment.

FIG. 5 is a configuration explanatory diagram showing the third step of the manufacturing process in the above embodiment.

FIG. 6 is a configuration explanatory diagram showing the fourth step of the manufacturing process in the above embodiment.

FIG. 7 is a configuration explanatory diagram showing the fifth step of the manufacturing process in the above embodiment.

FIG. 8 is a configuration explanatory diagram showing a conventional example.

FIG. 9 is a characteristic diagram showing the surface concentration of each impurity diffusion layer in a conventional example.

[Explanation of symbols]

1 First conductivity type semiconductor substrate 2 Base (second conductivity type impurity diffusion layer) 3
Source (first conductivity type impurity diffusion layer) 4 Drain (first conductivity type impurity diffusion layer) 5 Gate oxide film (insulating film) 6 Polycrystalline silicon layer (lower gate electrode layer) 7
Tungsten silicide layer (upper gate electrode layer)
11 Photoresist pattern 14 Channel region 16 Lower layer gate electrode 17 Upper layer gate electrode

Claims (2)

[Claims] 1. A gate electrode portion disposed on a first conductivity type semiconductor substrate through an insulating film, and a second conductivity type impurity diffusion having a channel region formed by ion implantation using the gate electrode portion as a mask. and a first conductivity type impurity diffusion layer formed by ion implantation in a self-aligned manner using the gate electrode portion as a mask, the gate electrode portion is a lower gate layer. 1. A semiconductor device having a double gate electrode structure comprising an electrode and an upper gate electrode disposed on the lower gate electrode and having a narrower width. 2. When forming a double diffused insulated gate field effect transistor, (i) a lower gate electrode layer and an upper gate electrode made of a different material from the first conductivity type semiconductor substrate are formed on the first conductivity type semiconductor substrate with an insulating film interposed therebetween; (ii) After forming a photoresist pattern, the upper gate electrode layer is etched using the photoresist pattern as a mask to form an upper gate electrode having a gate length shorter than the width of the pattern. (iii) etching the lower gate electrode layer using the photoresist pattern as a mask to form a lower gate electrode having a gate length longer than the gate length of the upper gate electrode;
After removing the above photoresist pattern, (iv) next, a window is opened only in the region where the second conductivity type impurity diffusion layer having the channel region is formed, and the lower layer gate electrode is passed through the upper layer gate electrode using a predetermined ion implantation energy as a mask. A method for manufacturing a semiconductor device, comprising: (v) opening a window only in a first conductivity type impurity diffusion layer formation region, and implanting ions at a predetermined ion implantation energy using a lower gate electrode as a mask.