JPH0430590A - Wiring board - Google Patents

Wiring board

Info

Publication number
JPH0430590A
JPH0430590A JP2137850A JP13785090A JPH0430590A JP H0430590 A JPH0430590 A JP H0430590A JP 2137850 A JP2137850 A JP 2137850A JP 13785090 A JP13785090 A JP 13785090A JP H0430590 A JPH0430590 A JP H0430590A
Authority
JP
Japan
Prior art keywords
lands
wiring
wiring board
conductive paste
recessions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2137850A
Other languages
Japanese (ja)
Inventor
Futoshi Hosoya
太 細谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2137850A priority Critical patent/JPH0430590A/en
Publication of JPH0430590A publication Critical patent/JPH0430590A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

PURPOSE:To make it possible to distribute a wire between a pair of lands without a short circuit through conductive paste by making recessions independently close to and along the sides of the lands opposite to each other. CONSTITUTION:A conductive pattern is formed on a substrate 1, a pair of lands 2 and a wiring 3 are made, and strip-shaped recessions 4 surrounded by the conductive pattern are made in the lands 2 along their sides opposite to each other. conductive paste 5 squeezed out to between the lands 2 by mounting a chip part 6 thereon stays in the recessions 4 and does not reach the wiring 3, the wiring 3 can be arranged between the lands 2 without short circuit, and high-density packaging is achieved. If for example a 2mm long chip capacitor is mounted, up to two 0.1mm wide wirings can be arranged at a distance of 0.1mm without short circuit even if the land patterns having the recessions in the peripheries are 0.6mm or less distant from each other.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は配線基板に関し、 載される配線基板に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a wiring board, The present invention relates to a wiring board to be mounted.

〔従来の技術〕[Conventional technology]

特にチップ部品が搭 従来の配線基板におけるチップ部品搭載ランドは、第4
図(a)、(b)に示すように、基板1に一対のランド
22が単に基板1の露出面をはさんで対向するように、
表面が凹凸なく平坦に形成されていた。
In particular, the chip component mounting land on a conventional wiring board on which chip components are mounted is the fourth
As shown in FIGS. (a) and (b), a pair of lands 22 are placed on the substrate 1 so that they simply face each other across the exposed surface of the substrate 1.
The surface was flat with no irregularities.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この従来の配線基板において、長さ2mm以下の小型の
チップ部品を使用部材の耐熱性や工程上の問題から、半
田リフロー等の半田付けでなく、導電性ペーストで配線
基板上に接続する場合には、印刷または吐出によって、
配線基板のランド上に導電性ペーストを十分な接続強度
が得られるように供給し、この上からチップ部品を搭載
する。このとき、チップ部品下になった導電性ペースト
が押し出され、導電性ペーストの供給位置やランドの寸
法9位置を最適化しても、第5図に示したように、ラン
ド22間の基板1面上に流れ出すものが発生し、極端な
場合には、ランド22間が導電性ペースト5で短絡する
という問題があった。
In this conventional wiring board, when connecting small chip parts with a length of 2 mm or less to the wiring board using conductive paste instead of soldering such as solder reflow due to the heat resistance of the parts used and problems in the process. By printing or dispensing,
Conductive paste is supplied onto the land of the wiring board to provide sufficient connection strength, and chip components are mounted on top of this. At this time, the conductive paste below the chip component is pushed out, and even if the supply position of the conductive paste and the land dimensions 9 positions are optimized, the surface of the board 1 between the lands 22 as shown in FIG. There is a problem that something flows upward, and in extreme cases, a short circuit occurs between the lands 22 due to the conductive paste 5.

まな、このような状態であるからランド22間へ配線を
通すということは不可能であった。
However, in such a state, it was impossible to run wiring between the lands 22.

本発明の目的は、導電性ペーストによるランド間の短絡
がなく、ランド間へ配線を通すことが可能な配線基板を
提供することにある。
An object of the present invention is to provide a wiring board that allows wiring to be passed between lands without causing short circuits between lands due to conductive paste.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、 1、チップ部品を搭載する一対のランドを有する配線基
板において、前記一対のランドのそれぞれの対向する辺
の近傍に該対向する辺に沿ってそれぞれ独立した凹部が
設けられている。
The present invention provides the following features: 1. In a wiring board having a pair of lands on which chip components are mounted, independent recesses are provided near opposing sides of each of the pair of lands and along the opposing sides.

2、前記一対のランドのそれぞれの対向する辺間に配線
が形成されている。
2. Wiring is formed between opposing sides of each of the pair of lands.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)、(b)は本発明の第1の実施例のランド
の平面図及びA−A’線断面図である。
FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of a land according to a first embodiment of the present invention.

第1の実施例は、第1図(a)、(b)に示すように、
基板1上に導体パターンが形成され、対のランド2.配
線3を構成し、相対向するそれぞれのランド2の対向す
る辺の内側のランド2内には、導体パターンで囲まれた
短冊形の凹部4が形成されている。
The first embodiment, as shown in FIGS. 1(a) and (b),
A conductive pattern is formed on the substrate 1, and a pair of lands 2. A rectangular recess 4 surrounded by a conductor pattern is formed in the land 2 on the inside of the opposing sides of each land 2 that constitutes the wiring 3 and faces each other.

第2図は第1図(a)、(b)の配線基板にチップ部品
を導電性ペーストを用いて実装した断面図である。
FIG. 2 is a sectional view of chip components mounted on the wiring board of FIGS. 1(a) and 1(b) using conductive paste.

第2図に示すように、チップ部品6を上から載せること
によってランド2間へ押し出された導電性ペースト5は
凹部4に滞留し配線3へ達して短絡することは無く、ラ
ンド2間に配線3を通すことが可能となり、高密度実装
化が実現できる。
As shown in FIG. 2, the conductive paste 5 pushed out between the lands 2 by placing the chip component 6 from above stays in the recess 4 and does not reach the wiring 3 and cause a short circuit. 3 can be passed through, and high-density packaging can be achieved.

例えば、第2図の構造を長さ2mmのチップコンデンサ
を搭載する配線基板に適用すると、凹部外周を含んだラ
ンド部パターンの間隔を0.6mm以下とした場合でも
、短絡することがなく、0.1mm幅の配線を0.1m
m間隔で最大2本通すことができる。
For example, if the structure shown in Fig. 2 is applied to a wiring board on which a chip capacitor with a length of 2 mm is mounted, there will be no short circuit and no .1mm wide wiring 0.1m
A maximum of 2 wires can be passed at m intervals.

第3図(a)、(b)は本発明の第2の実施例のランド
の平面図及びB−B’線断面図である。
FIGS. 3(a) and 3(b) are a plan view and a sectional view taken along the line BB' of a land according to a second embodiment of the present invention.

第2の実施例は、第3図(a)、(b)に示すように、
基板1上に導体パターンが形成され、相対向するそれぞ
れのランド2の対向する辺のすぐ内側の基板1表面が長
方形の溝状に座ぐり加工され、凹部14が形成される。
The second embodiment, as shown in FIGS. 3(a) and (b),
A conductor pattern is formed on the substrate 1, and the surface of the substrate 1 immediately inside the opposing sides of the respective opposing lands 2 is counterboiled into a rectangular groove shape to form a recess 14.

この2つの凹部14にはさまれた基板1上に配線3が引
かれている。
A wiring 3 is drawn on the substrate 1 sandwiched between the two recesses 14.

本実施例も第1の実施例と同様に凹部14でランドの内
側に押し出された導電ペースト5が滞留し短絡が防止さ
れる。
In this embodiment, as in the first embodiment, the conductive paste 5 pushed out to the inside of the land stays in the recess 14, thereby preventing short circuits.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は一対のランドのそれぞれの
対向する辺の近傍に対向する辺に沿ってそれぞれ独立し
た凹部を形成したので、チップ部品の搭載時にランド間
へ押し出された導電性ペーストがその凹部に滞留し、ラ
ンド間を流れて短絡を起こしたり、リーク電流を増加さ
せることが無く、また、ランド間に配線を通すことが可
能となり高密度実装化が実現できるという効果を有する
As explained above, in the present invention, independent recesses are formed near the opposite sides of a pair of lands along the opposite sides, so that the conductive paste pushed out between the lands when chip components are mounted is It does not stay in the recess and flow between the lands, causing a short circuit or increasing leakage current, and also allows wiring to be passed between the lands, thereby achieving high-density packaging.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、(b)は本発明の第1の実施例のランド
の平面図及びA−A’線断面図、第2図は第1図(a)
、(b)の配線基板にチップ部品を導電ペーストを用い
て実装した断面図、第3図(a)、(b)は本発明の第
2の実施例のランドの平面図及びB−B’線断面図、第
4図(a)(b)は従来の配線基板のランドの一例の平
面図及びc−c’線断面図、第5図は第4図(a)。 (b)の配線基板にチップ部品を導電ペーストを用いて
実装した断面図である。 1・・・基板、2.’12,22・・・ランド、3・・
・配線、4.14・・・凹部、5・・・導電ペースト、
6・・・チップ部品。
FIGS. 1(a) and (b) are a plan view and a cross-sectional view taken along the line A-A' of the land of the first embodiment of the present invention, and FIG. 2 is the same as FIG. 1(a).
, (b) is a cross-sectional view of a wiring board in which a chip component is mounted using a conductive paste, and FIGS. 4(a) and 4(b) are a plan view and a sectional view taken along line c-c' of an example of a land of a conventional wiring board, and FIG. 5 is FIG. 4(a). FIG. 3B is a cross-sectional view of the wiring board in which chip components are mounted using conductive paste. 1... Substrate, 2. '12, 22...land, 3...
・Wiring, 4.14... recess, 5... conductive paste,
6...Chip parts.

Claims (2)

【特許請求の範囲】[Claims] 1.チップ部品を搭載する一対のランドを有する配線基
板において、前記一対のランドのそれぞれの対向する辺
の近傍に該対向する辺に沿つてそれぞれ独立した凹部を
設けたことを特徴とする配線基板。
1. A wiring board having a pair of lands on which chip components are mounted, characterized in that independent recesses are provided near opposing sides of each of the pair of lands along the opposing sides.
2.前記一対のランドのそれぞれの対向する辺間に配線
を形成したことを特徴とする請求項1記載の配線基板。
2. 2. The wiring board according to claim 1, wherein wiring is formed between opposing sides of each of the pair of lands.
JP2137850A 1990-05-28 1990-05-28 Wiring board Pending JPH0430590A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2137850A JPH0430590A (en) 1990-05-28 1990-05-28 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2137850A JPH0430590A (en) 1990-05-28 1990-05-28 Wiring board

Publications (1)

Publication Number Publication Date
JPH0430590A true JPH0430590A (en) 1992-02-03

Family

ID=15208261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2137850A Pending JPH0430590A (en) 1990-05-28 1990-05-28 Wiring board

Country Status (1)

Country Link
JP (1) JPH0430590A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7667299B2 (en) 2004-01-27 2010-02-23 Panasonic Corporation Circuit board and method for mounting chip component
WO2011148615A1 (en) * 2010-05-26 2011-12-01 株式会社村田製作所 Substrate with built-in component

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6018574B2 (en) * 1981-08-13 1985-05-11 日産自動車株式会社 Luggage storage structure in the rear parcel shelf
JPS62174997A (en) * 1986-01-28 1987-07-31 富士通株式会社 Mounting structure of chip parts on printed board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6018574B2 (en) * 1981-08-13 1985-05-11 日産自動車株式会社 Luggage storage structure in the rear parcel shelf
JPS62174997A (en) * 1986-01-28 1987-07-31 富士通株式会社 Mounting structure of chip parts on printed board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7667299B2 (en) 2004-01-27 2010-02-23 Panasonic Corporation Circuit board and method for mounting chip component
WO2011148615A1 (en) * 2010-05-26 2011-12-01 株式会社村田製作所 Substrate with built-in component
JP5278608B2 (en) * 2010-05-26 2013-09-04 株式会社村田製作所 Component built-in board
KR101383137B1 (en) * 2010-05-26 2014-04-09 가부시키가이샤 무라타 세이사쿠쇼 Substrate with built-in component

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