JPH04304182A - Pll speed control method for dc motor - Google Patents

Abstract

PURPOSE:To provide PLL speed control method for DC motor which functions similarly both for a detected speed error and for the sum of the detected speed error and a detected position error, wherein the fact that the position error detected through a position error detector is deviated from a predetermined value is detected and a value corresponding to the detected position error is added through an adder in order to suppress fluctuation of the position error detected through the position error detector. CONSTITUTION:The PLL speed controller comprises a position error detector 1 comparing a target position value with an output from a pulse motor coupled with a DC motor 7 and a speed error detector 2 comparing a target speed with an output from the pulse motor. A detected position error and a detected speed error are added at an adder 5 and the sum is amplified and employed in the driving of the DC motor 7. In such PLL speed control system, a fact that a position error detected through the position error detector 1 is deviated from a predetermined value is detected. A value corresponding to the detected position error is further added through the adder 5 thus settling the position error detected through the position error detector 1 within a predetermined range.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL speed control method for a DC motor.

0002

[Prior Art] A conventional PLL control method for a DC motor is as follows:
Adding the position error detection output and the speed error detection output, driving the DC motor in accordance with the added output, feeding back the output of the pulse generator connected to the DC motor to the position error detector and the speed error detector, It controlled the speed of the DC motor.

0003

[Problem to be Solved by the Invention] However, in the conventional speed control method described above, it is not performed to detect and feed back the deviation of the position error detection output and speed error detection output from the reference value. .

However, the output of the position error detector fluctuates due to variations in the load torque and torque constant of the motor, variations in components constituting the control circuit, and the like. This fluctuation becomes larger as the position control loop gain becomes smaller. There is a problem in that when this fluctuation value exceeds a certain value, the PLL circuit becomes unable to lock. Furthermore, there are cases where the position control loop gain has to be reduced. The present invention has been conceived in view of the above, and detects that the position error detection output and the speed error detection output are far from a reference value.

[0005]

[Means for Solving the Problems] The present invention provides a position error detector that compares a position target value and the output of a pulse motor connected to a DC motor, and a speed error detector that compares a speed target value and the output of the pulse motor. PLL speed control of a DC motor, which includes a detector, adds the detected position error and the detected speed error output output from the position error detector in an adder, amplifies the added output, and drives the DC motor with the amplified output. In this method, it is detected that the detected position error output from the position error detector is far from a predetermined value, and a value corresponding to this detected position error is further added in an adder to be output from the position error detector. It is characterized by keeping the detected position error within a predetermined range.

[0006] Furthermore, when it is detected that the detected position error output from the position error detector is far from a predetermined value, the amplification reference value is varied in accordance with this detected position error, and the amplification reference value is output from the position error detector. The detected position error may be kept within a predetermined range. Also, instead of the detected position error output from the position error detector being far from the predetermined value,
It may also be detected that the detected speed error output from the speed error detector deviates from a predetermined value. Furthermore, it may be detected that the sum of the detected position error and the detected speed error is far from a predetermined value.

[0007]

[Operation] According to the PLL speed control method for a DC motor of the present invention, when it is detected that the detected position error output from the position error detector is far from a predetermined value, the value corresponding to this detected position error is Fluctuations in the detected position error that is added by the adder and output from the position error detector are suppressed. The same applies to the detected speed error and the sum of the detected position error and the detected speed error.

[0008]

[Examples] The present invention will be explained below with reference to Examples. Figure 1
1 is a block diagram showing the configuration of a first embodiment of the present invention. FIG. The position error detector 1 compares the position target value and the output pulse from the pulse generator connected to the DC motor 7 to detect a position error, and the speed error detector 2 detects the position error by comparing the position target value and the output pulse from the pulse generator connected to the DC motor 7. The speed error is detected by comparing the output pulses from the generator. A detected position error is smoothed by a low-pass filter 3, and a detected velocity error is smoothed by a low-pass filter 4. An adder 5 adds the output of the low-pass filter 3, the output of the low-pass filter 4, and the output of a position error detector compensation circuit 20 (described later), and the output of the adder 5 is supplied to an amplifier 6 for amplification. The DC motor 7 is driven. As a reference voltage for the adder 5 and the amplifier 6, a voltage Vr1 obtained by dividing the voltage V1 by resistance is applied to the non-inverting input terminals of the adder 5 and the amplifier 6.

The position error detector compensation circuit 20 is connected to the switch 1
The output VP of the low-pass filter 3 is supplied to the voltage follower 11 through 0 to detect the position error output, and subjected to impedance conversion, and the output of the voltage follower 11 is supplied to the low-pass filter 12 with a large time constant for smoothing. turned into
The output VP1 of the low-pass filter 12 is a transistor Tr.
1, Tr2, resistors R12, R13 that constitute the voltage dividing circuit,
It consists of R14 and is supplied to the limiter circuit 13 to output VP.
Limit the level of 1. The output VP1 is supplied to an adder 5, where it is added to the output VP of the low-pass filter 3 and the output VF of the low-pass filter 4, and the difference with the reference voltage Vr1 is amplified.

Therefore, in the first embodiment described above, the sum of the detected position error output VP, the detected error output VF, and the output VP1 of the position error detector compensation circuit 20 becomes the error output, and the position error loop gain is kept small. The position error detection output can be kept virtually close to the desired value while
There is no longer a situation where the PLL circuit cannot lock.

Next, a second embodiment of the present invention will be explained. FIG. 2 is a block diagram showing the configuration of a second embodiment of the present invention. In this embodiment, the same components as in the first embodiment are denoted by the same reference numerals, and the explanation thereof will be omitted. The position error detector compensation circuit 21 is provided with an inverting amplifier 14 instead of the voltage follower 11 of the position error detector compensation circuit 20,
Using the output voltage Vr1 of the voltage dividing circuit 8 as a reference, the difference with the output voltage VP of the low-pass filter 3 is detected and amplified, the output voltage of the inverting amplifier 14 is supplied to the low-pass filter 12 and smoothed, and the output voltage of the low-pass filter 12 is The level of Vr2 is limited by a limiter 13. The output Vr2 of the low-pass filter 12 is the output voltage V of the low-pass filter 3.
P and the output voltage VF of the low-pass filter 4 are added by an adder 5A, the difference with the reference voltage Vr2 is amplified, and the output voltage of the adder 5A is supplied to the amplifier 6A, which amplifies the output voltage VM of the amplifier 6A. to drive the DC motor 7.

In the second embodiment of the present invention described above, it is assumed that the load torque of the motor 7 increases. It is assumed that the increase in voltage VM is covered by the increase in position error detector output voltage VP. On the other hand, since the position error detector output voltage VP is inverted and amplified by the inverting amplifier 14, the voltage Vr2 decreases. Since the speed error is small, the speed error detector output voltage VP hardly changes. Generally, the ratio of resistance R9/R1 is small. Therefore, when viewed from the adder 5A, the current is input from the resistor R7 at the current input point. The current input from the resistor R1 is suppressed by that amount, resulting in stability. In other words, the increase in the speed error detector output voltage VP can be small.

Next, a third embodiment of the present invention will be explained. FIG. 3 is a block diagram showing a third embodiment of the present invention. In the third embodiment, the position error detector output VP is supplied to the non-inverting amplifier 14A to amplify the difference between the voltage V1 and the divided voltage Vr1 obtained by dividing the voltage V1 by resistance, and the amplified output is smoothed by the low-pass filter 12. . The output of the low-pass filter 12 is added to the position error detector output voltage VP by an adder 15 which uses the reference voltage as a divided voltage Vr1, and the difference with the reference voltage Vr1 is amplified and supplied to the adder 5 for speed error detection. Output voltage VF
and add.

Next, a fourth embodiment of the present invention will be described. FIG. 4 is a block diagram showing a fourth embodiment of the present invention. In the fourth embodiment, the difference between the output voltage VP of the position error detector 1 smoothed by the low-pass filter 3 and the divided voltage Vr1 is amplified by the amplifier 14A, and the output of the amplifier 14A is supplied to the low-pass filter 12. The output of the low-pass filter 12 is supplied to the limiter 13 for limiting, and is also applied to the amplifier 16, where the difference between the output voltage VP and the position error detector 1 is amplified, and the output is supplied to the adder 5. and add it to the output of the speed error detector 2.

In the first to fourth embodiments described above, the limiter 13 essentially functions to quickly shift to constant speed at the time of startup. Further, as shown in FIG. 1, the switches 9 and 10 may be provided until the DC motor 7 reaches a constant speed. As shown in FIG. 1, the switch 9 is turned on and the switch 10 is turned off at startup, and the switch 9 is turned off and the switch 10 is turned on at constant speed.

Next, a fifth embodiment of the present invention will be explained. FIG. 5 is a block diagram showing a fifth embodiment of the present invention. In the sixth embodiment described below, this embodiment detects that the speed error detector output deviates from a predetermined value, and operates the position error detector output close to the predetermined value. The present embodiment shown in FIG. 5 corresponds to the first embodiment shown in FIG. The output of the low-pass filter 4 is transferred to the amplifier 14.
The voltage Vr1 obtained by dividing the voltage V1 by resistance is compared with a reference and inverted and amplified. Amplifier 14
The output of the low-pass filter 12 is supplied to the low-pass filter 12 for smoothing, and the output of the low-pass filter 12 is added to the output voltage VP of the low-pass filter 3 and the output voltage VF of the low-pass filter 4 in the adder 5. The gain of amplifier 14 is R6/R5
By defining each constant as 1/R7 = 1/R8 ・R6 /R5, the output V of the speed error detector 2
The DC component of the difference between F and voltage Vr1 can be canceled out. Therefore, the position error detection output due to the output error of the speed error detector 2 can be maintained at a predetermined value. The limiter circuit 13 is not necessary in a constant speed state because there is only a variation that is irrelevant after the PLL is locked in a steady state, but it is necessary when starting the DC motor 7. Reference numeral 24 indicates a speed error detector compensation circuit.

Next, a sixth embodiment of the present invention will be described. FIG. 6 is a block diagram showing a sixth embodiment of the present invention. The sixth embodiment corresponds to the second embodiment shown in FIG. The difference between the output of the speed error detector 3 and the voltage Vr1 is amplified by the amplifier 14A, and the output of the amplifier 14A is supplied to the low-pass filter 12 for smoothing. The output Vr2 of the low-pass filter 12 is supplied as a reference voltage to the adder 5 and the amplifier 6, and by changing the reference voltage Vr2 of the adder 5, a voltage corresponding to the difference between the output of the speed error detector 3 and the voltage Vr1 is applied. , fluctuations in the position error detector output due to changes in the speed error detection output can be suppressed. Here R6 <<R
5. Determine the constant under the conditions of 5. Resistor R2 and capacitor C
2 is a low-pass filter 13 with a large time constant. Further, the action of the limiter circuit 13 is the same as in the fifth embodiment. Reference numeral 25 indicates a speed error detector compensation circuit.

Next, a seventh embodiment of the present invention will be described. FIG. 7 is a block diagram showing a seventh embodiment of the present invention. The output VP of the position error detector 1 and the output VF of the speed error detector 2 are added one-to-one in an adding circuit 14B, and the difference with the voltage Vr1 is amplified in cooperation with resistors R15 and R16.
The output of the adder circuit 14B is supplied to the low-pass filter 12. The output of the low-pass filter 12 is supplied to the adder 5 and added to the sum of the outputs VP and VF. Now, set the resistances R15 to R16 = 1 to 6, and R8 = R1
or R15 >> R16 and R8 = R
If it is set to 1/6, the deviation of the output VP from the voltage Vr1 can be suppressed to 1/4. Reference numeral 26 indicates an error detector compensation circuit. FIG. 8 shows that the low-pass filter 12 is connected to the voltage V
This shows a case where only P is smoothed. By smoothing only the voltage VP with the low-pass filter 12, it is possible to quickly follow up at startup.

Next, an eighth embodiment of the present invention will be described. FIG. 9 is a block diagram showing an eighth embodiment of the present invention. In the eighth embodiment, the output VP of the position error detector 1 is non-invertedly amplified with respect to the output VF of the speed error detector 3 by an amplifier 14B. That is, the difference between the output VP and the output VF is amplified, and the amplified output is supplied to the low-pass filter 12 for smoothing. An adder 5 adds the output of the low-pass filter 12 to the sum of the output VF and the output VP. Reference numeral 27 indicates an error detector compensation circuit.

[0020]

As explained above, according to the present invention, it is possible to detect that the position error detection output, the speed error detection output, the sum of the position error detection output and the speed error detection output exceeds a predetermined value; The position error can be calculated by adding a value corresponding to the output to the sum of the position error detection output and the speed error detection output, or by changing the reference voltage of the adder for the position error detection output and the speed error according to the value. The detection output is suppressed within a predetermined value, and the PLL becomes locked.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a sixth embodiment of the present invention.

FIG. 7 is a block diagram showing a seventh embodiment of the present invention.

FIG. 8 is a block diagram showing a modification of the seventh embodiment of the present invention.

FIG. 9 is a block diagram showing an eighth embodiment of the present invention.

[Explanation of symbols]

1 Position error detector 2
Speed error detector 3, 4, 12 Low-pass filter 5 Adder 7 DC motor 13
Limiter circuit 20, 21, 24, 25, 26
, 27 Error detector output error compensation circuit

Claims (6)

[Claims] 1. A position error detector that compares a position target value with the output of a pulse motor connected to a DC motor, and a speed error detector that compares a speed target value with the output of the pulse motor, the detection position being In a PLL speed control method for a DC motor in which the error and the detected speed error output are added together using an adder, the added output is amplified, and the amplified output drives the DC motor, the detected position error output from the position error detector is set to a predetermined value. A direct current that is characterized by detecting that the detected position error is far from the value and further adding a value corresponding to the detected position error using an adder to bring the detected position error output from the position error detector within a predetermined range. PLL speed control method for motor. 2. A position error detector that compares a position target value and an output of a pulse motor connected to a DC motor, and a speed error detector that compares a speed target value and an output of the pulse motor, In a PLL speed control method for a DC motor, in which a position error and a detected speed error output are added together using an adder, the added output is amplified, and the DC motor is driven by the amplified output, the detected position error output from a position error detector is a predetermined value. The DC current is characterized in that the reference value of the amplification is varied according to the detected position error by detecting that the position error is far from the detected position error, and the detected position error output from the position error detector is within a predetermined range. PLL speed control method for motor. 3. A detection device comprising: a position error detector that compares a position target value and an output of a pulse motor connected to a DC motor; and a speed error detector that compares a speed target value and an output of the pulse motor. In a PLL speed control method for a DC motor in which the position error and the detected speed error output are added together using an adder, the added output is amplified, and the DC motor is driven by the amplified output, the detected speed error output from the speed error detector is It is characterized by detecting that the speed is far from a predetermined value and adding a value corresponding to the detected speed error using an adder to bring the detected position error output from the position error detector within a predetermined range. PLL speed control method for DC motor. 4. A position error detector that compares a position target value and an output of a pulse motor connected to a DC motor, and a speed error detector that compares a speed target value and an output of the pulse motor, In a PLL speed control method for a DC motor in which the position error and the detected speed error output are added together using an adder, the added output is amplified, and the DC motor is driven by the amplified output, the detected speed error output from the speed error detector is The method is characterized in that the detection position error output from the position error detector is brought within a predetermined range by detecting that the position error is far from a predetermined value and varying the reference value of the amplification according to the detected speed error. PLL speed control method for DC motor. 5. A position error detector that compares a position target value and an output of a pulse motor connected to a DC motor, and a speed error detector that compares a speed target value and an output of the pulse motor, In a PLL speed control method for a DC motor in which the position error and the detected speed error output are added together using an adder, the added output is amplified, and the amplified output drives the DC motor, the detected position error output from the position error detector and It is detected that the sum of the detected speed error output from the speed error detector is far from a predetermined value, and an adder further adds a value corresponding to the sum of the detected position error and the detected speed error to determine the position. A PLL speed control method for a DC motor, characterized in that a detected position error output from an error detector is kept within a predetermined range. 6. A detection device comprising: a position error detector that compares a position target value and an output of a pulse motor connected to a DC motor; and a speed error detector that compares a speed target value and an output of the pulse motor. In a PLL speed control method for a DC motor in which a position error and a detected speed error output are added together using an adder, the added output is amplified, and the DC motor is driven by the amplified output, the detected position error output from a position error detector is A deviation from the detected speed error output from the speed error detector is detected, and a value corresponding to this detection output is further added in an adder to bring the detected position error output from the position error detector within a predetermined range. A PLL for a DC motor characterized by
Control method.