JPH04302118A - Chip type laminated capacitor - Google Patents

Abstract

PURPOSE:To obtain at low cost a highly reliable chip type laminated ceramic capacitor having both high voltage-withstand characteristics, especially the suppressing performance of creeping discharge, when the AC current is applied and high humidity resistance and load life characteristics, and also having no electrochemical deterioration for the ceramic dielectric layer between an inner electrode and a terminal electrode. CONSTITUTION:Protective dielectric layers 16 and 17 are laminated on the outermost ceramic dielectric layer 13a and 13g, protective electrodes 16a, 16b, 17a and 17b are formed by printing on the surface of the protective dielectric layers 16 and 17 opposing to the enveloping part of the bare chip end part of the terminal electrodes 12a and 12b, and the protective electrodes 16a, 16b, 17a and 17b are connected to the terminal electrode in such a manner that they become equipotential to the terminal electrodes 12a and 12b.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type multilayer ceramic capacitor for surface mounting. More specifically, the present invention relates to internal electrodes of multilayer ceramic capacitors.

0002

[Prior art] Chip type multilayer ceramic capacitors are
It is widely used as a surface-mounted electronic component that is directly mounted on the surface of a substrate or the like. This capacitor forms a bare chip in which a plurality of internal electrodes face each other by alternately stacking internal electrodes and a ceramic dielectric, and the internal electrode is taken out at the end of this bare chip, and the taken out part is included in the capacitor. It is made by covering the ends of a bare chip to form terminal electrodes for external connection. On the other hand, the technological development of multilayer ceramic capacitors has progressed in recent years, and multilayer ceramic capacitors are beginning to be used in fields where tantalum capacitors and electrolytic capacitors have traditionally been used. Examples include smoothing capacitors for switching power supplies. In such applications, capacitors are required to have large capacity and high withstand voltage, and in addition, withstand voltage characteristics under alternating current and moisture resistance and load life characteristics under alternating current are important.

0003

[Problems to be Solved by the Invention] However, in chip-type multilayer ceramic capacitors, the glass components in the glass frit contained in the terminal electrodes tend to diffuse into the ceramic dielectric layer of the chip and form electrically weak parts. If an alternating current is applied to a capacitor with moisture infiltrating the terminal electrode portion, and a current is constantly passed through the capacitor, electrochemical deterioration or corrosion may occur in the dielectric layer near the terminal electrode. This tendency is particularly noticeable in the ceramic dielectric layer between the outermost layer where no internal electrode is formed and the terminal electrode wrapped around the bare chip end, and there is a risk of insulation failure in this dielectric layer. Ta. Furthermore, when a high voltage is applied to a chip-type multilayer ceramic capacitor in air, a phenomenon called creeping discharge occurs. This is between the terminal electrode in the dielectric layer on the surface of the capacitor and the outermost layer of the internal electrode facing it.
This is a phenomenon in which corona discharge occurs and current flows. This phenomenon occurs particularly markedly with alternating current, and occurs at about 500 Vrms, and therefore becomes a big problem in power supply applications. When a voltage higher than the corona generation voltage is applied, the corona becomes larger,
Eventually, a discharge will occur between the opposing terminal electrodes,
There was a risk of insulation failure or dielectric breakdown of the dielectric layer. To prevent this creeping discharge, conventional capacitors are coated with insulating oil on the surface of the capacitor or sealed with resin for the entire circuit, but additional oil coating and resin sealing processes are required. There was a problem.

The object of the present invention is to have high withstand voltage characteristics when alternating current is applied and moisture resistance load life characteristics under alternating current, and also to prevent electrochemical deterioration of the ceramic dielectric layer between the internal electrode and the terminal electrode. Our objective is to provide a chip-type multilayer ceramic capacitor that never fails. A further object of the present invention is to provide a chip-type multilayer ceramic capacitor that essentially prevents creeping discharge and does not require surface treatment.

[0005]

[Means for Solving the Problems] The present inventors have discovered that the cause of poor insulation between the terminal electrode and the opposing internal electrode, which occurs when alternating current is applied to a conventional capacitor, is due to the dielectric layer of the glass frit. It has been found that the problem can be solved by removing at least one of the following three points: diffusion, moisture, and electric current. Determining the composition of the glass frit so that it does not diffuse into the dielectric layer greatly affects the mechanical properties and solderability of the terminal electrode, so it is not easy to find the optimal composition, and The present invention was achieved by blocking the current flow in the dielectric layer, since the presence of the dielectric layer is unavoidable. The present inventors also discovered that corona discharge occurs along the electric field applied between the terminal electrode and the internal electrode facing thereto. Therefore, in order to prevent the occurrence of corona discharge and avoid the occurrence of creeping discharge, it is sufficient to block the current in the dielectric layer as described above, and for this purpose, a structure is created in which no electric field is applied to the dielectric layer that the terminal electrode surrounds. After some consideration, we arrived at the present invention. That is,
As shown in FIGS. 1 and 2, the present invention provides a plurality of ceramic dielectric layers 13a to 1 having internal electrodes 14 printed on their surfaces.
3g are stacked so that the internal electrodes face each other and the bare chip 11 has the internal electrodes 14 taken out at the ends 11a and 11b. A pair of terminal electrodes 1
2a and 12b. Its characteristic structure is that the outermost ceramic dielectric layers 13a and 13g are covered with a protective dielectric layer 16.
, 17 are laminated, and protective electrodes 16a, 16b, 17a, 17b are printed on the surfaces of the protective dielectric layers 16, 17, facing the wrapped portions of the bare chip ends of the terminal electrodes 12a, 12b. 16a, 16b, 17a, 17
b is connected to the terminal electrodes so as to have the same potential as the terminal electrodes 12a and 12b.

[0006]

[Operation] Protective electrode 16a serves as a dummy electrode for internal electrodes.
, 16b, 17a, 17b as the outermost internal electrode 14a,
By providing the internal electrodes 14a and 14g near the unextracted portion, when alternating current is applied to the capacitor, the internal electrodes 14a and 14g are connected to the unextracted portion and the terminal electrode 12.
No electric field is applied to the dielectric layer between a and 12b and the wrapped portion of the end of the bare chip. As a result, even if there is a glass frit diffusion layer or moisture in the dielectric layer facing the part where the terminal electrodes 12a and 12b are wrapped at the end of the bare chip, the flow of current itself is blocked in this dielectric layer. electrochemical corrosion will no longer occur. Also,
Since no electric field is applied, no corona discharge occurs,
Creeping discharge can be prevented without surface treatment of the capacitor.

The present invention will be explained in detail below. As shown in FIGS. 1 and 2, the chip-type multilayer ceramic capacitor 10 includes a bare chip 11, both ends 11a of the bare chip 11,
11b is provided with a pair of terminal electrodes 12a and 12b. In the figure, the bare chip 11 has seven ceramic dielectric layers 13
a to 13g, the second protective dielectric layer 16 from the top, the bottom protective dielectric layer 17, and the top cover dielectric layer 1.
It is formed by laminating a total of 10 layers consisting of 8 layers. Note that the number of laminated dielectric layers in the capacitor of the present invention is 10.
Not limited to layers. These dielectric layers 13a to 13g and 16 to 18 are all made of lead perovskite, barium titanate, or other ceramic dielectrics. The surface of each of the seven ceramic dielectric layers 13a to 13g is coated with noble metals such as Ag, Ag/Pd, and Pt, or Ni and F.
A conductive paste containing base metals such as E and Co is applied, and internal electrodes 14a to 14g are formed by printing, respectively. Further, the same conductive paste as that for the dielectric layers 13a to 13g is applied to the surfaces of the two protective dielectric layers 16 and 17, and pairs of protective electrodes 16a and 16b and 17a and 17b are formed by printing, respectively. These protective electrodes 16a, 16
b, 17a, and 17b are taken out at both ends of the dielectric layers 16 and 17, respectively. These internal electrodes 14a to 14
Odd-numbered internal electrodes 14a, 14c, 14e, and 14g of the ceramic dielectric layers 13a to 13g are taken out to the right of the ends of the dielectric layers 13a, 13c, 13e, and 13g. Furthermore, even-numbered internal electrodes 14b, 14d, and 14f of the ceramic dielectric layers 13a to 13g are connected to the dielectric layer 13b.
, 13d, and 13f. The inner electrode 14a of the outermost ceramic dielectric layer 13a, 13g,
It is not necessary to provide the protective electrodes 16b and 17b near the lead-out portion of 14g because these lead-out portions play the same roles, but it is better to provide the protective electrodes with a symmetrical printed pattern, since the protective dielectric layer 16 , 17 and its lamination process can be simplified, which is preferable.

The ceramic dielectric layers 13a to 13g and the protective dielectric layers 16 and 17 are punched out to a predetermined size and are press-bonded together with the uppermost cover dielectric layer 18. After the crimped body is cut into a predetermined chip size, it is fired to become a bare chip 11. End portions 11a, 1 of this bare chip 11
1b is barrel-polished to ensure reliable connection with terminal electrodes 12a, 12b. After polishing, a conductive paste containing one or more of Ag, Pd, Pt, and Cu is applied so as to wrap around the ends 11a and 11b.

The applied paste is baked onto the ends 11a and 11b of the bare chip 11. As a result, the terminal electrodes 12a, 12b are connected to the ends 11a, 11b of the bare chip 11.
and is connected to the internal electrode 14. Protective electrodes 16a, 16b and 17a, 17b are terminal electrodes 1
It faces the wrapped portion of the bare chip ends of 2a and 12b. Protective electrodes 16a, 17a and internal electrodes 14b, 14d, 14f are connected to the terminal electrode 12a.
Protective electrodes 16b, 17b and internal electrodes 14a, 1
4c, 14e, and 14g are connected. terminal electrode 12a,
An electroplating layer, such as a Ni plating layer or a Sn/Pb plating layer, may be formed on the surface of the layer 12b, if necessary. Although not shown, the extraction parts of the internal electrodes are provided alternately on the left and right parts of one end of the bare chip in the order in which the dielectric layers are stacked, and a pair of lead-out parts are provided so as to wrap around the left and right parts, respectively. The protective electrode of the present invention can be similarly provided on a chip-type multilayer ceramic capacitor forming a terminal electrode.

0010

As described above, according to the present invention, a protective electrode is printed as a dummy electrode on the layer surface of a protective dielectric layer, facing the bare chip encasing portion of the terminal electrode, and the protective electrode is attached to the terminal electrode. By connecting the terminal electrode so that it has the same potential as the electrode, when alternating current is applied to the capacitor,
No electric field is applied to the dielectric layer between the portion from which the internal electrode is removed and the portion of the terminal electrode that wraps around the bare chip end. As a result, even if there is a glass frit diffusion layer or moisture in the dielectric layer facing the part of the bare chip end where the terminal electrode is wrapped, the current itself will not flow through this dielectric layer. No electrochemical corrosion occurs. Further, since no electric field is applied to this dielectric layer, the occurrence of corona discharge can be suppressed, and the occurrence of creeping discharge can be prevented. As a result, an extremely reliable multilayer ceramic capacitor can be obtained, and surface treatment of the capacitor can be made unnecessary. In particular, the capacitor of the present invention can use conventional dielectric materials and terminal electrode materials, and the lamination process is the same as the conventional process except for the protective electrode layer, so it can be mass-produced at low cost. There are some advantages to doing so.

[0011]

EXAMPLES Next, examples of the present invention will be explained together with comparative examples. <Example> Lead perovskite-based dielectrics were used for the ceramic dielectric layer, the protective dielectric layer, and the cover dielectric layer. The ceramic dielectric layer has an interlayer spacing of 8
It was configured so that the capacitance was 47.3 nF at 0 μm. The internal electrodes and protective electrodes are made of Ag/Pd paste in Figure 2.
It was formed by coating the surface of each dielectric layer as shown in FIG. Furthermore, after applying Ag/Pd paste to both ends of the bare chip as shown in FIG. 1, baked terminal electrodes were formed. This ceramic capacitor is 4.5mm long and 3mm wide.
．． It had a thickness of 3 mm and a thickness of 1.7 mm, and had JIS-R characteristics. <Comparative Example> A ceramic capacitor was produced in the same manner as in the example except that a protective dielectric layer was not laminated and a protective electrode was not provided.

<Test Methods> The following two types of tests were conducted on the ceramic capacitors of Examples and Comparative Examples. The number n in parentheses is the number of samples tested. (a) AC humidity resistance load test (n = 30) At a temperature of 85°C and a relative humidity of 85%, an AC voltage of 50 Hz at 250 Vrms was applied, and the presence or absence of deterioration or destruction was examined after 1,000 hours and up to 10,000 hours. Ta. (b) AC withstand voltage test (n=30) Pressure increase rate 100Vrms in air and silicone oil
An alternating current voltage of 50 Hz was applied at a speed of 50 Hz/sec, and the voltage at which discharge started was measured. Table 1 shows the results of (a) and (b) above.
Shown below.

<Test Results and Evaluation> In the AC humidity resistance load test, the humidity resistance of the example in which a protective electrode was formed was significantly improved compared to the comparative example in which no protective electrode was formed, and no capacitors broke down after 1000 hours. Ta. On the other hand, some of the capacitors in the comparative example broke down after several tens of hours, and three, or 10% of the capacitors, broke down by the time 300 hours had passed. In the AC withstand voltage test, the example in which the protective electrode was formed did not cause creeping discharge even in the air, and the variation in breakdown voltage was reduced, and as a result, the average value was improved compared to the comparative example. Furthermore, in the capacitors of the examples, all of the destruction occurred in the internal electrode portions, but in the capacitors of the comparative examples, some creeping discharge occurred when tested in air. From the above, it was found that the example had extremely high reliability compared to the comparative example.

[0014]

[Table 1]

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a chip-type multilayer ceramic capacitor of the present invention.

FIG. 2 is a perspective view showing how the protective dielectric layer and ceramic dielectric layer are stacked.

[Explanation of symbols]

10 Chip type multilayer ceramic capacitor 11 Bare chips 11a, 11b Bare chip ends 12a, 12b Pair of terminal electrodes 13a to 13g Ceramic dielectric layers 14a to 14g
Internal electrodes 16, 17 Protective dielectric layer

Claims (3)

[Claims] 1. By laminating a plurality of ceramic dielectric layers (13a to 13g) each having internal electrodes (14) printed on the layer surface, the internal electrodes face each other and are located at the ends (11a, 11b). A bare chip (11) from which the internal electrode (14) has been taken out, and an end portion (11) of the bare chip.
a, 11b) so as to wrap around the internal electrodes (14).
), the chip-type multilayer ceramic capacitor (10) includes a pair of terminal electrodes (12a, 12b) connected to the outermost ceramic dielectric layers (13a, 13).
g) protective dielectric layers (16, 17) are laminated, and the terminal electrode (1) is formed on the surface of the protective dielectric layer (16, 17).
Protective electrodes (16a, 16b, 17a, 17b) are printed and formed opposite to the wrapped portions of the bare chip ends of 2a, 12b).
7b) is a chip-type multilayer ceramic capacitor, characterized in that it is connected to the terminal electrodes (12a, 12b) so as to have the same potential. [Claim 2] Protective electrodes (16a, 16b, 17a,
17b) is printed on the surface of the protective dielectric layer (16, 17) opposite to the enclosing portions of both ends (12a, 12b) of the bare chip. [Claim 3] The outermost ceramic dielectric layer (13a
, 13g), the protective electrodes (16a, 17a) are placed on the protective dielectric layer (1
6, 17) The chip type multilayer ceramic capacitor according to claim 1, wherein the chip type multilayer ceramic capacitor is printed on the surface of the chip type multilayer ceramic capacitor.