JPH04301981A - Image pickup signal processing circuit - Google Patents

Abstract

PURPOSE:To remove the influence of a noise component caused by the impedance of a power supply line or a ground line and to reduce picture quality degradation caused by wrong correction. CONSTITUTION:The image pickup output signal of a CCD image sensor 1 is supplied through a first sample/hold circuit 3 to a first signal adder 4 and supplied through a second sample/hold circuit 6 to a differential amplifier 8 after adding a blemish compensating signal. On the other hand, the image pickup output signal of the CCD image sensor 1 is supplied through a third sample/hold circuit 7 to the differential amplifier 8 after adding a reference level signal by a second signal adder 5.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a charge-coupled device (CCD) including a defective pixel that generates a signal component independent of incident light.
The present invention relates to an imaging signal processing circuit that performs blemish correction processing on an imaging output signal from a solid-state imaging device such as a 3D imaging device (Charge Coupled Device).

0002

2. Description of the Related Art In general, in a solid-state image pickup device such as a CCD formed of a semiconductor, defective pixels that output a signal at a peculiar level even when no light is incident are generated due to local crystal defects in the semiconductor. It is known that image quality deteriorates due to the image pickup output from this defective pixel. As defective pixels in the solid-state image sensing device, for example, black defective pixels that appear as black dots and white defective pixels that appear as white dots are known in the image output from the solid-state image sensor on a monitor screen. From the defective pixel, an offset voltage corresponding to the defect level is added to an imaging output corresponding to the amount of incident light, and the resulting image is output. This type of pixel defect is called a blemish. Conventionally, data about the position of the defective pixel included in a solid-state image sensor and the blemish level, that is, the defect level included in its output signal, is stored in a memory. Based on the data read from the defective pixel, image quality deterioration caused by the image output from the defective pixel is corrected by signal processing.

That is, as shown in FIG. 3, for example, the imaging output signal CCDOUT of the solid-state imaging device 21 is supplied to a signal adder 23 for blemish correction processing via a correlated double sample and hold circuit 22, and this signal addition Vessel 2
3, the blemish correction signal SBR is added and mixed to undergo blemish correction processing and is output from the signal output terminal 24. The blemish correction signal SBR is generated by a blemish correction signal generation circuit 25 in response to a timing signal from a timing generator (not shown), and is supplied to the signal adder 23 after being phase adjusted by a phase adjustment circuit 26.

Here, the correlated double sample and hold circuit 22 includes a first sample and hold circuit 31 activated by the first sampling pulse SHP, and second and third sample hold circuits activated by the second sampling pulse SHD. It comprises hold circuits 32 and 33, and a differential amplifier 34 to which sampling outputs from the second and third sample and hold circuits 32 and 33 are supplied.

The correlated double sample and hold circuit 22 reduces random noise components contained in the image pickup output of the solid-state image pickup device 21 by a correlated double sample and hold method, and as shown in FIG. The black level LB of the imaging output signal CCDOUT of the element 21 is
The sample and hold circuit 31 samples and holds the black level signal SLBP using the first sampling pulse SHP, and the second sample and hold circuit 32 samples and holds the black level signal SLBP using the first sampling pulse SHP. At the same time, the video level LS of the imaging output signal CCDOUT of the solid-state image sensor 21 is sampled and held by the third sample and hold circuit 33 using the second sampling pulse SHD, and The difference between the sampled and held black level signal SLBD and the video level signal LSD is extracted by the differential amplifier 34 as the video signal CDSOUT.

The signal adder 23 supplies the video signal CDSOUT whose random noise component has been reduced by the correlated double sample and hold circuit 22 from the blemish correction signal generation circuit 25 via the phase adjustment circuit 26. Blemish correction processing is performed by adding and mixing the blemish correction signals SBR.

[0007]

[Problems to be Solved by the Invention] However, in the conventional imaging signal processing circuit for blemish correction processing as described above,
In the signal adder 23, the video signal CDSOUT
If the blemish correction signal SBR is not added to the video signal CDSOUT in the same phase as the video signal CDSOUT, the image quality will deteriorate due to the correction error. Therefore, as shown in FIG.
Therefore, it is necessary to perform phase adjustment of the blemish correction signal SBR with high precision, and delicate phase adjustment must be performed in consideration of variations in the output phase of the circuit constituent elements.

In addition, in the correlated double sample hold circuit 22, when defect correction is performed by so-called zero-order hold by stopping the second sampling pulse SHD at the timing of image pickup output from the defective pixel, this correlation Since no blemish component is output to the video signal CDSOUT output from the double sample and hold circuit 22, the video signal CDSOUT does not contain a blemish component.
The blemish correction signal SBR is added to and mixed with T, resulting in image quality deterioration due to incorrect correction. Further, in such defect correction, since the previous data is maintained, if the data includes a blemish component, the image quality will deteriorate due to the blemish component.

Furthermore, when the gain of the correlated double sample hold circuit 22 is changed, the signal adder 2
Unless the addition/mixing ratio of the video signal CDSOUT and the blemish correction signal SBR in step 3 is also changed, image quality deterioration will occur due to the correction error. Further, the power supply line and the ground line have impedances 27 and 28 due to wiring patterns and harnesses, and the blemish correction signal SBR generated by the blemish correction signal generation circuit 25 has an electric current flowing through the blemish correction signal generation circuit 25. Noise caused by the flow and noise generated in peripheral circuits are superimposed. This noise component is added to the video signal CDSOUT, in which the random noise component has been reduced by the correlated double sample and hold circuit 22, and the blemish correction signal SB.
In the signal adder 23 that adds R, the video signal S
It is superimposed on OUT, resulting in a correction error.

Therefore, in view of the above-mentioned problems in the conventional image signal processing circuit for blemish correction processing, the present invention aims to solve the problem of correction caused by variations in the output phase of the circuit components, changes in the gain of the processing system, etc. The present invention provides an imaging signal processing circuit that prevents the occurrence of errors, eliminates the influence of noise components due to the impedance of power supply lines and ground lines, and reduces the possibility of image quality deterioration due to correction errors.

[0011]

[Means for Solving the Problems] In order to achieve the above-mentioned object, an imaging signal processing circuit according to the present invention provides blemish processing for a pixel that generates a signal component that does not depend on incident light among a plurality of pixels of a solid-state image sensor. a correction signal generation means for outputting a correction signal together with a reference level signal; a first sample-hold means for sample-holding an imaging output signal from the solid-state imaging device; and an imaging output signal sample-held by the first sample-hold means. a first addition means for adding a blemish correction signal from the correction signal generation means to the first addition means; a second sample and hold means for sampling and holding the imaging output signal to which the blemish correction signal has been added by the first addition means; a second addition means for adding a reference level signal from the correction signal generation means to the imaging output signal from the solid-state imaging device; and sampling and holding the imaging output signal to which the reference level signal has been added by the second addition means. a third sample and hold means; and a differential amplification means to which the imaging output signal sampled and held by the second sample and hold means and the imaged output signal sampled and held by the third sample and hold means are supplied. It is characterized by being prepared.

0012

[Operation] In the imaging signal processing circuit for the solid-state imaging device according to the present invention, the first to third sample-hold means and the differential amplification means convert random noise contained in the imaging output of the solid-state imaging device into correlated components. It functions as a double sample-and-hold circuit that reduces correlation using the sample-and-hold method. Further, the differential amplification means subtracts and synthesizes the imaging output signal to which the blemish correction signal has been added by the first addition means and the imaging output signal to which the reference level signal has been added by the second addition means. It outputs an imaging output signal that cancels out noise components caused by the impedance of power lines, ground lines, etc.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image signal processing circuit for a solid-state image sensor according to the present invention will be described in detail below with reference to the drawings.

The imaging signal processing circuit of the solid-state imaging device according to the present invention is configured as shown in FIG. 1, for example.

The imaging signal processing circuit shown in FIG. 1 is an example in which the present invention is applied to a CCD video camera device using a CCD image sensor 1 as an imaging section. Blemish correction signal SBR for pixels that generate signal components independent of
A correction signal generation circuit 2 is provided which outputs the reference level signal SREF together with the reference level signal SREF.

Here, the correction signal generation circuit 2 stores blemish data indicating the position of a pixel with a blemish and its blemish level, which has been determined by previously performing defect measurement on the CCD image sensor 1,
A blemish correction signal SBR is formed based on this blemish data, and this blemish correction signal SBR is output together with, for example, a ground line reference level signal SREF. As shown in FIG. 2, the blemish correction signal SBR output from the correction signal generation circuit 2 is accompanied by level fluctuations due to the influence of impedances 11 and 12 of the power supply line, ground line, etc., and the reference level signal SREF indicates the level fluctuation.

The CCD image sensor 1 is driven by a CCD drive circuit (not shown), and image charges of each pixel are sequentially read out one horizontal line at a time via a horizontal transfer register. The imaging output signal CCDOUT obtained by this CCD image sensor 1 is
the first signal adder 4 via the sample and hold circuit 3 of
and directly to the second signal adder 5.

The first sample and hold circuit 3 receives the imaging output signal CCDO from the CCD image sensor 1.
The black level of UT is sampled and held by the first sampling pulse SHP. The first sample and hold circuit 1 outputs the imaging output signal CCDOUT by the first sampling pulse SHP.
A black level signal SLBP sampled and held is supplied to the first signal adder 4.

The first signal adder 4 receives the black level signal SL obtained by the first sample and hold circuit 3.
The blemish correction signal SBR from the correction signal generation circuit 2 is added to BP. The first signal adder 4 supplies the black level signal SLBP to which the blemish correction signal SBR has been added to the differential amplifier 8 via the second sample and hold circuit 6.

The second sample and hold circuit 6 receives the blemish correction signal SB by the first signal adder 4.
The black level signal SLBP to which R has been added is sampled and held by the second sampling pulse SHD. The second sample and hold circuit 6 supplies the black level signal SLBD sampled and held by the second sampling pulse SHD to the differential amplifier 8.

Further, the second signal adder 5 has the above C
Imaging output signal CC obtained by CD image sensor 1
The reference level signal SREF from the correction signal generation circuit 2 is added to DOUT, and the added output signal is supplied to the differential amplifier 8 via the third sample and hold circuit 7.

The third sample and hold circuit 7 receives the reference level signal SREF by the second signal adder 5.
The video level of the image pickup output signal CCDOUT to which is added is sampled and held by the second sampling pulse SHD. The third sample and hold circuit 7 supplies the differential amplifier 8 with the video level signal SLSD sampled and held using the second sampling pulse SHD.

The differential amplifier 8 receives the black level signal SLBD sampled and held by the second sample and hold circuit 6 and the video level signal S sampled and held by the third sample and hold circuit 7.
The difference with LSD is extracted as a video signal SOUT and output from the signal output terminal 9.

In the imaging signal processing circuit having such a configuration, the first to third sample holds 3, 6, and 7 and the differential amplifier 8 add random noise to the imaging output signal CCDOUT obtained by the CCD image sensor 1. It functions as a correlated double sample and hold circuit 10 that reduces random noise components by a correlated double sample and hold method, and outputs a video signal SOUT with reduced random noise components from the signal output terminal 9.

[0025] Also, the first sample and hold circuit 3
The black level signal SL of the imaging output signal CCDOUT of the CCD image sensor 1 sampled and held by
Blemish correction processing is performed by adding and mixing the blemish correction signal SBR to B by the first signal adder 4. Here, by adding and mixing the blemish correction signal SBR to the timing portion of the second sampling pulse SHD which further samples and holds the black level signal SLB in the second sample hold circuit 6, image quality deterioration due to correction errors can be prevented. Blemish correction processing can be reliably performed without any interference.

Furthermore, in the correlated double sample and hold circuit 10, when defect correction is performed by so-called zero-order hold by stopping the second sampling pulse SHD at the timing of image pickup output from the defective pixel, erroneous correction may occur. There is no deterioration in image quality due to Further, even when the gain of the correlated double sample and hold circuit 10 is changed, there is no need to change the addition/mixing ratio of the imaging output signal CCDOUT and the blemish correction signal SBR in the first signal adder 4.

Moreover, the differential amplifier 8 generates a black level signal obtained by sampling and holding the black level signal SLBP to which the blemish correction signal SBR has been added by the first signal adder 4 using the second sample and hold circuit 6. SLBD and the reference level signal SREF added by the second signal adder 5 to the imaging output signal CCDO.
A video level signal S obtained by sample-holding the video level LS of UT by the third sample-hold circuit 7
Since the difference from the LSD is extracted as the video signal SOUT, the noise components generated in the correction signal generation circuit 2 and its peripheral circuits due to the influence of the impedance of the power supply line and the ground line are canceled out, resulting in a video signal SOUT with extremely low noise components. can be output from the signal output terminal 9.

[0028]

Effects of the Invention As described above, in the imaging signal processing circuit for a solid-state imaging device according to the present invention, the first to third sample and hold means and the differential amplification means are capable of processing random signals included in the imaging output of the solid-state imaging device. It functions as a correlated double sample and hold circuit that reduces noise components by a correlated double sample and hold method, and performs blemish correction processing by adding and mixing a blemish correction signal to the imaging output signal of the solid-state image sensor using the first signal addition means. Therefore, by adding and mixing the blemish correction signal to the portion sampled and held for each pixel by the second sample hold means, the blemish correction process can be reliably performed without deterioration of image quality due to correction errors. Moreover, the above differential amplifier is
By subtracting and combining the imaging output signal to which the blemish correction signal has been added by the first addition means and the imaging output signal to which the reference level signal has been added by the second addition means, the impedance of the power supply line, ground line, etc. It is possible to obtain an imaging output signal in which the noise component due to the influence is canceled out.

Therefore, according to the present invention, when performing blemish correction processing on an image output signal from a solid-state image sensor, it is possible to prevent the occurrence of erroneous correction due to variations in the output phase of circuit components, changes in the gain of the processing system, etc. It is possible to provide an imaging signal processing circuit that prevents this, eliminates the influence of noise components caused by the impedance of the power supply line and the ground line, and reduces the risk of image quality deterioration due to erroneous correction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an imaging signal processing circuit of a solid-state imaging device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the imaging signal processing circuit shown in FIG. 1;

FIG. 3 is a block diagram showing the configuration of an image signal processing circuit of a conventional solid-state image sensor.

FIG. 4 is a timing chart for explaining the operation of the correlated double sample and hold circuit in the imaging signal processing circuit shown in FIG. 3;

FIG. 5 is a timing chart for explaining the operation of blemish correction in the imaging signal processing circuit shown in FIG. 3;

[Explanation of symbols]

1... CCD image sensor 2...
・Correction signal generation circuits 3, 6, 7...Sample hold circuits 4, 5...
・Signal adder 8...Differential amplifier

Claims (1)

[Claims] 1. Correction signal generating means for outputting a blemish correction signal for a pixel that generates a signal component independent of incident light among a plurality of pixels of a solid-state image sensor together with a reference level signal; and an image pickup output signal from the solid-state image sensor. a first sample-and-hold means for sample-holding the image; a second sample and hold means for sample-holding the imaging output signal to which the blemish correction signal has been added by the addition means; a third sample-hold means for sample-holding the imaging output signal to which the reference level signal has been added by the second addition means; and an imaging output signal sample-and-held by the second sample-hold means. and differential amplification means to which the image pickup output signal sampled and held by the third sample and hold means is supplied.