JPH0430057B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Technical Field> The present invention relates to a method for coupling a data processing device, such as a host processor, to a virtual storage system for the storage of large amounts of digital data under the exclusive control of the virtual storage system. Regarding the device. More particularly, the present invention relates to an apparatus for performing data formatting and compression operations and for interfacing a host processor to a virtual storage system processor.

BACKGROUND It has been a long-standing challenge in the computer and data processing industries to provide less expensive storage devices with faster access times for storing large amounts of digital data. It has become common for large computer devices to have hierarchical level storage for storing data. The selection is made based on the frequency of use of a given data file. That is, a compromise is made between access time and cost of the storage means used. Thus, for example, a large computer device may require a significant amount of access time to advance its least frequently used data file to the point on the tape where it is physically sent to a given tape drive and the desired data is stored. can be stored on a reel of magnetic tape that requires The next step in this hierarchical level storage is typically magnetic disk storage, which comes in several types. As with tape, user-loadable disk drives require an operator to remove a physical disk file and load it onto the drive. However, the access time is quite short. There is an even faster type of disk storage, so-called "fixed head disks." In this fixed head disk configuration, the disk is permanently mounted. Other types of data storage include solid state sequential access storage and random access storage.

It is generally accepted that these methods are too uneconomical for long-term storage and are only used to accommodate datasets that are actually in use. As is common in the prior art, when a user program requests access to a given data file, the host computer assigns the file name to the file on the given tape reel, i.e., the disk drive. It converts to a physical location and issues commands to the tape drive to load a given tape reel or access a specific portion of the disk. The choice of the type of storage device and where a particular user file should be stored on a given storage device is made by the user or operator of the computer device;
At lower ranks, task processing is performed by the host processor. Therefore, this data storage device itself is not intelligent and only responds to commands given by the host. Co-pending U.S. application filed October 18, 1979
No. 85909, an improvement to this device was made, in which the host processor receives data destined for storage on tape and converts the host processor's commands, such as the command ``tape device,'' to a disk drive. A virtual storage device that includes means for converting that information into instructions suitable for storage on the device. This virtual storage device thus mimics a tape drive to the host processor. In this manner, faster access times are provided to the host processor without modification of the host processor operating system.

A device that further develops this concept has been awarded a U.S. patent.
No. 4467421. In this patent, a host processor operating system is modified so that the host processor has little or no control over the resulting storage of the data and simply writes that data to virtual storage. This virtual storage determines where and on what type of storage (generally a disk) the data should be stored. That is, the host processor is freed from this function, thereby improving effective processing power. The efficiency of storage usage is greatly improved when used in conjunction with virtual storage in this manner.

The actual arrangement of virtual storage devices includes devices where in other environments the computer itself would be recognized as the center of the device. In a preferred embodiment
A Magnuaon M80 type computer is used. The computer determines where and on what type of data storage device a given data should be stored. The main memory is used as a ``cache,'' in which data is reformatted from a user-selected record size to a convenient record size for storage in selected long-term storage devices called ``pages.'' For example, in this preferred embodiment, the most common storage mode is for disk drives;
The page size is also chosen to be equal to one disk track. This greatly simplifies addressing and formatting. Thus, data is received record by record from the host processor, and this data is written into "frames" of memory locations within the solid state memory of the Magnuson CPU. Once such a frame is filled with a "page" of data, this page is written to a disk frame of the same size for permanent storage. Such frame-by-frame configurations are important for efficient use of disk storage and, as explained in the aforementioned patents, have significantly improved overall computer operability.

The present invention relates to hardware means used to interface the above-described virtual storage device to one or more host processors. The hardware means itself includes a processing unit for performing pagination of data received from the host processor, and further for performing compression of the data to remove redundant bytes and reduce storage requirements. including means of Of course, this compression is performed prior to paging the user records to an appropriate size for storage in back-end storage.

OBJECTS OF THE INVENTION Accordingly, one object of the invention is to provide improved digital data storage means.

Another object of the invention is to provide a means for interfacing a first type of host processor to a virtual storage system that includes a second type of processor.

Yet another object of the present invention is to write data to a storage device within the virtual processing system upon receiving data from such a host processor in a block size convenient for storage in the storage device within the virtual storage system. The object of the present invention is to provide an apparatus for performing data compression and pagination before data compression and pagination.

Yet another object of the present invention is to provide a means for connecting multiple host processors to a virtual storage system.

SUMMARY OF THE INVENTION In accordance with the present invention, the above needs and the like are met by providing a channel adapter for virtual storage that includes a microprocessor operating a subprocessor for controlling the flow of data through a slave device or system. It achieves the objectives of the invention. The microprocessor is a relatively slow and highly intelligent device, while the subprocessor is a fairly fast device with relatively low intelligence. The microprocessor and subprocessor each control the hardware logic. While the microprocessor controls the allocation of storage locations, pagination of data, and the actual path that data takes through the channel adapter of the present invention, a subprocessor or "sequencer" handles the switching of signal lines. The hardware logic that controls and actually transfers the individual data bytes is monitored.

DESCRIPTION OF EMBODIMENTS As mentioned above, the present invention relates to virtual storage, where a channel adapter connects one or more host processors to the virtual storage system. Performing interfacing functions, the virtual storage system makes decisions, independent of the host processor, as to where and on what type of data storage device a given user record should be stored.

FIG. 1 shows the overall layout of the system along with the host processor and shows the channel adapter and virtual storage system. A host processor 30 is shown with various conventional inputs and outputs. Inputs and outputs are shown in the diagram as cards, printed paper output, and consoles. According to this virtual storage concept, the host processor 30 connects the interface cable 32
At least two channel adapters via 4
0, and this adapter 40 is also connected to the virtual storage device 20. A channel adapter 34 is additionally provided and is connected to an additional host processor as shown. In this manner, one virtual storage device 20 can be used by multiple host processors through at least the same number of channel adapters 34,40. As will be explained in more detail below, there are typically at least two channel adapters 34, 40 per host processor, so that there are alternating paths for carrying out data transmission. Virtual storage 20 is also provided with a console 42 for operator interaction and is connected to mass storage 38 by an interface cable 36. Generally, this storage device 38 may include disk or tape drives and other types of storage devices.

It will be appreciated that the conventional method of allocating space on a magnetic storage device, such as that shown at 38 in FIG. 1, to a given file code is to select a maximum size for each data file. The idea was to force the user to do this and to permanently allocate this much space to the file. Files are underutilized except in relatively unusual situations where files are of a fixed size. That is, it is not completely filled with actual data. Users will inevitably build larger files rather than risk overflowing the space. In this file, the user specifies the appropriate record length,
Additionally, when a file is not being processed, there are choices as to where and on what type of data storage device (eg, disk or tape) the file should be stored. When a user wishes to work with a particular user file, the user specifies its location and specifies which portions of the file are to be transferred from storage to the computational host processor 30. After this calculation is complete, the file is returned to the same location on the long-term storage medium.

In accordance with the present invention, as further described in the co-pending U.S. application cited above, where and on what type of data storage device is a user file provided with virtual storage stored on behalf of a user? decide. Therefore, the user only needs to specify a file name, and the virtual storage device accesses its memory to determine where to store the data and causes the host processor 30 to read that portion. host processor 3
Several important advantages are achieved by performing the storage space allocation function outside of 0 and without operator intervention. One of the most important features is that the user does not have to specify the file size, but only allocates to a given file the storage space actually needed to store the data. This allows the available storage space to be used effectively. A second advantage is that virtual storage allows data to be reformatted into block sizes convenient for storage purposes, rather than being determined by the user's purposes. Thus, for example, a user file is a "page" of data having a size convenient for storage in a storage device selected by virtual storage as the resulting storage location.
divided into For example, in this preferred embodiment, the majority of the storage is located on disk storage. Therefore, a "page" of data is sized equal to the length of one disk track. This can greatly simplify addressing and result in better utilization of disk space. This "paginating" of data is accomplished by providing cache read-state storage 68 in virtual storage 20 that allows pages of data to be assembled before being written to long-term storage 38. executed inside. In a preferred embodiment, virtual storage 20 is a Magnuson
Includes M80 computer. The main memory 68 of this computer becomes the cache memory.
Thus, for example, when the host is outputting data, the data is divided into data storage areas equal in size to the desired data pages in the virtual storage device 2.
0 storage device 68. Note that this divided data storage area is called a "frame". When a given frame of data is filled, virtual storage 20 outputs the data from the cache to the selected track of disk drive 38.

As described in FIG. 1, the channel adapter 40 connects the host processor 30 and the virtual storage device 2.
used to form an interface with 0. It is within these channel adapters that pagination functions are performed. That is, the user data file is reformatted into sub-blocks of page length convenient for the storage device, rather than for the user as in the prior art. Furthermore, it is preferable to perform data compression. This compression involves removing redundancy from the data and replacing it with a compression characteristic that indicates the number of times a given byte is repeated. Obviously, it is preferable to perform such data compression before paging the data;
This is also done in the channel adapter as well.

FIG. 2 shows a functional block diagram of the channel adapter 60 and the virtual storage central processor (VCP) 70. Channel adapter 60 and central processor 64 are connected to virtual storage system (VSS) bus 62. Although the second channel adapter 60 is only partially shown, it means that multiple channel adapters 60 are connected to a single virtual storage system bus 62 that operates in conjunction with a single virtual storage central processor 70. Show that. As previously mentioned, each channel adapter 60 connects to the host processor 3 via the host processor interface unit 74.
0 and to the VSS system bus 62 via a system bus interface 76. Within each channel adapter 60 are a channel adapter processor 78, a host processor data handler 71, and an operation tag handler 73. Operation tag handler 73 applies instructions from host processor 30 to processor 78 and system bus interface 76, which control the flow of data through channel adapter 60. As explained in more detail below, channel adapter processor 78 includes a data processing capable microprocessor, such as a Zilog Z8000. this
Although the Zilog Z8000 has the capability for fairly complex decision-making tasks, it is too slow to perform functions such as switching signals to the host processor interface 74. Therefore, the second processor with limited intelligence but much faster present in the operation tag handler of FIG. 2 is the channel adapter 78.
is subordinate to. This second processor also effectively controls the protocols to the host processor interface 74. The actual movement of data from host processor interface 74 to system interface 76 is performed in hardware. Data compression occurs along this path. The thus compressed data is sent to virtual storage device 64 via bus 62. As mentioned above, the virtual storage device (VSS) 64
is typically formed within a Magnuson M80 computer. The illustrated storage device 68 is a Magnuson
This is a storage device of the M80, in which addresses of various data files stored in a back-end storage device 38 such as a desk or tape are arranged. Assignments are made by the VSS central processor 70.
Storage device 68 may be, for example, a cache memory for temporarily holding one or more data pages for short periods of time while a given backend data storage device 38 is ready to receive data. further including. Alternatively, cache memory may be used to hold all of a given page of data from backend storage 38 before returning it to the host processor via VSS system bus 62 and channel adapter 60. Storage device 68 also stores software programs executed by VCP 64. eventually,
VCP 64 includes channels 72 for connecting to various backend storage devices 38 and operator console 42.

FIG. 3 shows a detailed block diagram of the channel adapter 60 of FIG. 2. Its main components are Zilog or AMDZ8000 microprocessor 8
It is 0. The AMD Z8000 may be duplicated with a second Z8000 81 connected in parallel to detect errors. Subordinate to the Z8000 microprocessor 80 through two 8-bit control registers 84 and 85 is a channel sequencer unit 86, which in the preferred embodiment is
It is an Intel 8X 300 microcontroller chip. This microcontroller chip also
It is controlled by a 2K x 18 bit PROM 88 to ensure proper sequencing and operational control. As previously mentioned, the Z8000 80 microprocessor controls the flow of data, but the channel sequencer 86 actually performs the tasks of gating control registers and signal lines and monitoring hardware data movement due to its considerably higher speed. Process. Thus, while channel sequencer 86 can be said to be subordinate to microprocessor 80, channel sequencer 86 provides significant high speed data processing capabilities. This capability is important to the operation of channel adapter 60.

The figures following FIG. 3 illustrate the paths taken by data and control signals between the major components of the channel adapter 60 of FIG. Fourth
In each of FIGS. 8 to 8, the primary one-way data path is shown by a solid line, and the reverse path is shown by a broken line. The main components traversed by each path are also shown. It is understood herein that these figures
This is a portion of the figure, the rest of which has been omitted for the sake of brevity. When these figures and Figure 3 are viewed together, it can be seen that the overall function of the channel adapter is carried out. Thus, for example:
Figure 4 shows the channel cable 32 connecting the channel adapter 60 to the host processor 30 on the left side of the figure, and the channel adapter 60 and the channel cable 32 that connects the channel adapter 60 to the host processor 30 on the left side of the figure.
The main data coupling between the VCP 70 and the VSS system bus 64 is shown. This connection becomes the path taken by the data when it is written by the host processor 30 to the virtual storage device 20 of the present invention. This data is sent from the channel bus 32 to a receiver 90 and then through a 2:1 multiplexer 92 (a simple switching unit) to a first-in/first-out buffer 94. next
The data is passed through data compression logic 96 operating in a compressed mode under the control of PROM 98 to a second first-in/first-out buffer 100. A detailed hardware diagram of the logic that can be used to perform data compression is described in FIG. The data compressed in this way is transferred from the output buffer 102 to the output register 104.
The signal is sent to the transceiver 106 through the . In the output buffer 102, the FIFO buffer 10
A 9-bit data word sent from 0 (i.e., 8 bits plus the parity bit)
The 64 data bits are assembled into 8 parity bit words convenient for transmission on the VSS bus 64. Once the data is received in the cache memory of VSS processor 70 (FIG. 2), the actual pagination operation, ie, the accumulation of data pages of a convenient size for long-term storage, is performed. Pagination tasks specify the storage area where data is written.
It is generated by the Z8000 microprocessor 80 (see Figure 5).

The dashed paths in FIGS. 3 and 4 indicate the data path used when a read operation is being performed.
First-in/first-out register 9
Data is transferred from transceiver 106 to data input buffer 10 such that the sequence of data compression/decompression logic 96 is the same as that of
8. Multiplex unit 92, first-in/first-out registers 94 and 10
0 from drive 110 through data compression/decompression logic 96 and back to the channel bus. Fourth
These primary data flow paths of the figure, as commanded by the Z8000 microprocessor 80, are sequenced and controlled by the channel sequencer 86 as described above. Control signals are sent from microprocessor 80 through control register 84 to channel sequencer 86, thereby separating Z8000 bus 122 from 8X300 bus 120. The straight path shown in FIG. 4 is called Direct Memory Access (DMA).

dynamic program storage 116 and
PROM 118 is connected to address bus 112 and Z8000 bus 122 to provide Z8000 microprocessor 80 with the necessary inputs for its operation. Similarly, control signals are sent through a control data register 124 that sends commands through a system control bus interface 126 to a system control bus 128. Z8000 microprocessor 80 also sends control signals to DMA via data bus 122.
counter 130 and receives control data from virtual storage 20 when control data register 132 requests it. Z8000 microprocessor 80 uses various registers, tags, opcodes, etc. to assist in the operation of channel sequencer 86 and also operates various diagnostic and error control circuits not shown. These methods will be obvious to those skilled in the art, as will be the appropriate location for a parity check operator to perform error detection and the like.

Looking at the remaining data distribution control paths shown in FIGS. 5 to 8, the operating state of the channel adapter 40 according to the present invention can be seen in more detail. Thus, for example, in FIG.
The data flow paths to Z8000 microprocessor 80 are shown in solid lines, while the control signal flow paths from VSS system data bus 64 back to Z8000 microprocessor 80 are shown in dashed lines. For example, Z8000 microprocessor 80 can send a 24-byte header before each page of data is communicated to host processor 30. Each block within each page is preceded by a byte header. It is through this path that the VSS 20 and channel adapter 40 communicate regarding the sequence of data movement.

In FIG. 6, the flow of control signals from host processor 30 to channel sequencer 86 is shown in solid lines, while the flow of responses is shown in dashed lines. Similarly, in Figure 7, Z8000
The flow of control signals from the microprocessor 80 to the channel bus interface 74 for transmission to the host processor 30 is shown in solid lines;
The flow of control signals to the Z8000 is shown by dashed lines. Such signals may include, for example, fields of data communicated from host processor 30 to channel adapter 60 for compression and subsequent communication to long-term storage virtual storage 20, regarding particulars related to the operation of channel adapter 60. It can be a signal with a size.

In FIG. 8, the distribution of signals from channel sequencer 86 directly to channel bus 32 is shown. This path is not normally used and communications from host processor 30 are not routed through slave channel sequencer 86 and are normally
This is done through the Z8000 microprocessor 80. However, this path may be used, for example, by the host processor 30 when the channel adapter is already transmitting data or is full to assemble.
used to send a "busy" signal to the Host processor 30 tries second channel adapter 60 if second channel adapter 60 is connected to host processor 30 for this purpose. The reverse path (dashed line) made from channel bus 32 to channel sequencer 68 is only used for diagnostic purposes.

FIG. 9 shows one possible hardware implementation that can compress data. generally 8
A byte with a width of bits is stored in the first register 100.
and then compared with the contents of the second register 102 in a comparator 104, shown as an AND gate. If both are the same, comparator 1
04 outputs a high signal to the configuration input of flip-flop 106. If this signal is the first high input to the set input of flip-flop 106, counter 108 is reset to one.
At the same time, escape character generator 110 outputs a predetermined character on output line 112. On the other hand, if flip-flop 106 is set to all, the only result of comparator 104 outputting a high signal is to increase the value of counter 108. Registers 100 and 102
The contents of are also compared in NAND gate 114. Thus, a series of identical bytes are detected by comparator 10.
4 and counted in counter 108, if the byte is
If this byte is not the same as the byte stored in register 102, the flip
Flop 106 is reset. That is, the output from flip-flop 106 causes counter 108 to transmit its contents to output line 11.
6 and at the same time the contents of register 102, ie the repeat byte, are also output on output line 118. The escape character along with the repetition number and the example of the repetition byte are thus stored in the same byte in a predetermined position. As will be appreciated herein, this process is only useful if the number of repeat bytes is at least equal to the number of bytes needed to indicate that compression has been performed (in this case 4). This can be done by adding another register to the register shown and by adding an AND gate 10
This can be done simply by providing multiple inputs to NAND gate 114 and NAND gate 114. As previously mentioned, the overall function of virtual storage 20 is to divide user data into frames of a convenient size for storage on a back-end storage device such as disk drive 38. Considering this context,
Channel adapter 60 functions as an interface between virtual storage central processor (VCP) 70 and host processor software. A channel adapter 60 is attached to a host processor 30 having a standard channel interface 74 and a VCP 70.
connected to. That is, in the preferred embodiment
Corrected to be an extension of the Magnuson M80/40 system bus. Functionally, channel adapter 6
0 contains 5 parts. 2) data compression/decompression logic means 96; 3) channel adapter processor 78 and its storage (Z8000 unit); 4) direct storage. access logic and 5) system bus interface 76. The function of the primary channel adapter is to receive blocks of various lengths of data from the host processor user's standard channel protocol, to compress this data if possible, to assemble these blocks into frames, and to collect the filled frames ( control of the pages (referred to as pages) is sent by message means to the virtual storage system central processor 70. Therefore, 1
Frame is a virtual memory system central processor 7
0 will be the space having the size of one track in the virtual memory system storage device 38 that is allocated by the software included therein. Control of the frame is initially sent to channel adapter 60 via messages. The virtual storage system central processor 70 then controls the movement of filled frames, or pages, to back-end disk storage, thereby freeing the frames for reuse. In the preferred embodiment, the frame size is 19064 bytes. The reverse action is similarly performed during the reading operation. The second function of channel adapter 60 is to connect host processor 30 and virtual memory system processor 70.
The goal is to allow messages to flow between the software. This work is performed when the messages are not grouped and when the disk drive unit 38
It is executed in the same way except when it is not stored in .

As mentioned above, the concept of virtual volumes, or data files of unspecified length, is important in virtual storage. Such a virtual volume consists of at least one page of data. When such a volume is "opened," access to it is made by the virtual storage system central processor 70 and accessed by the channel adapter 60. Controlled by the ``stream block''. Any host processor 30 connected to the virtual storage device 20 can access any volume, and true multi-host processors can access the same file simultaneously. . This is not possible conventionally.

To write data to the opened volume, host processor 30 issues a "SET ID" command to channel adapter 60. The hardware logic of the channel adapter 60 detects the selection and connects the 8X300 channel sequencer 8.
Set 1 bit in the register monitored by 6. Channel sequencer 86 controls channel tags and provides channel addresses and instructions.
It is stored in a register available to the Z8000 microprocessor 80 and also sends an interrupt signal to the Z8000 microprocessor 80. Z8000 microprocessor 80 is 8X300 microcontroller 8
It responds to this interrupt by sending a command to 6. The 8X300 microcontroller 86 responds to instructions by issuing an interrupt reason. then
Z8000 microprocessor 80 commands 8X300 microcontroller 86 to enter an initial state and transmit data bytes from channel 32 to the channel address register and to the Z8000 microprocessor 80 instruction register. These four bytes contain the stream block ID. This stream block ID is translated by the Z8000 microprocessor 80 and treated as the stream block's system storage address. Z8000 microprocessor 80 writes stream block addresses and other control data to registers that control the system bus interface logic. Then the stream block
The virtual memory system is fetched from storage 68 and placed into Z8000 storage using the Magnuson M80/40 bus protocol. The Z8000 microprocessor 80 then writes the termination status into the channel status register and instructs the 8X300 microcontroller 86 unit to provide the termination status directly to the host processor 30. Virtual memory system storage 68 is thus ready to receive data from host processor 30.

Host processor 30 then chains write instructions through the initial state that repeat the ``SET ID'' operation as described above. The Z8000 microprocessor 80 then sets data transmission parameters, such as writing and compression, in the channel interface logic and instructs the 8X300 microcontroller 86 to begin data transmission. In this manner, the interface hardware controls byte-sequential data transmission from channel 32 to first-in/first-out buffer 94 which precedes data compression logic 96. The work buffers 94 and 100 are driven until they are full. Meanwhile, direct memory access (DMA) is provided by the Z8000 microprocessor 80.
transmission begins. The DMA logic then assembles the byte-sequential data 8 sent from Batcher into byte sets, obtains the VSS system bus 64, and sends the data to virtual memory system storage 68. The actions of the direct memory access logic include automatically incrementing addresses and counting bytes, thereby relieving the Z8000 microprocessor 80 of these tasks and thus
This allows the Z8000 microprocessor 80 to operate even faster. As a result of this action, the data is completely transmitted to the system. Then,
The 8X300 microcontroller 86 interrupts the Z8000 microprocessor 80 again, the Z8000 microprocessor 80 updates the stream block to indicate the current state, adds the header data to the stored block, and sends the 8X300 microprocessor 86 back to the 8X300 microprocessor 86. command to again indicate to host processor 30 that the operation is complete. Once sufficient host processor data has been sent to fill a frame in virtual memory system storage 68, control of this frame (page) is
Sent to VCP70.

As mentioned above, data is transmitted in frames. The operation of the Z8000 microprocessor 80 is therefore set to fill the frame. If the frame is filled before channel 32 signals the end of the data, the block continues with another frame. Since the next frame typically does not touch the first storage device of virtual storage system storage 68, it will be necessary to establish a second direct storage access. This is essentially an independent operation as described above. As will be apparent to those skilled in the art, system bus interface 76 is connected to data compression buffer 102 and Z8000 under direct storage control.
It handles virtual memory system storage 68 data transmissions directly from microprocessor 80, ie, data transmission operations and control operations. These operations may be interleaved as desired. The read operation is similar to the write operation as described above. In particular, in the preferred embodiment, the direction of travel through the data compression/decompression logic 96 is common to both modes to simplify design. The only difference is that data transmission proceeds in the opposite direction, as shown in FIG.

Numerous other advantages of the present invention will be apparent to those skilled in the art, although not specifically described herein. For example, diagnostic and error correction logic may be incorporated at numerous points throughout the channel adapter 40 described above for convenience and reliability of operation. Additionally, as those skilled in the art will appreciate, channel adapter 40 can be used to connect virtual storage 20, including a Magnuson M80 computer as virtual storage processor 70, and an IBM 370 CPU (particularly the aforementioned co-processor).
Although the design of channel adapter 40 is designed to interface with other virtual storage system central processors 70 and other It can be easily modified to work with a host processor 30.

[Brief explanation of drawings]

FIG. 1 is an overall diagram of a data processing storage system including a virtual storage system connected to a channel adapter according to the present invention, FIG. 2 is a block diagram of a channel adapter and a virtual storage processing device according to the present invention, and FIG. 3 4 is a detailed block diagram of a channel adapter according to the invention; FIG. 4 is a diagram showing the main data path through the channel adapter according to the invention of FIG.
Figure 5 is a diagram showing the flow of control signals flowing between the virtual storage data bus and the microprocessor which is the center of the channel adapter according to the present invention, and Figure 6 shows the flow of control signals flowing from the microprocessor to the sequencer. Figure 7 shows the flow of control signals flowing back and forth between the host computer and the microprocessor, and Figure 8 shows the flow of control signals flowing between the channel and the sequencer. FIG. 9 is a block diagram of hardware that may be used to perform data compression in a channel adapter according to the present invention.

Claims (1)

[Scope of Claims] 1. A channel adapter connected to a host processor and a virtual storage system including a long-term storage medium and a processor for allocating storage locations for data storage on the long-term storage medium, , the channel adapter is connected between the host processor and the processor in the virtual storage system to store data provided for storage by the host processor on the long-term storage medium. a channel adapter processor that divides the data into blocks of an appropriate size for processing, and a device that supplies the data in the appropriate block size to the processor in the virtual storage system. channel adapter. 2. Claim 1, wherein the channel adapter processor comprises a relatively low-speed intelligent processor and a relatively high-speed channel sequencer unit subordinate to the intelligent processor. Channel adapter as described in . 3. A patent characterized in that it comprises means for compressing said data by removing redundancy, and means for dividing said compressed data into blocks of appropriate size for storage on said long-term storage medium. The channel adapter according to claim 1. 4. The channel adapter of claim 1, wherein a plurality of channel adapters interconnect a plurality of host processors with the virtual storage system. 5. Claim 1, wherein the long-term storage medium is a plurality of magnetic disk devices, and the size of the block for the long-term storage medium is the size of one track of the magnetic disk device. Channel adapter as described in . 6. A channel adapter connected to a virtual storage system comprising a long-term storage medium for storing data received from a source in any format on the long-term storage medium, the channel adapter comprising: means for determining whether the data is to be stored on a medium; means for dividing said data into block sizes suitable for storage on said long-term storage medium; and means for receiving data from said source and responsive to said dividing by said means for dividing. and means for controlling the flow of data to the virtual storage system. 7. The channel adapter according to claim 6, further comprising means for compressing the data before dividing the data into appropriate block sizes for storage on the long-term storage medium. 8. The channel adapter of claim 6, wherein a plurality of said receiving means are provided for correlating a host processor and said virtual storage system. 9. Claim 6, wherein the long-term storage medium includes a plurality of magnetic disk drives, wherein the size of the block for the long-term storage medium is the size of one track of the magnetic disk drive. Channel adapter as described in . 10 Intervening between a virtual storage system and a host processor, dividing data received from the host processor into a format selected by the user, and transmitting the divided data within the virtual storage system. said channel adapter for presenting said virtual storage system in a format selected to be suitable for storage, said channel adapter comprising first and second processor means, said first processor means processing a host processor instruction and a virtual storage system; responsive to storage system instructions and controlling the operation of said second processor means, said second processor means directing said data flow through said channel adapter in response to instructions from said first processor means; Orientation: A channel adapter characterized in that said first processor means is relatively intelligent and said second processor means is relatively fast. 11. The channel adapter according to claim 10, further comprising means for compressing the data before dividing the data.