KR100386348B1 - A circuit for aligning logical sectors with physical sectors in a disk storage system - Google Patents

Abstract

A circuit for managing data conversion between a logical sector format and a physical sector format is disclosed. In the padding mode, this circuit generates a data sector in physical sector format having a physical length by adding a padding value to the data stream in a logical sector format having a logical length. In the extraction mode, this circuit extracts the data stream in logical sector format from the data stream in physical sector format.

Description

Padding data addition and extraction circuit {A CIRCUIT FOR ALIGNING LOGICAL SECTORS WITH PHYSICAL SECTORS IN A DISK STORAGE SYSTEM}

The present invention relates to a disk storage system, and more particularly to padding the logical sectors to align the boundaries of the logical sectors with the boundaries of the physical sectors. A circuit for appending and extracting data is provided.

In a typical disk storage system, data is organized into physical sectors, where each physical sector contains a predefined number of consecutive bytes. When data is written to or read from the disk drive, the amount of data to be transferred must be transmitted in units of physical sectors, and all data transfers must begin and end at the boundary of the physical sector. For example, if the physical sector consists of 514 bytes, the data transfer may consist of 514 bytes, 1028 bytes, 1542 bytes.

When a processor accesses a disk drive, for example when the processor writes a file, the processor probably does not need to operate on exactly one physical sector or an integer multiple of that sector. Instead, the processor probably needs an amount of data that is not, for example, 514 bytes, 1028 bytes, 1542 bytes, or the like.

In the situation of transferring data between a processor and a data storage system, the data manipulated by the processor is called a logical sector. As mentioned above, the boundaries of logical sectors typically do not coincide with the boundaries of physical sectors. Thus, data transfer often involves manipulating more data than is actually used by the processor.

Design goals for disk storage systems include maximizing recording density and throughput. The write density is the ratio of the memory occupied by the valid data to the total memory capacity of the disk storage system. Throughput is a measure of the overall throughput handled by the system for a particular time.

The following patents are representative prior art attempts to maximize recording density and throughput. In general, they address system or method aspects of organizing data on disk drives or handling misalignment of logical and physical sector boundaries.

US Patent No. 5,596,458 to Emo et al., Entitled "Variable Zone Layout For Information Storage Disk Drive," measures the performance characteristics of each read / write head for a disk having multiple disk surfaces. By this, a method and system for improving recording density are described. Zone boundaries are established for each disk surface based on performance characteristics and based on the frequency with which data is read and written for a particular zone. Zone boundaries on the surface of the disk may not necessarily be vertically aligned. The write density is improved by reducing the read / write frequency of the read / write head with lower performance characteristics than the predefined level.

US Pat. No. 5,671,439 to Klein et al., Entitled "Multi-Drive Virtual Mass Storage Device And Method Of Operating Same," describes a virtual mass storage organized into blocks that are allocated for different physical devices. Describe a virtual mass storage device. Physical devices operate in parallel to increase the total data rate of the virtual device.

U.S. Patent No. 5,765,201 to Manges et al., Entitled " Changing Page Size In Storage Media Of Computer System ", applies to a system in which data is stored in blocks or sectors defined by headers. Describe. Tables are used to define memory destinations and segments, and to assign virtual memory addresses to physical memory. Headers and tables can be changed without rewriting all data in sectors or pages of physical memory. Thus, the page size can also be changed to accommodate new system components.

U.S. Patent No. 5,802,584 to Kool et al., Entitled "Hardware Alignment In A Headerless Disk Drive Architecture," discloses a system for controlling data transfer to and from data sectors of a disk drive. Initiate. The system includes a disk controller that decodes an event control word and a counter that increments as the read / write head passes through the sectors on the disk. The counter indicates the position of the read / write head by indicating the data frame in which the head is located. An alignment processor scans the control word to find the control word corresponding to the data frame indicated by the counter. During the scan, the alignment processor also aligns the logical and physical sector counters indicated by the position of the read / write head. Thereafter, the disk controller uses the aligned values to begin decoding the control word and controlling the data transfer.

Murphy et al., US Pat. No. 5,813,025, entitled "System And Method For Providing Variable Sector-Format Operation To A Disk Access System," describes a pre-defined logical sector format and a variable physical sector format. Describes a system and method for handling I / O requests. When the read operation starts at the center of the physical sector, the data before the first logical sector is discarded, and user request data is stored in the user buffer. If the write operation is for a logical sector located in the center of the physical sector, the physical sector is read and modified in accordance with the write request for the logical sector and then written back to the disk as a complete physical sector. The buffer is preserved to hold data that is modified after being read before being written back to disk.

1 illustrates a relationship between a logical sector and a physical sector according to the prior art. The data stream on the disk drive is organized into physical sectors 1-128, which are 514 bytes each, which have logical sectors # 1, # 32, which are 2054 bytes each.

Logical sectors # 1 through # 32 are serial data streams written from a processor to a disk drive, i.e., without gaps or fillers between logical sectors. This is a technique used to improve the recording density, which is adversely affected by factors such as the presence of invalid or excess data between valid occurrences of data.

Note that four physical sectors are 2056 bytes in total, and four physical sectors are required to accommodate each 2054 byte logical sector. For example, logical sector # 1 is in physical sectors 1-4. Since four physical sectors of 2056 bytes in length are two bytes larger than a logical sector of 2054 bytes in length, logical sector # 1 ends and logical sector # 2 starts two bytes before the end of physical sector four. Logical sector # 2 then ends 4 bytes ahead of the end of physical sector 8. That is, logical sector # 2 starts at byte 512 of physical sector 4 and ends at byte 510 of physical sector 8. This two-byte difference accumulates so that logical sector # 32 ends 64 bytes (ie, 32 x 2 bytes) before the end boundary of physical sector 128.

When writing a data stream of 32 logical sectors to a disk drive, the processor must add 64 bytes of padding data to the end of logical sector # 32. When the write operation is finished, the disk drive issues an interrupt 105 to the processor. After receiving the interrupt 105, the processor sends another set of 32 logical sectors to the disk drive.

Minor differences in the relationship between logical and physical sectors become even more apparent when reading data from a disk drive. For example, assume that the processor wants to read logical sector # 2. The processor must determine the address of logical sector # 2 and recognize that it starts at byte 512 of physical sector 4 and ends at byte 510 of physical sector 8. Since the disk drive can only transfer data in units of physical sectors, and all data transfers must start and end at the boundary of the physical sector, the disk drive must read all data contained in the physical sectors 4-8. The processor must then discard the excess data. In particular, data of bytes 1 to 511 of physical sector 4 and data of bytes 513 and 514 of physical sector 8 should be discarded. One of the problems with a system such as that shown in FIG. 1 in which logical sectors are not aligned with physical sectors is that manipulation of excess data reduces the total throughput of the system.

Another conventional technique for dealing with inconsistencies in logical and physical sector boundaries is to pad each logical sector so that the length of the logical sector extends to the length of the physical sector. Although this operation is relatively simple, it is typically implemented in software, which implementation is accompanied by the results discussed later.

2 illustrates padding of logical sectors using software. The data streams on the disk drive are organized into physical sectors 1 through 128, which are each 514 bytes, which have logical sectors # 1 through # 32, which are each 2054 bytes. To accommodate logical sectors that are 2054 bytes each, four physical sectors of 2056 bytes in total are needed. For example, logical sector # 1 exists in physical sectors 1-4. Since physical sectors 1 through 4 that are 2056 bytes long are two bytes larger than logical sector # 1 that is 2054 bytes long, logical sector # 1 ends two bytes from the end of physical sector 4. These two bytes are filled with padding data 205 added by software at the end of logical sector # 1. The start of logical sector # 2 coincides with the start of physical sector 5.

The data stream shown in FIG. 2 is not a continuous data stream. During a write operation, the processor prepares 2054 bytes of data for logical sector # 1, adds two bytes of padding data 205, and sends this data to the disk drive. When the write operation ends, the disk drive issues an interrupt 210 to the processor. After receiving the interrupt 210, the processor sends logical sector # 2 to which the data 215 has been added to the disk drive. Upon completion of this write operation, the disk drive issues an interrupt 220 to the processor.

Interrupt handlers divert the processor from other tasks and often have significant overhead in preparing to handle the interrupt. As shown in FIG. 2, one of the problems with systems that add padding data to the end of logical sectors in software is that the disk drive interrupts the processor every time a write operation ends.

Accordingly, it is an object of the present invention to provide an improved system that adds padding data to a logical sector in order to align the end boundary of the logical sector with the end boundary of the physical sector when writing to the disk drive, but implements it in hardware.

Another object of the present invention is to provide an improved system for removing padding data from a physical sector to produce a logical sector when reading data from a hard drive, but implementing it in hardware.

It is yet another object of the present invention to provide an improved system that adds and extracts variable length padding data so that logical and physical sectors have variable lengths, but implements them in hardware.

According to the present invention, a predetermined circuit manages the conversion of data between a logical sector format and a physical sector format. In the padding mode, this circuit adds padding values to the logical data stream (the logical sector of the stream has a predetermined logical length) to create a physical data stream (the physical sector of the stream has a predetermined physical length). . In the extraction mode, this circuit extracts the logical data stream from the physical data stream.

In padding mode, this circuit includes a switch, a logical length counter, a physical length counter, and a controller. The switch has an input for receiving a logical data stream, an input for receiving a padding value, and an output for transmitting a physical data stream. The logical length counter counts bytes of the logical data stream, and the physical length counter counts bytes of the physical data stream. The controller controls the switch to select a logical data stream until the logical length is counted, and the switch to select a padding value until the physical length is counted.

In the extraction mode, the circuit includes a data latch, a logic length counter, and a physical length counter. The data latch has an input for receiving a physical data stream and an output for transmitting a logical data stream. The logical length counter counts bytes of the logical data stream, and the physical length counter counts bytes of the physical data stream. The controller causes the data latch to receive the physical data stream until the logical length is counted and disables the data latch until the physical length is counted.

1 illustrates a conventional mismatched logical and physical sector;

2 illustrates padding logical sectors in software according to the prior art;

3A and 3B illustrate padding logical sectors in hardware in accordance with the present invention;

4 is a schematic diagram of a logic circuit for adding and extracting padding values for a logical sector in accordance with the present invention;

5 illustrates the use of a counter by hardware to add padding values to logical sectors in accordance with the present invention;

6 illustrates the use of a counter by hardware to extract logical sectors from physical sectors in accordance with the present invention.

Explanation of symbols for the main parts of the drawings

404: logical sector length register 406: physical sector length register

408: sector register / counter 410: pad value register

412 logical length counter 414 physical length counter

426, 428, 430: 0 detector 424: control logic

448, 458, 452, 460: data latch 450: pad / data multiplexer

454 memory interface

The present invention discloses a circuit for adding / extracting padding data to / from a logical sector to align a logical sector's border with respect to a physical sector's border. First, the conceptual operation of the circuit is described in the discussion of FIGS. 3A and 3B. The circuit itself is then described in the discussion of FIGS. 4 to 6.

3A and 3B illustrate padding logical sectors in hardware in accordance with the present invention. 3A shows a general case and FIG. 3B shows an exemplary application of the invention.

In Fig. 3A, data streams on a disk drive are organized into physical sectors 1 to 32, which hold logical sectors 1 to 32 of data issued from the processor. Padding data is added at the end of each logical sector to align the beginning of the next logical sector with the beginning of the next physical sector. For example, padding data 310 is added to logical sector # 1 to align the beginning of logical sector # 2 with the beginning of physical sector # 2. Padding data is added to each logical sector by circuitry operatively located between the processor and the disk drive.

During the write operation, the processor prepares logical sectors 1 to 32 as a continuous data stream. The processor issues this data stream to the circuit described above. This circuit transfers the data stream to the disk drive and adds padding data to the end of each logical sector. The disk drive writes this data stream when it receives the data stream from the circuit. After writing all the data streams, the disk drive issues an interrupt 350 to the processor. Thereafter, the processor may issue another data stream for the circuit.

Since the present invention is implemented by circuitry rather than software of the processor, the problem of the prior art of handling multiple interrupts is somewhat solved, resulting in improved system throughput.

3B illustrates implementing the invention in a particular application. The data streams on the disk drive are organized into physical sectors 1 through 128, which are 514 bytes each, and include logical sectors # 1 through # 32, which are each 2054 bytes. Four physical sectors totaling 2056 bytes in length are required to accommodate logical sectors of 2054 bytes each. For example, logical sector # 1 exists in physical sectors 1-4. Since physical sectors 1 through 4 that are 2056 bytes long are two bytes larger than logical sector # 1 that is 2054 bytes long, logical sector # 1 ends two bytes from the end of physical sector 4. The circuit according to the present invention adds two bytes of padding data to the end of logical sector # 1 so that the start of logical sector # 2 coincides with the start of physical sector # 5. Similarly, logical sector # 2 ends two bytes ahead from the end of physical sector eight. The circuit adds two bytes of padding data to the end of logical sector # 2 so that the start of logical sector # 3 coincides with the start of physical sector # 9.

During the write operation, the processor prepares logical sectors # 1 to # 32 as a continuous data stream. The processor issues a data stream to this circuit. The circuit sends this data stream to the disk drive and adds two bytes of padding data to the end of each logical sector. The disk drive writes the data stream as it is received from the circuit. After writing all the data streams, the disk drive issues an interrupt 350a to the processor. The processor may then send another data stream to the circuit.

The read operation is best described by way of example. Suppose the processor wants to read logical sector # 2. The processor must determine the address of logical sector # 2 and recognize that this logical sector starts at physical sector 5 and ends at physical sector 8. Since the disk drive can only transfer data in units of physical sectors, and all data transfers must start and end at the boundary of the physical sector, the disk drive must read everything contained in physical sectors 4-8.

The disk drive sends physical sectors 4 through 8 to the circuit. The last two bytes of data in physical sector 8 contain padding data added by this circuit during writing. During a read operation, the circuit will discard this two bytes of padding data and send logical sector # 2 with no excess data to the processor.

4 is a schematic diagram of a logic circuit 400 for adding and extracting padding values for logical sectors in accordance with the present invention. The main system components of this circuit are control logic 424, logic length counter 412, physical length counter 414, pad / data multiplexer 450 and data latch 458. The logical sector length register 404, the physical sector length register 406, the sector register / counter 408, the pad value register 410, the zero detects 426, 428, 430, and the buffer 446 456, 462, data latches 448, 452, 460, and memory interface 454.

Processor interface bus 402 provides a path for signals from a processor (not shown) to logical sector length register 404, physical sector length register 406, sector register / counter 408, and pad value register 410. do. The output of the logical sector register 404 is connected to the input of the logical length counter 412. The output of the physical sector length register 406 is connected to the input of the physical length counter 414. The output of the pad value register 410 is connected to the input of the pad / data multiplexer 450.

The outputs of logical length counter 412, physical length counter 414, sector register / counter 408 are connected to the inputs of zero detects 426, 428, 430, respectively. The output of the zero detectors 426, 428, 430 is connected to the input of the control logic 424.

The data stream of the processor is received by the buffer 446 and is connected to the pad / data multiplexer 450 through the data latch 448. Data passes from the output of pad / data multiplexer 450 to data interface 454 through data latch 452, which sends data to a disk drive buffer (not shown).

The data stream from the disk drive buffer is received by the memory interface 454 and sent to the data latch 460. The output of data latch 460 is connected to data latch 458. The output of data latch 458 is connected to buffer 456, which sends data to the processor.

The control logic 424 generates several signals for controlling the operating circuit 400. An enable signal 416 makes the count function of the sector register / counter 408 operational. Load signal 418 controls logical length counter 412 and physical length counter 414 to load values from logical sector length register 404 and physical sector length register 406, respectively. Enable signals 420 and 422 render the counting functions of logical length counter 412 and physical length counter 414 respectively operable. The memory control signal 444 directs the operation of the memory interface 454. Enable signals 432, 434, 440, and 442 control data loading into data latches 458, 448, 460, and 452, respectively. Select signal 436 controls pad / data multiplexer 450 to input data from data latch 448 or pad value register 410. The control logic 424 also generates a data wait signal 431 that is transmitted through the buffer 411 to generate a data wait signal 409. The data validation signal 438 is transmitted through the buffer 462.

The circuit 400 has a padding mode and an extracting mode. In padding mode, this circuit 400 receives data streams of logical sectors (i.e., logical data streams) and adds padding data to the end of each logical sector to decode the data streams of physical sectors (i.e., physical data streams). Make. In the extraction mode, the circuit 400 receives the data stream of the physical sector, suppresses the padding data, and extracts the data stream of the logical sector. Details of the operation of each of these two modes are described below.

The function of some system components is related to the operation of the padding mode and also to the operation of the extraction mode. Before examining the operation of each mode, the behavior of these system components is discussed first.

The logical sector has a logical length of a predefined number of bytes, and the physical sector has a physical length of a predefined number of bytes. Logical length and physical length are programmable by the processor. Through the processor interface bus 402, the processor loads the logical length into the logical sector length register 404 and the physical length into the physical sector length register 406. The processor specifies the number of sectors to be transferred to / from the disk drive by loading the number of sectors into the sector register / counter 408. The processor also specifies a value for the padding data by loading the padding value into the pad value register 410.

In any mode of operation, in order to transfer each sector of data, control logic 424 controls logical length counter 412 to load the logical length from logical sector length register 404 and the physical length counter 414. Control to load the physical length from the physical sector length register 406. The control logic 424 makes the logic length counter 412, the physical length counter 414, and the sector register / counter 408 operational during data transfer. The logical length counter 412 decrements the coefficient by one each time one byte of data is transmitted, and reaches zero when the logical length is all counted. The physical length counter 414 decrements the coefficient by one each time one byte of data is transmitted, and reaches zero when the physical length is all counted. Similarly, the sector register / counter 408 decrements the coefficient by one each time data in each sector is transferred and reaches zero when all sectors have been transferred. The zero detectors 426, 428, 430 monitor the coefficients of the logical length counter 412, the physical length counter 414, and the sector register / counter 408, respectively. Notify the control logic 424 of the fact.

The control logic 424 manages the transmission of multiple sectors by indirectly monitoring the state of the physical length counter 414 and the sector register / counter 408 through their respective zero detectors 428, 430. When the physical length counter 414 reaches zero, one sector has been completely transmitted. In response, control logic 424 decrements the coefficient of sector register / counter 408 by one through enable signal 416. If the sector register / counter 408 has not yet been reduced to zero, more sectors have to be sent, and the load signal 418 allows the control logic 424 to transfer the logical length counter 412 from the logical length sector register 404. Reload and reload the physical length counter 414 from the physical sector register 406.

In padding mode, control logic 424 manages data wait signal 431 to control the transmission of the logical data stream from the processor. It is connected through a buffer 411 to generate a data wait signal 409. Initially, the data wait signal 431 is not set. Therefore, the processor is allowed to send the logical data stream to the buffer 446, and the data is latched in the data latch 448. The logical data stream is sent from the data latch 448 to the input of the pad / data multiplexer 450.

Control logic 424 indirectly monitors logical length counter 412 via zero detector 426 and selects a logical data stream from data latch 448 until logical length counter 412 becomes zero. The pad / data multiplexer 450 is controlled via the selection signal 436. Thereafter, the control logic 424 indirectly monitors the physical length counter 414 via the zero detector 428. Control logic 424 prohibits data transfer from the processor by issuing a data wait signal 431 and controlling pad / data multiplexer 450 via select signal 436 so that the pad / data multiplexer has a physical length. And select pad value from pad value register 410 until counter 414 reaches zero. The output of the pad / data multiplexer 450 is a physical data stream, that is, a data stream in which padding data is added to a logical sector, and the length of the logical sector and its padding data combined is also the length of the physical sector.

The physical data stream output of the pad / data multiplexer 450 is sent to the data latch 452 and then to the memory interface 454. Via the memory control signal 444, the control logic 424 instructs the memory interface 454 to send the physical data stream to the disk drive buffer.

In the extraction mode, the physical data stream is received from the disk drive buffer through the memory interface 454 and temporarily stored in the data latch 460. The physical data stream is then sent from data latch 460 to data latch 458.

The control logic 424 indirectly monitors the logic length counter 412 via the zero detector 426, and through the enable signal 432 through the enable signal 432 until the logic length counter 412 becomes zero. Data latch 458 is controlled to input data from. The control logic 424 then indirectly monitors the physical length counter 414 via the zero detector 428 and the data until the physical length counter 414 reaches zero via the selection signal 436. Make the latch 458 inoperable. The output of the data latch 458 is a logical data stream, that is, a data stream composed of logical sectors extracted from this physical sector in which the padding value held by the physical sector is suppressed.

The logical data stream output of the data latch 458 is sent to the processor through the buffer 456. Control logic 424 generates data valid signal 438 during the time that the output of data latch 458 transmits a valid logical data stream. The data valid signal 438 is connected through a buffer 462 and transmitted to the processor as a transmit data valid signal 461.

5 illustrates the use of a hardware counter to add padding values to logical sectors. This illustrates the case where a 2054 byte long logical sector is received from the processor and a 2056 byte long physical sector is transferred to the disk drive. The logical length counter (see 412 in FIG. 4) and the physical length counter (see 414 in FIG. 4) will each be zero (one count) for each byte of the data stream being transmitted. Counting down until In step 505, the logical length counter 412 goes to zero, indicating that one logical sector has been counted. The physical length counter 414 continues to count until step 515, where the counter's count is zero. Note that two bytes of padding data have been added to the data stream.

In step 520, the sector register / counter (see 408 in FIG. 4) decreases by one, and the logical length counter 412 and the physical length counter 414 are reloaded, and then subsequent sectors. Can be counted upside down again during transmission. Those skilled in the art will appreciate that the counter is loaded with a value less than one, which is actually less than the number of bytes to be counted since the counter finally decreases to a value of zero.

6 illustrates the use of a counter to extract logical sectors from physical sectors in hardware in accordance with the present invention. A 2056 byte long physical sector is received from the disk drive, and a 2054 byte long logical sector is sent to the processor. The logical length counter (see 412 in FIG. 4) and the physical length counter (see 414 in FIG. 4) are each zero, counting each byte of the data stream being transmitted as one (one count). Count upside down. The transmission data valid signal (see 461 of FIG. 4) is a logic "1" while valid data is being sent to the processor. In step 605, the logical length counter 412 reaches zero, indicating that one logical sector has been sent. In step 610, the transmit data valid signal 461 changes to a logic " 0 " while the padding value of the data stream is received from the disk drive. The physical length counter 414 continues counting backwards until step 615 where the value becomes zero.

In step 620, the sector register / counter (see 408 in FIG. 4) decreases by one, the logical length counter 412 and the physical length counter 414 are reloaded, and then the subsequent sectors. Can be counted upside down again during transmission. The transmission valid data signal 461 is once again changed to a logical " 1 " to indicate that valid data is to be transmitted.

It is to be understood that the foregoing description is only illustrative of the invention. Various substitutions or modifications may be made by those skilled in the art without departing from the invention. For example, data latches or buffers may be configured to alter the order of data transmitted through the circuit, and the timing relationship of various control signals may be modified. In addition, the data stream being transmitted may be a data unit other than bytes, and the data transmission line may be configured as a serial link or a parallel bus. Accordingly, the present invention is intended to embrace all such alterations, modifications and variations that fall within the scope of the appended claims.

Therefore, according to the present invention, padding data is added / extracted to the logical sector to align the boundary of the logical sector with the boundary of the physical sector, and implemented in hardware, thereby recording density and throughput. It will be possible to improve.

Claims (21)

Adding a padding value to the first data stream having a logical length, thereby providing a second data stream—operation request of the recording device on the recording device when the second data stream is recorded on the recording device. A circuit that occupies a determined physical length that fits and wherein the logical length and the physical length are measured in data units, A first input for receiving the first data stream, a second input for receiving the padding value, and an output for transmitting the second data stream, wherein either one of the first input and the second input A switch capable of controlling sending the output to the output; A logical length counter that counts the data units of the first data stream, the logical length counter having an output indicating when the logical length has been counted; A physical length counter that counts the data units of the second data stream, the physical length counter having an output indicating when the physical length has been counted; ④ in response to the output from the logical length counter and the physical length counter, controlling the switch to select the first data stream until the logical length is counted, and then when the physical length is counted A controller for controlling the switch to select the padding value until Padding value addition circuit. The method of claim 1, An input for receiving the second data stream from the output of the switch and an output for transmitting the second data stream, wherein the input for receiving the second data stream is enabled or disabled It further includes a data latch that can be controlled as a disable. Padding value addition circuit. The method of claim 1, And a sector counter for counting sectors of the second data stream, the sector counter having an output indicating when the sector is counted. Padding value addition circuit. The method of claim 1, And a logical length register holding a value indicating the logical length, wherein the logical length counter is loaded from the logical length register. Padding value addition circuit. The method of claim 1, And a physical length register for holding a value indicating the physical length, wherein the physical length counter is loaded from the physical length register. Padding value addition circuit. The method of claim 1, And a padding value register for holding the padding value, wherein the second input of the switch receives the padding value from the padding value register. Padding value addition circuit. The method of claim 1, The data unit is a byte Padding value addition circuit. A circuit for extracting a first data stream having a logical length, wherein the logical length and the physical length are measured in data units, from a second data stream having a predetermined physical length that meets an operation request of a recording apparatus. (1) has an input for receiving the second data stream and an output for transmitting the first data stream, the input for receiving the second data stream in an enabled or disabled state; Controllable data latches, A logical length counter that counts the data units of the first data stream, the logical length counter having an output indicating when the logical length has been counted; A physical length counter that counts the data units of the second data stream, the physical length counter having an output indicating when the physical length has been counted; In response to the output from the logical length counter and the physical length counter, controlling the data latch to make the input operable with receiving the second data stream until the logical length is counted; And a controller for controlling the data latch to render the input receiving the second data stream inoperable until the physical length is counted. Circuit for extracting a data stream having a logical length. The method of claim 8, And a sector counter for counting sectors of the second data stream, the sector counter having an output indicating when the sector is counted. Circuit for extracting a data stream having a logical length. The method of claim 8, And a logical length register holding a value indicating the logical length, wherein the logical length counter is loaded from the logical length register. Circuit for extracting a data stream having a logical length. The method of claim 8, And a physical length register for holding a value indicating the physical length, wherein the physical length counter is loaded from the physical length register. Circuit for extracting a data stream having a logical length. The method of claim 8, The controller provides an output indicating that the output of the data latch is transmitting the first data stream. Circuit for extracting a data stream having a logical length. The method of claim 8, The data unit is a byte Circuit for extracting a data stream having a logical length. Adding a padding value to the first data stream having a logical length to occupy a defined physical length on the recording device that meets the dynamic requirements of the recording device when recorded to the recording device. Circuitry capable of operating in a padding mode for generating a second data stream to perform, or in an extracting mode for extracting the first data stream from the second data stream—the logical length and the physical length Is measured in data units-- A first input for receiving the first data stream, a second input for receiving the padding value, and an output for transmitting the second data stream, wherein either one of the first input and the second input A switch capable of controlling sending the output to the output; (B) having an input for receiving the second data stream and an output for transmitting the first data stream, wherein the input for receiving the second data stream is enabled or disabled; A first data latch that can be controlled, A logical length counter that counts the data units of the first data stream, the logical length counter having an output indicating when the logical length has been counted; A physical length counter that counts the data units of the second data stream, the physical length counter having an output indicating when the physical length has been counted; A controller responsive to said output from said logical length counter and said physical length counter, The controller, In the padding mode, control the switch to select the first data stream until the logical length is counted, and then control the switch to select the padding value until the physical length is counted; , In the extraction mode, controlling the first data latch to enable the input receiving the second data stream until the logical length is counted, and then the physical length is counted. To control the first data latch to disable the input receiving the second data stream until Circuit. The method of claim 14, An input for receiving the second data stream from the output of the switch and an output for transmitting the second data stream, wherein the input for receiving the second data stream is enabled or disabled And further comprising a second data latch that can be controlled in a disabled state. Circuit. The method of claim 14, And a sector counter for counting sectors of the second data stream, the sector counter having an output indicating when the sector is counted. Circuit. The method of claim 14, And a logical length register holding a value indicating the logical length, wherein the logical length counter is loaded from the logical length register. Circuit. The method of claim 14, And a physical length register for holding a value indicating the physical length, wherein the physical length counter is loaded from the physical length register. Circuit. The method of claim 14, And a padding value register for holding the padding value, wherein the second input of the switch receives the padding value from the padding value register. Circuit. The method of claim 14, The controller provides an output indicating that the output of the first data latch is transmitting the first data stream. Circuit. The method of claim 14, The data unit is a byte Circuit.