JPH04299777A - Printed circuit board designing device - Google Patents

Abstract

PURPOSE:To generate an appropriate detour pattern corresponding to the shape of an equipment when wiring between pins of parts or through holes which can not keep enough clearance. CONSTITUTION:A detour processing part 5 is provided in a wiring processing part 2. This detour processing part 5 is provided with an obstacle detecting means to calculate a search area including a space between two designated points and to discover an objective obstacle to be detoured in this search area by calculating the distance, a detour point detecting means to calculate an offset line along the shape of the obstacle discovered by the obstacle detecting means and to calculate a detour point by calculating an intersection while keeping the clearance from the end point of the obstacle, a reform processing means to adjust the detour point when the plural obstacles exist, lock processing means to designate the angle of the line segment of the detour pattern and to generate the detour point so as to obtain the detour pattern based on this designated angle, and an on-grid processing means to move the detour point so as to load the detour point on a wiring lattice for each prescribed position.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board design device, and more particularly to a wiring detour function during interactive wiring of a printed circuit board design device.

0002

[Prior Art] In conventional systems, when wiring A to B between component pins or through holes C to D that do not maintain sufficient clearance between the pins, as shown in Figure 20, it is checked by a design routine check. , it is treated as a clearance error and wiring cannot be done.

0003

Problems to be Solved by the Invention When wiring is routed around this obstacle using conventional methods, the following problems occur.

(1) If sufficient clearance cannot be maintained, wiring is performed manually while taking the clearance into consideration. For example, as shown in FIG. 21, a plurality of bending points P1,
Input P2, P3, and P4 to create a detour pattern and detour around the obstacle. With this method, when component pin components are defined by arbitrarily shaped pads such as SMD components, the designer cannot judge how much gap should be maintained, and wiring work is difficult. Very difficult.

[0005] Furthermore, it is possible that mistakes may occur in wiring patterns that occur due to manual intervention. Therefore, it is necessary to check for mistakes and correct the mistakes later.

(2) Since SMD components have various pin spacings and dimensions, conventional regular grid (GRI)
The wiring method using D ON) cannot fully utilize the characteristics of SMD components.

(3) As pattern widths become finer and through holes become smaller in diameter, the number of parts and through holes increase, and a function that automatically bypasses obstacles such as component pins and through holes is required. has been done.

[0008] The present invention has been made with attention to these points, and its purpose is to provide wiring between component pins or through-holes where sufficient clearance cannot be maintained.
It is an object of the present invention to provide a printed circuit board design device capable of generating an appropriate detour pattern that matches the shape of a component.

[0009]

[Means for Solving the Problems] The present invention, which solves the above problems, obtains a search area that includes two specified points, and detects an obstacle to be detoured within this search area by distance calculation. means, a detour point detecting means for determining an offset line along the shape of the obstacle found by the obstacle detecting means, calculating an intersection point while maintaining clearance from an end point of the obstacle, and determining a detour point; a lock processing means that specifies an angle of a line segment of a detour pattern and generates a detour point so that the detour pattern is based on the specified angle; The present invention is characterized by comprising on-grid processing means for moving the detour points so that the detour points are placed on the wiring grid at each predetermined position.

0010

[Operation] In the present invention, an offset line is determined by the detour point detection means along the shape of the obstacle found by the obstacle detection means, and an intersection point is calculated while maintaining a clearance from the end point of the obstacle. A detour point is required. A detour pattern is created based on this detour point.

[0011] Furthermore, if a plurality of obstacles exist, the detour point is adjusted by the reform processing means. Furthermore, when the line segment angle of the detour pattern is specified, the lock processing means generates detour points so that the detour pattern is based on the specified angle. Then, when on-grid processing is designated, the on-grid processing means moves the detour point so that it is placed on the wiring grid at each predetermined position.

0012

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First, the features of the apparatus of this embodiment will be explained with reference to FIG. 3 and subsequent figures. The device of this embodiment is configured to automatically detour regardless of the shape of the elements constituting the component pin. That is, it corresponds to the various shapes shown in FIG. A closed figure with an arbitrary shape shown in Fig. 3(e) is treated as a rectangle.In addition, in order to realize a detour around multiple component pins and through holes, the closed figure shown in Fig. 4 is
There are various modes. These modes are: (DETOUR MODE): Selection mode for whether or not to perform detour processing. (OPTIMZ): Select whether to pass through the pins by dividing them equally depending on the clearance between the pins and the pattern width. Figure 5 (
5(a) shows the case of equal division processing with one pin between the pins and OPTIMS on, and FIG. 5(b) shows the case with OPTIMS off. Further, FIG. 5(c) shows the case of equal division processing with two pins and OPTIMS on, and FIG. 5(d) shows the case with OPTIMS off. (TYPE): When detouring around multiple obstacles, do you detour all at once (Fig. 6 (b)) or do you detour individually (Fig. 6
Select (a)). (PATN): Horizontal, vertical, 45° detour (
Figure 7 (a)) or a detour connecting the shortest distance (Figure 7 (b)
)) to choose.

[0014]The designer is configured to be able to specify the detour direction through dialogue with the apparatus of this embodiment. That is, as shown in FIG. 8, the detour direction can be determined by moving a rubber hand on the CRT screen. Furthermore, when a detour pattern is generated by the distance calculation method, it is gridless in principle, but it is also possible to place all of the detour pattern on a wiring grid if selected.

FIG. 1 is a block diagram showing one embodiment of the present invention. In this figure, the device of this embodiment has the following configuration. Note that the operation of each part will also be explained here.

Input device 1: Consists of a keyboard and a pointing device, and specifies a position.

Wiring processing device 2: Overall control of the entire operation of the interactive wiring processing device. It also has functions for performing various processes.

Control unit 3: Exchanges data with each unit and executes wiring processing.

Design routine checking unit 4: Checks whether wiring rules are violated between wiring figures.

Detour processing unit 5: This is a characteristic part of this embodiment, and creates a wiring detour pattern. Details are shown in Figure 2.

Memory 6: Wiring pattern data and detour data are stored.

CRT 7: The created wiring pattern is displayed as an image. Further, as shown in FIG. 2, the detour processing section 5 has the following configuration.

Obstacle detection unit 5a: Finds a rectangular search area (Fig. 9■) that includes the specified two points, and detects obstacles C, D, and E to be detoured within this search area ■ by distance calculation. find. This search area is L from the starting point A and ending point B.
It is a rectangle containing distant points. Here, L=(line width size)/2+(clearance value).

Detour point detection unit 5b: Determines the detour point P by calculating offsets and intersections, taking clearance into account.

In the round-shaped obstacle shown in FIG. 10(a),
L1 is obtained by offsetting the line segment AB to the position r (radius) + L ((line width size)/2 + (clearance value)). And tangents L2 and L3 to the circle with radius r+L
seek. After this, the intersections P1 to P4 between L1, L2, and L3 are determined.

In the square-shaped obstacle shown in FIG. 10(b),
Obtain L1 by offsetting the line segment AB to the position r+l. Then, tangents L2 and L3 that are moved by l from the end points P1' and P2' of the corners of the obstacle are determined. After this,
Find the intersections P1 to P4 between L1, L2, and L3.

FIG. 11 shows the case of a rectangular obstacle (SMD component pin) E. In this case, the side P1 ′P2
Find a line segment L1 offset by L (L=(line width size)/2+(clearance value)) from ''. and,
A tangent L2 moved by L from the vertex P1'P2',
Find L3. After this, the intersections P1 to P4 between L1, L2, and L3 are determined.

Renovation processing section 5c: Renovates a detour point when a plurality of obstacles are present. Note that the detour method differs depending on the above-mentioned (TYPE) designation.
In the case of [THROUGH], as shown in Fig. 12, if there are multiple obstacles G and H, the intersection point P is
1 to P4 and P1' to P4' to find a continuous detour pattern. However, as shown in FIG. 13(a), if an intersection occurs in the middle of the detour point, a line segment with a smaller detour width (L1 here) is extended to create a new intersection N1.
In search of this, we carry out renovation processing. On the other hand, [LUM
P], the maximum detour width is determined and a collective detour pattern is created (FIG. 6(b)).

Lock designation detour processing unit 5d: Creates a detour pattern by locking horizontally, vertically, and at an angle of 45°. This is shown in detail in FIG. That is, a perpendicular line (or parallel line) is generated from points A and B, and the points of intersection P1 and P2 with the tangent line L3 are determined. Lock processing is performed in the same way even if there are multiple obstacles.

On-grid processing unit 5e: performs processing to place the created detour pattern on the wiring grid. In this process, an offset is forcibly performed in a direction in which clearance is maintained based on the relationship between the center coordinates of the obstacle and each coordinate of the detour pattern.

The overall operation will be explained in detail below.

<Initial Settings> Select the [RULE] item on the menu switch shown in FIG. 4 to call up the wiring rule table from the memory 6. Next, each mode of the detour process (the above four types of modes) is selected and executed by moving the cursor. Thereby, the control unit 3 executes processing according to each mode.

<Wiring operation> When the start point and end point of the net to be additionally connected are specified by the input device 1, a rubber band R is displayed by the control unit 3 between the start point A, the end point B, and the cursor position on the CRT. (Figure 15). Next, a line segment Aa is created by sequentially inputting the bending points of the wiring route. Here, if a situation occurs where the clearance cannot be maintained due to an obstacle D on the way as shown in FIG. 16, the control section 3 generates a rubber band R and inquires of the designer about the detour direction. Here, the designer determines the detour direction by operating the rubber band R by moving the cursor.

When a detour direction is specified by the designer via the input device 1, the detour processing section 5 generates a detour pattern that maintains the clearance (FIG. 17). At this time, if grid on is selected on the screen described in FIG. 4, on-grid processing is executed, and it is possible to place all the coordinates of the line segments created by the detour processing on the wiring grid. After one detour process is completed, the detour process is continuously executed even if the next obstacle is present.

Finally, by instructing the position of the end point using the input device 1 or by pressing the [OPC] key, the control unit 3 creates the final line segment. This completes the wiring work between the pin pairs (FIG. 18). Also, if you want to cancel the detour pattern created by this detour process during wiring, press the [REJECT] key, and the control unit 3 will delete the detour pattern all at once.
The display on the CRT returns to the previous point.

For the detour pattern created by the above processing, the design rule check section 4 executes a design rule check for each line segment with respect to wiring patterns of other nets, component pins, and through holes. Therefore, FIG.
If a clearance error occurs, as in C.
The RT is notified of the occurrence of a clearance error in real time.

As explained above, according to this embodiment,
Even when passing through areas where it is difficult to maintain clearance, which would conventionally require manual intervention, it is possible to maintain clearance and automatically generate a detour pattern. Therefore, it leads to improved reliability in terms of clearance checking and improved operability in terms of work.

In particular, in SMD components, the pad shapes of component pins are configured in various types, so it is extremely difficult to perform manual work while constantly considering the clearance value between component pins and wiring patterns. However, in this embodiment, it is possible to generate a detour pattern with any pattern, and the characteristics of SMD components can be fully utilized.

Furthermore, by providing modes such as batch detour, lock, and OPTIMS, it is also possible to create a detour pattern that is extremely close to the one designed manually.

[0040]

Effects of the Invention As described in detail above, according to the present invention, when wiring between component pins or through holes where sufficient clearance cannot be maintained, an appropriate detour pattern suitable for the shape of the component can be established. It is possible to provide a printed circuit board design device capable of generating.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a configuration diagram showing the configuration of essential parts of an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing shapes that can be handled by the apparatus according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram showing an example of the position of a mode setting screen according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 6 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 7 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 8 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 9 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 10 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 11 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 12 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 13 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 14 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 15 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 16 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 17 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 18 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 19 is an explanatory diagram showing the operating state of an embodiment of the present invention.

FIG. 20 is an explanatory diagram showing the operating state of the conventional device.

FIG. 21 is an explanatory diagram showing the operating state of a conventional device.

[Explanation of symbols]

1 Input device 2 Wiring processing section 3 Control section 4 Design rule checking department 5 Detour processing section 6 Memory 7 CRT

Claims (1)

[Claims] Claim 1: Obstacle detection means for determining a search area including between two designated points and finding an obstacle to be detoured within this search area by distance calculation; and an obstacle detected by the obstacle detection means. a detour point detection means that calculates an offset line along the shape of the object, maintains a clearance from the end point of the obstacle, calculates the intersection, and calculates the detour point; and a reform processing means that adjusts the detour point when there are multiple obstacles. and a locking means for specifying the angle of the line segment of the detour pattern and generating detour points so that the detour pattern is based on the specified angle, and a locking means for generating detour points so that the detour points are placed on the wiring grid at each predetermined position. and on-grid processing means for moving a detour point.