JP2819664B2 - Area pattern automatic generation processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Using a computer-aided design device (hereinafter referred to as a CAD device),
Regarding an area pattern automatic generation processing method for automatically generating a large area area pattern of a power supply and a ground on a printed circuit board, the object of the present invention is to provide an area pattern automatic generation processing method capable of automatically generating an area pattern with little effort. When a component pin is specified and an area pattern is generated,
The region pin automatic generation processing means provided in the CAD device extracts the already arranged component pins, vias, and lines of the same net as the specified component pin, and extracts the extracted component pins, vias, and lines of the net. In order to avoid intersecting with the wiring prohibited area and other nets, wiring is performed in the X and Y directions, the wiring is traced in a specific rotation direction, and the distance between the wiring area and the wiring prohibited area of the printed circuit board is calculated. Boundary coordinates are determined by determining the boundary coordinates, determining the distance to the wiring of the adjacent other nets, and dividing according to the ratio of the degree of necessity to widen the area pattern of each net. A polygon is formed based on the boundary coordinates, and each area pattern is generated.

[Industrial applications]

The present invention relates to an improvement in an area pattern automatic generation processing method for automatically generating a wide area area pattern of a power supply and a ground on a printed circuit board using a CAD device.

In recent years, many components have been mounted on a printed circuit board, and the power supply net for passing a large current needs to have a large area pattern.The ground of the power supply for passing a large current is different from the ground of other circuits. It is necessary to use a net, and each of them must be a wide area pattern, and the net design of the power supply and the ground has become complicated.

The outline of the CAD device is as shown in Fig. 5,
A processor 10, a display device 11 for displaying graphics, etc., a keyboard 12, for inputting data, etc., a tablet 13, for inputting graphics coordinates, etc., a RAM 14, a ROM 15 for storing programs and the like, an external storage device 16, and a display device 11. It consists of a stylus pen 17 for designating the displayed figure.

The data file of the external storage device 16 includes circuit diagram data such as connection of component pins, which ground the component pins are connected to, and wiring condition data such as a ratio of necessity to increase the area of each net. , Design standard data such as clearance between nets, line size, etc., board data such as wiring prohibited area and wiring area, component data such as number of component pins, shape data of components, boards, etc., component pins, vias and lines Of the existing design.

[Conventional technology]

FIG. 6 is an explanatory diagram of a conventional area pattern generation processing method.

In a conventional CAD device, for example, in order to generate the area patterns 20 and 21 shown in FIG. 6, the tablet 13 shown in FIG.
In the above, manually set the wiring prohibited area, wiring possible area,
Considering the clearance, the ratio of the degree of necessity to increase the area size of each net, etc., there is a method of specifying the angles of the area patterns 20 and 21 and the corner points of the other nets indicated by the squares for punching. It takes a lot of time to specify many points.

Considering the ratio of the degree of necessity to widen the area of the wiring prohibited area, the wiring area, the clearance, and the area of each net on the tablet 13, and inputting the corner points of the area patterns 20 and 21, the area pattern is obtained. Among them, there is an area pattern automatic generation processing method in which other nets are automatically punched.

[Problems to be solved by the invention]

However, even in the conventional area pattern automatic generation processing method, it is necessary to input the corner points of the area pattern in consideration of the routing prohibited area, the routable area, the clear run, the ratio of the necessity to increase the area size of each net, and the like. However, there is a problem that the input operation is troublesome.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an area pattern automatic generation processing method capable of easily automatically generating a plurality of area patterns existing on the same printed circuit board.

[Means for solving the problem]

 FIG. 1 is a diagram illustrating the principle of the present invention.

When a wide area pattern of power supply and ground is generated on a printed circuit board using a CAD device, a component pin is designated and a region pattern generation is instructed. As shown in FIG. The area pattern automatic generation processing means 1 extracts already arranged component pins, vias, and lines of the same net as the specified component pin, and extracts the extracted component pins, vias, and lines of the net to the wiring prohibited area and Wire in the X and Y directions so as not to cross other nets, trace the wiring in a specific rotation direction, determine the distance to the routable area or the wiring prohibited area of the printed circuit board and determine the boundary coordinates Further, the distance between adjacent wirings of other nets is determined, and the boundary coordinates are determined by classifying the distances according to the ratio of the degree of necessity of widening the area pattern of each net, and the boundary coordinates are determined based on the determined boundary coordinates. The polygon formed, so as to generate each region pattern.

[Action]

According to the present invention, when a component pin is specified and an area pattern generation is instructed, the area pattern automatic generation processing means 1 extracts a component pin, a via, and a line already arranged in the same net as the specified component pin, The extracted component pins, vias, and lines of the net are lined in the X and Y directions so as not to intersect with the wiring prohibited area and other nets.
Wiring method using T-branch, one-stroke wiring method using line segment search method, etc. If it is not possible to simply wire it, it is assumed that there is no route once, and another route is found and wired Line at.

Then, the wiring is traced in a specific rotation direction, the distance to the wiring-possible area or the wiring-prohibited area of the printed circuit board is determined to determine the boundary coordinates, and the distance to the wiring of another adjacent net is determined. Boundary coordinates are determined by partitioning according to the ratio of the necessity of increasing the size of the area pattern for each net, and a polygon is formed based on the determined boundary coordinates to generate each area pattern.

That is, if a component pin is specified and an instruction to generate an area pattern is issued, a plurality of area patterns existing on the same printed circuit board are automatically generated, so that it is possible to reduce labor compared to the related art.

〔Example〕

FIG. 2 is a flowchart of an area pattern generation processing program according to the embodiment of the present invention, FIG. 3 is a diagram showing an area pattern generation processing process of the embodiment of the present invention, and FIG. FIG. 4 is an explanatory diagram for obtaining a boundary by combining in the case of: 1.

The program shown in FIG. 2 is an R program of the CAD device shown in FIG.
When stored in the OM 15 and instructed by the keyboard 12 to generate an area pattern, the processor 10 reads it out and generates an area pattern.

 This will be described with reference to FIG.

In step 1, from the data file of the external storage device 16, the circuit diagram data such as the connection of the component pins, the ground to which the component pins are connected, the ratio of the necessity to increase the area of each net, and the like are obtained. Wiring condition data, clearance between nets, design reference data such as line size, board data such as wiring prohibited area and wiring area, component data such as the number of component pins, shape data of components, boards, etc. Via
Load the already designed data of the line.

In step 2, the operator designates a component pin and instructs generation of an area pattern. [Of course, it is also possible to designate component pins of a plurality of area patterns (nets). Good, but at this stage, they may not be placed, so the component pins are specified. ].

Then, in step 3, component pins, vias, and lines that have already been placed on the same net as the specified component pin are extracted based on the read data, and in step 4, the component pin coordinates of the same net are extracted in the X direction, Wire (net element) with a line in the Y direction, and proceed to step 5.

If there is a via in step 5, wiring is performed on the wired net element in step 6, and the process proceeds to step 7. If there is no via in step 5, the process proceeds to step 7.

If there is a line in step 7, wiring is performed on the wired net element in step 8, and the process proceeds to step 9, and if there is no line in step 7, the process proceeds to step 9.

In step 9, until wiring of all specified nets is completed,
The operation from step 3 to step 8 is performed, and the process proceeds to step 10.

Note that the above wiring is a line in the X and Y directions so as not to intersect with the wiring prohibited area and other nets, using the Lee's maze method, the line segment search method, etc., and using the T-branch and single-stroke wiring method. If the route cannot be simply routed, it is determined that the route has not been created once, and another route is found and wired.

The state up to this point will be described with reference to FIG. 3. As shown in FIG. 3, the component pins, vias, and lines of the net A are scattered as indicated by a circle, and the component pins, vias, and lines of the net B are X.
If it is scattered as indicated by the mark, wiring is performed for each net as shown in FIG.

In step 10, it is checked whether all the component pins, vias, and lines of the net are connected. Then, the process proceeds to step 11, and a search is made, for example, counterclockwise along the wiring tree. The horizontal and vertical distances to the routable area, the wiring prohibited area, and the other net element (wiring tree) are obtained, and the process proceeds to step S13.

In step 13, when the distance from the other net element is determined,
Proceeding to step 14, the line segment is divided by the ratio of the degree of necessity to increase the size of the area pattern as a boundary, and the processing proceeds to step 16.

In step 13, when the distances to the routable area and the forbidden area are obtained instead of the other net elements, the process proceeds to step 15, where the necessary clearance is subtracted to be a boundary, and step 16 is performed.
Proceed to.

The state up to this point will be described with reference to FIG.
For example, in the case of the net A, it turns to the left according to the wiring tree of the net A, and the horizontal and vertical distances are obtained. A part of the distance is shown in this case. This is the case where the distance is obtained.

If the ratio of the degree of necessity to increase the width of the net A and the net B in this case is 1: 1, the point indicated by the black point becomes a boundary, and the boundary with the wirable area also becomes the point indicated by the black point. .

Next, in step 16, the horizontal and vertical boundaries are synthesized,
Proceed to step 17.

This synthesizing method will be described with reference to FIG. 4 taking as an example a case where the ratio of the degree of necessity to increase the area with other nets is 1: 1.

Assuming that the horizontal division points are as indicated by, and the vertical division points are as indicated by, then combining these results as indicated by.

This is because, as shown in A, the area where both the horizontal and vertical line segments are in contact with the wiring tree under search is the area of the wiring tree under search, and as shown in C, the wiring tree under search using only vertical line segments. Is the area of the wiring tree under search, and as shown in B, if there is only a horizontal line segment and does not touch any of the wiring trees, 1/2 is the area of the wiring tree under search, and D As shown in (1), when there is only a vertical line segment and is in contact with the wiring tree of another net, a boundary is set as an area of the wiring tree of another net.

In this case, in the case of FIG. 3, the boundary becomes as shown by.

In step 17, steps 11 to 16 are performed until returning to the search point, and the process proceeds to step 18, and steps 10 to 17 are performed until the designated net number is completely completed.
Go to 19.

Step 19 corrects the boundary smoothly, and step 20
In step 20, punching processing of another net is performed for each area, and the process is completed.

The state up to this point will be described with reference to FIG. 3. As shown in FIG. 3, the boundary is corrected smoothly, and as shown in FIG. 3, another net in the area is punched out for each area, and a clearance is provided to generate an area pattern.

If an instruction is given to generate an area pattern of a predetermined width based on the wiring tree, such an area pattern can be automatically generated.

In other words, the region pattern can be automatically generated only by the operator designating the component pins of the region pattern to be generated.
An area pattern can be generated without any hassle.

〔The invention's effect〕

According to the present invention as described in detail above,
By simply designating the component pins of the area pattern to be generated, a plurality of area patterns existing on the same printed circuit board can be automatically generated, so that the area pattern can be generated without any trouble.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a principle diagram of the present invention, FIG. 2 is a flowchart of an area pattern generation processing program of an embodiment of the present invention, and FIG. 3 is an area pattern generation process of an embodiment of the present invention. FIG. 4 is an explanatory view of obtaining a boundary by combining in the case of a division ratio of 1: 1 according to the embodiment of the present invention. FIG. 5 is a schematic view of an example of a CAD apparatus. FIG. 6 is a conventional example. FIG. 6 is an explanatory diagram of an area pattern generation processing method of FIG. In the figure, 1 is an area pattern automatic generation processing means, 10 is a processor,
11 is a display device, 12 is a keyboard, 13 is a tablet, 14 is
RAM, 15 is a ROM, 16 is an external storage device, and 17 is a stylus pen.

Claims (1)

(57) [Claims] When generating a plurality of region patterns having a large area, such as a power supply and a ground, existing on a printed circuit board using a computer-aided design device, component pins of the same net connected to the respective region patterns are generated. When an area pattern is generated and specified, an area pattern automatic generation processing means (1) provided in the computer aided design apparatus
The component pins, vias, and lines that are already arranged in the same net as the specified component pin are extracted, and the extracted component pins, vias, and lines of the net are not crossed with the wiring prohibited area and other nets. Wiring is performed in lines in the X and Y directions, the wiring is traced in a specific rotation direction, the distance to the wiring-possible area or the wiring-prohibited area of the printed circuit board is determined, and the boundary coordinates are determined. Determine the distance from the wiring, determine the boundary coordinates by dividing according to the ratio of the degree of necessity to widen the area pattern of both nets, determine the boundary coordinates, form a polygon based on the determined boundary coordinates, An area pattern automatic generation processing method, wherein each area pattern is generated.