JPH04298119A - Phase synchronizing signal generating circuit - Google Patents

Abstract

PURPOSE:To realize the phase synchronizing signal generating circuit generating a clock signal phase locked with an external trigger signal simply and stably even when a Vp-p voltage of a triangle wave is fluctuated. CONSTITUTION:The circuit is the phase synchronizing signal generating circuit generating a clock signal phase locked with an external trigger signal and featured to be provided with peak hold means 119-121 holding a peak voltage of a phase measurement signal whose frequency is equal to a frequency of the clock signal, a reference voltage generating means generating plural reference voltages V1-V4 based on a holding peak voltage and a phase control means controlling a phase of the clock signal based on the phase data obtained by the comparison between the phase measurement signal and the plural reference voltages. The phase measurement signal is featured to be a triangle wave signal or a sawtooth wave signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-synchronized signal generating circuit that generates a clock signal that is phase-synchronized with an external trigger signal.

0002

[Prior Art] Conventionally, this type of phase synchronization signal generation circuit measures the phase by comparing a triangular wave signal with a plurality of reference voltages using a level comparator, and outputs a clock signal based on the measured phase data. A method of controlling the phase of the signal is used. FIG. 7 shows an example of the configuration of a conventional phase synchronization signal generation circuit of this type.

A reference oscillator (X'
tal generator; O. ) 114, a VCO 731 that generates a triangular wave signal and a square wave signal, and a phase comparator (PD) 733 that compares the phase of each output signal. generated. This triangular wave signal is input to the + side terminals of the level comparators 115, 116, 117, 118, and the reference voltages V1, V2 are input to the - side terminals.
, V3 and V4. Here, when the external trigger signal K is input, the comparison result is latched into the phase measurement data storage circuit 132 as phase data. Then, a set control circuit 128, a reset control circuit 129, an SR flip-flop (F/F) 13
0, clear control circuit 131 generates a synchronous clock signal based on the phase data latched in phase measurement data storage circuit 132.

0004

[Problems to be Solved by the Invention] However, in the above conventional example, the reference voltages V1, V2, V3, V4
is constant, so the peak-to-peak voltage (Vp-p) of the triangular wave signal must be constant in order to accurately measure the phase. For this reason, X'tal generator 1
14, VCO 731, phase comparator 733, etc., which require the use of complicated circuit elements, leading to an increase in cost due to an increase in the chip area of the IC. Furthermore, Vp-p due to bandgap voltage fluctuation due to temperature
It also had the disadvantage of unavoidable changes in

The present invention has been made in view of the above-mentioned problems, and provides a phase clock signal that stably and simply generates a clock signal whose phase is synchronized with an external trigger signal even if the Vp-p voltage of the triangular wave fluctuates. The purpose of the present invention is to provide a synchronization signal generation circuit.

[0006]

Means for Solving the Problems In order to achieve the above object, the phase synchronized signal generating circuit of the present invention is a phase synchronized signal generating circuit that generates a clock signal phase synchronized with an external trigger signal, and a peak hold means for holding a peak voltage of a phase measurement signal having a frequency equal to that of the signal; and based on the held peak voltage,
a reference voltage generation means for generating a plurality of reference voltages; and a phase control means for controlling the phase of the clock signal based on phase data obtained by comparing the phase measurement signal with the plurality of reference voltages. Equipped with. Here, the phase measurement signal is a triangular wave signal or a sawtooth wave signal.

In the phase synchronization signal generation circuit configured as described above, the peak voltage of the phase measurement signal is held and a reference voltage is generated based on this peak voltage, thereby generating the phase measurement signal voltage. It is possible to stably perform phase synchronization even with fluctuations in , and at the same time, it is possible to simplify the configuration of the phase synchronization signal generation circuit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of a phase synchronization signal generation circuit according to this embodiment. The operation of this embodiment will be explained below with reference to FIG.

The switch 127 connects the X'tal generator 11
It is turned on/off by the clock signal output from 4. When switch 127 is off, capacitor 113 is charged by constant current source 111, and the voltage across it increases with time. On the other hand, when the switch 127 is on, the electric charge stored in the capacitor 113 is discharged by the constant current source 112, and the voltage across the capacitor 113 decreases with time. Here, if the current value of the constant current source 112 is twice the current value of the constant current source 111, then the capacitor 1
13, a triangular wave whose rising and falling slopes are equal as shown in (3) in FIG. 3 is obtained.

This triangular wave voltage is input to the buffer 119, and the buffer 119, the diode 120, and the capacitor 1
21, the peak voltage of the triangular wave is held. The held voltage is passed through the buffer 132 to the resistors 122, 123, 12.
4,125,126, slice level V
1, V2, V3, and V4 are input to the negative input terminals of level comparators 115, 116, 117, and 118, respectively. A triangular wave signal from the capacitor 113 is input to the positive input terminals of these level comparators 115, 116, 117, and 118.
Triangular wave voltage and reference voltage levels V1, V2, V3,
A comparison with V4 is made.

Level comparators 115, 116, 11
7,118 output pulse signals C1, C2, C3,
C4 is input to the phase measurement data storage circuit 132. This phase measurement data storage circuit 132 includes
A clock signal (C0) from a generator 114 is also input, and these input signals are latched by an external trigger signal applied to input terminal K.

Here, the data obtained by latching the clock signal of the X'tal generator 114 is D0, and the output pulse signal C
1 to C4 are latched to D1 to D, respectively.
4. Then, the phase measurement data storage circuit 132 stores the phase range Z1 of the external trigger signal for the triangular wave signal.
-Z8 (see FIG. 3), latch output data (hereinafter referred to as phase data) as shown in FIG. 4 is obtained, and this phase data is input to the set control circuit 128 and the reset control circuit 129.

The set control circuit 128 and the reset control circuit 129 control phase data D1 to D4.
, level comparator output pulse signals C1 to C4
and the square wave clock signal C0 (D0) from the X'tal generator 114, the input signal to the set terminal and the input signal to the reset terminal of the RS flip-flop (F/F) 130 are respectively generated. The output signal of the RS flip-flop (F/F) 130 becomes the desired synchronous clock signal.

FIG. 2 shows the set control circuit 128,
2 is a circuit diagram showing the configuration of a reset control circuit 129, an RS flip-flop (F/F) 130, and a clear control circuit 131. FIG. The operation of these circuits will be described below with reference to FIG.

In the figure, a circuit consisting of EXNOR128a to 128d and a 5-input AND128e is added to the set control circuit 128 in FIG.
129d and a 5-input AND 129e is connected to the reset control circuit 129.
A circuit composed of 1a and 131b corresponds to the clear control circuit 131. OR201a, NOR20
1h, NAND201b~201e, 4 input AND20
1f, 4-input NOR 201g is a polarity control circuit 201, which is not shown in FIG.

Here, when the phase data D0 to D4 and the output pulse signals C0 to C4 (C0 is the output of the X'tal generator 114) match, the SR flip-flop 130 is set, and C0 to C4 are set to If the SR flip-flop 130 is reset at the reset timing shown in the column, a synchronous square wave clock with a duty of 50% can be obtained. The reset data C0 to C4 at this time is shown in Figure 4.
As can be seen from the figure, the values are the inversions of D0 to D4.

That is, the set control circuit 128 and the polarity control circuit 201 in FIG. 2 control the output pulse signals C0 to C4 and the phase data D0 to D4.
The circuit is configured to output a high level when the two match. Further, the reset control circuit 129 and the polarity control circuit 201 output pulse signals C0 to C4.
The circuit has a circuit configuration that outputs a high level when the phase data D0 to D4 have an inverted relationship with each other. In addition, the gate 201f in the polarity control circuit 201
, 201g, and 201h is designed to not take into account the clock signal C0 and phase data D0, which are undefined data, when the external trigger signal is input at the phase range Z1 or Z5 shown in FIG. It is something.

According to the above configuration, (4) in FIG.
A synchronous clock output waveform as shown in (11) is obtained. (4) to (11) in FIG. 3 show the output synchronous clock signals when the external trigger signals are input at the time points in the phase range Z1 to Z8, respectively.

By the way, the Q output of the D/F/F 131a in the clear control circuit 131 in FIG. 2 becomes high level as soon as the external trigger signal is input, and the RSF
/F Clear 130. Clearing is canceled at the first reset pulse (
This is when the output of the 5-input AND 129e) is output. Therefore, the output synchronous clock is forced to a low level from the time the external trigger signal is input until the reset pulse is output. Clear control circuit 1 like this
By providing 31, it becomes possible to easily identify the previous synchronized clock signals indicated by diagonal lines in (4) to (11) of FIG.

[0020] In the above embodiment, an example of the configuration was explained in which the reference voltage is generated by holding only the maximum value of the triangular wave voltage, but a configuration in which the minimum value of the triangular wave voltage is held or the maximum and minimum values are simultaneously held A configuration is also possible.

FIG. 5 is a diagram showing an example of a configuration in which a reference voltage is generated by holding both the maximum value and the minimum value of the triangular wave voltage. In FIG. 5, the same reference numerals are given to the same components as in FIG. 1, and redundant explanation here will be omitted.

In the figure, 501 and 504 are buffers, 502
is a diode, and 502 and 503 are capacitors. Here, the buffer 501, the diode 502, and the capacitor 503 constitute a peak hold circuit, and the capacitor 1
The minimum value of the triangular wave of the voltage at both ends of 13 is held. The minimum value of this triangular wave passes through the buffer 504 and becomes the terminal voltage of the resistor 126.

According to such a configuration, not only the maximum value but also the minimum value can be held and the slice level is determined based on this, so even if the Vp-p of the triangular wave changes significantly, the ( As shown in 2) and (3), the slice levels V1, V2, V3, and V4 are Vp-p.
controlled to be adaptive.

In the above embodiment, the phase synchronization signal generation circuit is constructed using hardware, but this embodiment can also be constructed using software using a program. When the phase synchronization signal generation circuit described above is used, the peak voltage of the phase measurement signal is held and the reference voltage is generated based on this peak voltage, so it is stable even against fluctuations in the phase measurement signal voltage. It is possible to perform phase synchronization, and at the same time, it is possible to simplify the configuration of the phase measurement signal generator.

[0025]

According to the present invention, it is possible to provide a phase synchronization signal generation circuit that stably and simply generates a clock signal phase-synchronized with an external trigger signal even if the Vp-p voltage of the triangular wave fluctuates.

[Brief explanation of drawings]

[Figure 1-1]

FIG. 1-2 is a diagram showing the configuration of a phase synchronization signal generation circuit of this embodiment.

FIG. 2 is a circuit diagram showing the configurations of a set control circuit, a reset control circuit, an RS flip-flop, and a clear control circuit in this embodiment.

FIG. 3 is a timing chart showing the operation of this embodiment.

FIG. 4 is a diagram showing the relationship between phase measurement data and reset timing.

[Figure 5-1]

FIG. 5-2 is a circuit diagram showing another configuration example of the phase synchronization signal generation circuit of this embodiment.

FIG. 6 is a diagram showing the operation of the embodiment of FIG. 5;

FIG. 7 is a circuit diagram showing the configuration of a conventional phase synchronization signal generation circuit.

[Explanation of symbols]

111, 112...constant current source, 113...capacitor, 11
4...X'tal generation circuit, 115, 116, 117, 1
18... Level comparator, 119... Buffer, 120
...Diode, 121...Capacitor, 122, 123,
124, 125, 126...Resistance, 127...Switch, 1
28...Cassette control circuit, 129...Reset control circuit, 130...RS flip-flop, 13
DESCRIPTION OF SYMBOLS 1... Clear control circuit, 132... Phase measurement data storage circuit, 501... Buffer, 502... Diode, 5
03...Capacitor, 504...Buffer

Claims (2)

[Claims] 1. A phase synchronization signal generation circuit that generates a clock signal phase-synchronized with an external trigger signal, comprising: a peak hold means for holding a peak voltage of a phase measurement signal having a frequency equal to that of the clock signal; a reference voltage generating means that generates a plurality of reference voltages based on the peak voltages detected; 1. A phase synchronization signal generation circuit comprising: phase control means for controlling the phase of a signal. 2. The phase synchronization signal generation circuit according to claim 1, wherein the phase measurement signal is a triangular wave signal or a sawtooth wave signal.