JPH04298044A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a structure for decreasing series collector resistance rc without increasing the number of masks. CONSTITUTION:A base region 16 is formed at the surface of an isolated region 15, and it is covered with an oxide film having an opening for emitter diffusion. A collector contact region is formed by selective etching using a solution such as KOH having a dependency on impurity concentration. Emitter diffusion is performed through the opening to form an emitter 19 and a collector contact 20.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a bipolar semiconductor device capable of reducing collector series resistance rC of an NPN transistor.

0002

[Prior Art] One of the important characteristics of an NPN transistor, which is the main element of a bipolar semiconductor device, is the saturation voltage VC.
There is E (sat). The saturation voltage mainly depends on the resistance of the epitaxial layer (collector series resistance rC), and the N+ buried layer buried under the epitaxial layer is created for the purpose of reducing the collector series resistance rC. In addition, in integrated circuits, there are restrictions on taking out electrodes from the epitaxial layer surface, so a highly doped collector low resistance region is provided from the epitaxial layer surface to the N+ buried layer, and the collector electrode is placed on the surface of this collector low resistance region. What is provided is widely known (for example, Japanese Patent Laid-Open No. 01-270349).

FIG. 5 shows a structure in which the collector extraction region is formed. In the figure, (1) is a P-type semiconductor substrate, (2) is an N-type epitaxial layer, (3) is an N+ type buried layer, (4) is an island region that becomes the collector of the NPN transistor, and (5) is P-type base region, (6) is N+
(7) is an N+ type collector low resistance region, (8) is an oxide film, and (9) is an Al electrode. According to this configuration, since the highly doped buried layer (3) and the collector low resistance region (7) are present in the collector current path, the collector series resistance rC can be reduced and the saturation voltage can be reduced.

0004

However, the structure shown in FIG. 5 has the disadvantage that the number of masks increases by one compared to an example in which the collector contact is formed by emitter diffusion. This has the disadvantage of complicating the manufacturing process and increasing costs.

[0005]

[Means for Solving the Problems] The present invention has been made in view of the above-mentioned drawbacks, and includes a step of forming a base region (16) on the surface of the island region (15) and an oxide film (17) for emitter diffusion. a step of forming an opening (18) of the opening (18);
a step of selectively etching the silicon surface exposed in the opening (1) with an etching solution having impurity concentration dependence;
8) to perform emitter diffusion using the formed oxide film (17) as a selective mask, it is possible to reduce the collector series resistance rC without increasing the number of masks.

[0006]

[Operation] Etching solutions such as potassium hydroxide (KOH) show dependence on impurities doped into the silicon surface and their concentration. In particular, the etching rate of silicon surfaces highly doped with boron (B) is extremely low. Therefore, according to the manufacturing method of the present invention, the collector electrode (2
4) can be excavated only on the surface of the island area (15) where it is to be provided. Also, an opening for emitter diffusion (18)
Since selective etching is performed using , there is no need to add a mask.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. First, an N+ type buried layer (12) is formed on the surface of a P type silicon substrate (11) with a plane orientation of (100), and an N type epitaxial layer (13) with an impurity concentration of about 1015 is formed on the substrate (11). Stack. A P+ type isolation region (14) penetrating the epitaxial layer (13) is formed from the surface of the epitaxial layer (13) by selective diffusion, and the epitaxial layer (13) is junction-separated to form an island region (15). Boron (B) on the surface of the island region (15)
is selectively diffused to form the base region (16
) and an oxide film ( ) on the surface of the epitaxial layer (13).
17) to form a selective mask for emitter diffusion (FIG. 1). The selective mask for emitter diffusion has openings (18) on the surface of the base region (16) and on the surface of the island region (15) where the collector electrode is to be placed. In addition, the base area (16) is 1016 to 1017at
It has a surface concentration of oms cm-2.

Next, potassium hydroxide (KOH) (80
The wafer is immersed for several minutes in an etching solution that is dependent on impurity concentration, such as a solution (18°C), and the silicon surface exposed in the opening (18) is etched by about 1 to 2 μm (FIG. 2). At this time, since the surface of the base region (16) is doped with boron (B), the etching rate with respect to the KOH aqueous solution is extremely small and is hardly etched. Since the surface of one island region (15) is doped with only a low concentration of phosphorus (P), the etching rate is fast. In addition to the above-mentioned KOH, etching solutions that exhibit impurity concentration dependence include ethylenediamine-pyrocatechol-water (EPW).
) (115℃) solution and hydrazine/water (100℃) solution.

Next, the selection mask used in the previous step is used again as a selection mask to fill the opening (18) with phosphorus (
By selectively diffusing P), an emitter region (19) and a collector contact region (20) are formed (FIG. 3). Since the surface of the base region (16) is hardly etched, the emitter region (19) can be controlled with high precision by double diffusion. Since the collector contact region (20) is formed on the surface of the island region (15) dug by selective etching, it is formed deeper than the emitter region (19).

Next, an oxide film (21) is formed on the surface of the epitaxial layer (13), contact holes are formed on each region, an aluminum film is formed by vapor deposition or sputtering, and this is patterned to form an electrode ( 2
2) Form (23) and (24) (Fig. 4). The semiconductor device manufactured in this way has a collector contact region (20
) is formed on the surface of the dug island region (15), the distance to the buried layer (12) is shortened, and the resistance of the epitaxial layer (13) can be reduced during this time. Therefore, by reducing the collector series resistance rC of the NPN transistor, the saturation voltage VCE (sat) can be reduced.

Furthermore, by using an etching solution that is dependent on impurity concentration, selective etching can be performed using the emitter diffusion window while leaving the surface of the base region (16) exposed.
There is no increase in the number of masks.

0012

[Effects of the Invention] As explained above, according to the present invention, K
By using an etching solution that is dependent on the concentration of impurities such as OH, there is an advantage that a structure capable of reducing the collector series resistance rC as shown in FIG. 4 can be manufactured without increasing the number of masks.

[Brief explanation of drawings]

FIG. 1 is a first cross-sectional view illustrating the manufacturing method of the present invention.

FIG. 2 is a second cross-sectional view illustrating the manufacturing method of the present invention.

FIG. 3 is a third sectional view illustrating the manufacturing method of the present invention.

FIG. 4 is a fifth sectional view illustrating the manufacturing method of the present invention.

FIG. 5 is a sectional view for explaining a conventional example.

Claims (2)

[Claims] 1. A method for manufacturing a semiconductor device in which a base region of one conductivity type and an emitter region of an opposite conductivity type are formed on the surface of an island region serving as a collector, wherein a base region of one conductivity type is formed on the surface of the island region. forming an emitter diffusion window, coating the surfaces of the base region and the island region with an insulating film, forming an emitter diffusion window in the insulating film on the surface of the base region and the surface of the island region, and A step of selectively etching the surface of the base region and the surface of the island region exposed to the window with an etching solution having impurity concentration dependence, and diffusing impurities of opposite conductivity type from the emitter diffusion window to form an emitter on the surface of the base region. forming a collector contact region on the surface of the island region etched by the selective etching. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching solution having impurity concentration dependence is a potassium hydroxide (KOH) solution.