JPH04298041A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04298041A
JPH04298041A JP6230891A JP6230891A JPH04298041A JP H04298041 A JPH04298041 A JP H04298041A JP 6230891 A JP6230891 A JP 6230891A JP 6230891 A JP6230891 A JP 6230891A JP H04298041 A JPH04298041 A JP H04298041A
Authority
JP
Japan
Prior art keywords
film
insulating film
etched
etching
resist mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6230891A
Other languages
Japanese (ja)
Inventor
Tetsuro Kondo
哲朗 近藤
Fukashi Harada
深志 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6230891A priority Critical patent/JPH04298041A/en
Publication of JPH04298041A publication Critical patent/JPH04298041A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To prevent corrosion of etched wiring irrespective of variations in conditions such as humidity and temperature. CONSTITUTION:A film 1 to be patterned, an insulating film 2, and a resist mask 6 are formed in sequence on a semiconductor substrate 5. The insulating film 2 and the film 1 are masked with the resist 6 and dry-etched. After the resist is removed, the insulating film 2 is etched by ion sputtering so that sputtered particles are deposited to form the side wall 3 of the film 1.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は半導体装置の製造方法に
係り,特に被エッチング膜(配線膜等)のエッチング後
に生ずる腐食を防止する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for preventing corrosion of a film to be etched (wiring film, etc.) after etching.

【0002】半導体装置の微細化に伴い,その製造工程
の一つであるエッチングがウエットからドライに変わっ
てから,エッチング後のアルミニウム(Al)系配線の
腐食を防止することが要求されている。
With the miniaturization of semiconductor devices, etching, which is one of the manufacturing steps, has changed from wet to dry etching, and there is a need to prevent corrosion of aluminum (Al)-based interconnects after etching.

【0003】本発明はこの要求に対応した製造方法とし
て利用することができる。
The present invention can be used as a manufacturing method that meets this requirement.

【0004】0004

【従来の技術】ドライエッチング後の配線の腐食は,例
えば,配線の側壁に残留する塩素と大気中の水分との反
応で生ずる反応生成物によって起こる。
2. Description of the Related Art Corrosion of wiring after dry etching is caused, for example, by reaction products produced by the reaction between chlorine remaining on the side walls of the wiring and moisture in the atmosphere.

【0005】このような配線の腐食を防止する従来方法
として次のようなものがあった。 ■  ドライエッチング後,直ちに,現像液,硝酸,ア
ンモニア,アルコール等を用いてウエット処理を行う。 ■  インラインでレジスト剥離(ウエット処理の一つ
)を行う。 ■  配線を覆ってフッ素系のパッシベーション膜を形
成する。
Conventional methods for preventing such corrosion of wiring include the following. ■ Immediately after dry etching, perform wet processing using a developer, nitric acid, ammonia, alcohol, etc. ■ Perform in-line resist stripping (a type of wet processing). ■ Form a fluorine-based passivation film to cover the wiring.

【0006】この内,■,■はウエット処理によりドラ
イエッチング後の残留塩素を除去するものであるが,完
全な処理は困難であった。上記■はパッシベーション膜
により大気中の水分との遮断を行うものであるが,十分
な効果は得られなかった。
Among these, methods (1) and (4) involve removing residual chlorine after dry etching by wet processing, but it was difficult to perform complete processing. The method (2) above uses a passivation film to block moisture from the atmosphere, but a sufficient effect was not obtained.

【0007】以上のように,いずれの腐食防止方法も完
全なものではなかった。
As described above, none of the corrosion prevention methods was perfect.

【0008】[0008]

【発明が解決しようとする課題】従来技術では,湿度や
温度等の不安定要素のわずかの変動に対しても腐食が発
生するという問題が生じていた。
[Problems to be Solved by the Invention] In the prior art, there has been a problem in that corrosion occurs even in response to slight fluctuations in unstable factors such as humidity and temperature.

【0009】本発明は湿度や温度等の不安定要素の変動
に対しても配線に腐食が発生しないような製造方法の提
供を目的とする。
An object of the present invention is to provide a manufacturing method that prevents corrosion of wiring even when unstable factors such as humidity and temperature change.

【0010】0010

【課題を解決するための手段】上記課題の解決は,半導
体基板(5) 上に被エッチング膜(1) 及び絶縁膜
(2) を順次被着し,該絶縁膜(2) 上にレジスト
マスク(6) を形成し,該レジストマスクをエッチン
グマスクにして該絶縁膜(2) 及び該被エッチング膜
(1) をドライエッチングする工程と,次いで,レジ
ストマスク(6) を除去し,該絶縁膜(2) に対し
イオンスパッタエッチングを行い,スパッタされた該絶
縁膜(2) を該被エッチング膜(1) の側面に再付
着させて側壁堆積膜(3)を形成する工程を有する半導
体装置の製造方法により達成される。
[Means for solving the problem] The above problem can be solved by sequentially depositing a film to be etched (1) and an insulating film (2) on a semiconductor substrate (5), and applying a resist mask on the insulating film (2). (6) dry etching the insulating film (2) and the film to be etched (1) using the resist mask as an etching mask, and then removing the resist mask (6) and etching the insulating film. (2) perform ion sputter etching on the insulating film (2), and re-deposit the sputtered insulating film (2) on the side surface of the film to be etched (1) to form a sidewall deposited film (3). This is achieved by a manufacturing method.

【0011】[0011]

【作用】図1 (A)〜(C) は本発明の原理説明図
である。 図1(A) はエッチング前の断面図である。
[Operation] FIGS. 1A to 1C are diagrams explaining the principle of the present invention. FIG. 1(A) is a cross-sectional view before etching.

【0012】図において,1は被エッチング膜,2は絶
縁膜,4は層間絶縁膜,5は半導体基板,6はレジスト
マスクである。半導体基板5上に,層間絶縁膜4,被エ
ッチング膜1,絶縁膜2を順次積層し,絶縁膜2上にレ
ジストマスク6を形成し,これをエッチングマスクにし
て絶縁膜2及び被エッチング膜1をドライエッチングし
てパターンを形成する。
In the figure, 1 is a film to be etched, 2 is an insulating film, 4 is an interlayer insulating film, 5 is a semiconductor substrate, and 6 is a resist mask. An interlayer insulating film 4, a film to be etched 1, and an insulating film 2 are sequentially laminated on a semiconductor substrate 5, a resist mask 6 is formed on the insulating film 2, and using this as an etching mask, the insulating film 2 and the film to be etched 1 are stacked. A pattern is formed by dry etching.

【0013】図1(B) はエッチング後の断面図であ
る。 図において,レジストマスク6を剥離する。図1(C)
 において,基板表面をイオンスパッタエッチングして
,スパッタされた絶縁膜2が被エッチング膜1の側面に
再付着して側壁堆積膜3を形成する。
FIG. 1B is a cross-sectional view after etching. In the figure, the resist mask 6 is peeled off. Figure 1(C)
In this step, the surface of the substrate is subjected to ion sputter etching, and the sputtered insulating film 2 is reattached to the side surface of the film to be etched 1 to form a sidewall deposited film 3.

【0014】本発明は,この側壁堆積膜3とエッチング
後に残留した絶縁膜2が側壁を含めて被エッチング膜全
体を覆い,大気中の水分と残留塩素とを遮断して被エッ
チング膜の腐食の発生を防止するものである。
In the present invention, the sidewall deposited film 3 and the insulating film 2 remaining after etching cover the entire film to be etched including the sidewalls, block moisture in the atmosphere and residual chlorine, and prevent corrosion of the film to be etched. This is to prevent this from occurring.

【0015】[0015]

【実施例】図1を用いて実施例を説明する。図1(A)
 において,半導体基板としシリコン(Si)基板5上
に,層間絶縁膜として気相成長(CVD) による厚さ
4000Åの二酸化シリコン(SiO2)膜4,被エッ
チング膜として厚さ5000〜10000 Åのアルミ
ニウム(Al)膜(またはAl合金膜) 1,絶縁膜と
して厚さ4000ÅCVD SiO2膜2を順次積層し
,CVD SiO2膜2上に厚さ 2.0μmのレジス
トマスク6を形成し,これをエッチングマスクにしてC
VD SiO2膜2及びAl膜1をドライエッチングし
てパターンを形成する。
[Embodiment] An embodiment will be explained using FIG. Figure 1(A)
In this process, a silicon dioxide (SiO2) film 4 with a thickness of 4,000 Å was formed by vapor phase growth (CVD) as an interlayer insulating film on a silicon (Si) substrate 5 as a semiconductor substrate, and an aluminum film (with a thickness of 5,000 to 10,000 Å) as a film to be etched. Al) film (or Al alloy film) 1. CVD SiO2 films 2 with a thickness of 4000 Å are laminated in sequence as insulating films, and a resist mask 6 with a thickness of 2.0 μm is formed on the CVD SiO2 film 2, and this is used as an etching mask. C
A pattern is formed by dry etching the VD SiO2 film 2 and the Al film 1.

【0016】エッチャは異方性エッチングができる反応
性イオンエッチング(RIE) 装置や電子サイクロト
ロン共鳴(ECR) エッチング装置等を用いる。ドラ
イエッチングの条件は, 例えば以下のようである。
As the etcher, a reactive ion etching (RIE) device or an electron cyclotron resonance (ECR) etching device capable of anisotropic etching is used. For example, the conditions for dry etching are as follows.

【0017】SiO2のエッチング条件反応ガス:  
CF4/CHF3 ガス圧力:  0.3 Torr RF  電力:  600 W Alのエッチング条件 反応ガス:  BCl3/SiCl4/Cl2ガス圧力
:  0.1 Torr RF  電力:  300 W 図1(B) はドライエッチング後の断面図である。
Etching conditions for SiO2 Reactive gas:
CF4/CHF3 gas pressure: 0.3 Torr RF power: 600 W Al etching conditions Reactive gas: BCl3/SiCl4/Cl2 gas pressure: 0.1 Torr RF power: 300 W Figure 1(B) is the cross section after dry etching It is a diagram.

【0018】図において,インラインで,レジストマス
ク6を剥離する。図1(C) において,CVD Si
O2膜2に対してイオンスパッタエッチングを行う。こ
の際,スパッタされたCVD SiO2膜2がAl膜1
の側面に再付着して側壁堆積膜3が形成される。
In the figure, the resist mask 6 is peeled off in-line. In Figure 1(C), CVD Si
Ion sputter etching is performed on the O2 film 2. At this time, the sputtered CVD SiO2 film 2 is attached to the Al film 1.
The sidewall deposited film 3 is formed by re-adhering to the side surface of the film.

【0019】イオンスパッタエッチングの条件の一例は
以下のようである。 イオン種:  Ar, Xe ガス圧力:  0.1 Torr RF  電圧:  800 W 以上の実施例の結果, 付加的な効果として, 配線形
成後に絶縁膜形成時の加熱によって配線に生ずる突起の
発生を防止できる。
An example of the conditions for ion sputter etching is as follows. Ion species: Ar, Xe Gas pressure: 0.1 Torr RF voltage: 800 W As a result of the above examples, as an additional effect, it is possible to prevent the formation of protrusions on the wiring due to heating during the formation of the insulating film after the wiring is formed. .

【0020】[0020]

【発明の効果】湿度や温度等の不安定要素が変動しても
配線の腐食発生を完全に防止した製造方法が得られた。
Effects of the Invention: A manufacturing method has been obtained which completely prevents corrosion of wiring even if unstable factors such as humidity and temperature fluctuate.

【0021】この結果,半導体装置の信頼性の向上に寄
与することができた。
As a result, it was possible to contribute to improving the reliability of the semiconductor device.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】  本発明の原理説明図[Figure 1] Diagram explaining the principle of the present invention

【符号の説明】[Explanation of symbols]

1  被エッチング膜でAl膜 2  絶縁膜でCVD SiO2膜 3  側壁堆積膜 4  層間絶縁膜でCVD SiO2膜5  半導体基
板でSi基板 6  レジストマスク
1 Film to be etched: Al film 2 Insulating film: CVD SiO2 film 3 Sidewall deposited film 4 Interlayer insulation film: CVD SiO2 film 5 Semiconductor substrate: Si substrate 6 Resist mask

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  半導体基板(5) 上に被エッチング
膜(1) 及び絶縁膜(2) を順次被着し,該絶縁膜
(2) 上にレジストマスク(6) を形成し,該レジ
ストマスクをエッチングマスクにして該絶縁膜(2) 
及び該被エッチング膜(1) をドライエッチングする
工程と,次いで,レジストマスク(6) を除去し,該
絶縁膜(2) に対しイオンスパッタエッチングを行い
,スパッタされた該絶縁膜(2) を該被エッチング膜
(1) の側面に再付着させて側壁堆積膜(3)を形成
する工程を有することを特徴とする半導体装置の製造方
法。
Claim 1: A film to be etched (1) and an insulating film (2) are sequentially deposited on a semiconductor substrate (5), a resist mask (6) is formed on the insulating film (2), and a resist mask (6) is formed on the insulating film (2). using the insulating film (2) as an etching mask.
and dry etching the film to be etched (1), then removing the resist mask (6), performing ion sputter etching on the insulating film (2), and removing the sputtered insulating film (2). A method for manufacturing a semiconductor device, comprising the step of forming a sidewall deposited film (3) by redepositing the film to be etched on the side surface of the film (1).
JP6230891A 1991-03-27 1991-03-27 Manufacture of semiconductor device Withdrawn JPH04298041A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6230891A JPH04298041A (en) 1991-03-27 1991-03-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6230891A JPH04298041A (en) 1991-03-27 1991-03-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04298041A true JPH04298041A (en) 1992-10-21

Family

ID=13196379

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6230891A Withdrawn JPH04298041A (en) 1991-03-27 1991-03-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04298041A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5417799A (en) * 1993-09-20 1995-05-23 Hughes Aircraft Company Reactive ion etching of gratings and cross gratings structures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5417799A (en) * 1993-09-20 1995-05-23 Hughes Aircraft Company Reactive ion etching of gratings and cross gratings structures

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Legal Events

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A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19980514