JPH04298036A - Method for manufacture of semiconductor - Google Patents

Abstract

PURPOSE:To obtain a plasma etching method capable of etching a via hole which penetrates a compound semiconductor substrate with a high precision at a high speed. CONSTITUTION:In a first stage etching, the effect of a sputter etching is eliminated by suppressing RF power at a low level, and a via hole opening 3a is formed by etching. Then, in a second stage etching, the RF power is increased to perform a high speed etching. Thus, a via hole opening 3b is formed without any column-shaped residue.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of etching a hole (hereinafter referred to as a via hole) penetrating a compound semiconductor substrate.

0002

2. Description of the Related Art FIG. 3 shows an etched cross-sectional view obtained by a conventional compound semiconductor etching method. In the figure, an etching mask 2 is formed on a compound semiconductor substrate 1, and a via hole etched portion 3 is formed at a predetermined location. Further, reference numeral 4 indicates an undercut generated in the substrate portion below the mask 2 due to etching.

Next, the manufacturing method will be explained. for example,
In the case of semiconductor devices using GaAs, via holes are etched using wet etching or plasma etching. Because wet etching is essentially isotropic etching, it is difficult to etch via holes with high pattern accuracy, and the depth of the via hole (generally, this is the thickness of the semiconductor substrate) and the etching opening diameter It is impossible to form a via hole with a ratio of 1 or more. For this reason, plasma etching, which allows more anisotropic etching and has excellent pattern accuracy, has come to be used. However, when performing etching with high pattern accuracy using plasma etching, the etching rate is several thousand angstroms/min, and even if a magnetron RIE is used as an etching device to achieve higher speed etching, the etching rate is about 1 μm/min. An etching rate of only

FIG. 5 shows silicon tetrachloride (hereinafter referred to as SiCl4).
) and chlorine (hereinafter referred to as Cl2), the total flow rate was 50 sccm, the RF power was 300 W, the etching time was 25 minutes, the etching pressure and the gas flow rate ratio were each 20 to 50 mTorr, and the Cl2 flow rate ratio was 20 to 50 mTorr. The figure shows the etching depth of GaAs when the etching depth is 60%. As shown in the figure, the higher the pressure during etching and the larger the Cl2 flow rate ratio, the greater the etching depth, that is, the etching rate tends to increase.

However, although the etching rate increases due to the increase in pressure and the increase in the Cl2 flow rate ratio, the etching cross-sectional shape is reduced by the undercut 4 as shown in FIG.
or surface roughness may occur on the side wall of the hole. This undercut 4 deteriorates pattern accuracy and also impedes pattern miniaturization. In addition, the surface roughness of the side wall of the hole causes problems such as adhesion when the etched side wall is coated with a conductor in a later step.

[0006] Therefore, etching conditions that allow a high etching rate and do not cause undercuts or roughness on the side wall surfaces of the holes include gas flow rate ratio of 20% Cl2 and pressure of 30 mT.
orr, the case with RF power of 300 W is the best, and if the value D/t obtained by dividing the etching depth D at this time by the etching time t is 25 minutes, the etching rate is 1.7 μm/
It became min.

[0007]

[Problems to be Solved by the Invention] Via holes are formed by the conventional manufacturing method of semiconductor devices as described above.
When performing μm via hole etching, due to contamination in the etching chamber of the etching equipment and instability of RF power, when a power of 300 W or more is applied, a columnar residue 5 as shown in Fig. 4 is formed at the bottom of the hole. Many things happen. In addition, R
When the F power is increased, such columnar residues are generated more noticeably, which again poses problems such as becoming an obstacle when covering the via hole with a conductor and metallizing it.

[0008] This invention was made to solve the above-mentioned problems, and it is possible to form via holes with high pattern accuracy, and metallization can be performed without creating obstacles such as columnar residues that deteriorate the etching cross-sectional shape. An object of the present invention is to provide a method for manufacturing a semiconductor device that can perform etching at a high etching rate.

[0009]

[Means for Solving the Problems] Etching of via holes according to the method of manufacturing a semiconductor device according to the present invention is performed by step etching of multiple levels using a plasma etching method, and the first stage of etching is performed using a sputter etching method with a low sputter etching effect. This is done under certain conditions.

0010

[Operation] In this invention, since the first step of etching the semiconductor substrate is performed under etching conditions that have a low sputter etching effect, there is a low probability that the removed material sputter etched in the subsequent etching will re-adhere to the etched bottom surface. Even if high-speed etching is performed with high RF power, no columnar residue is generated.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic cross-sectional view of a device according to a method of manufacturing a semiconductor device according to an embodiment of the present invention.
A GaAs substrate was etched using the device. The same reference numerals as in FIGS. 3 and 4 indicate the same or corresponding parts, and 3a and 3b are via hole openings. Also, Figure 1
(a) is a cross-sectional view during the first stage of etching, and Figure (b) is a cross-sectional view during the subsequent second stage of etching.

Next, the manufacturing method will be explained. When etching a via hole with an opening diameter of 60 μm, a mixed gas of 40 sccm of SiCl4 gas and 10 sccm of Cl2 gas is used as the etching gas, and the pressure is 30 mTorr.
, when etching is performed for 5 minutes with RF power of 225W, Figure 1
As shown in (a), the via hole 3a has a depth d1 of 10 μm and a cross-sectional shape with excellent anisotropy. next,
The via hole opening 3 is etched to a desired depth d2, for example 100 μm, using RF power of 300 W.
get b.

[0013] By performing the etching in two stages as described above, etching can be achieved in which no columnar residue is generated at the bottom of the hole. This is based on the fact that under etching conditions that have a sputter etching effect, the probability that the substance from which the mask material 2 and the like has been sputtered will re-adhere to the etched surface is reduced in recesses.

FIG. 2 shows the number of columnar residues generated with respect to the depth when the first stage of etching was performed under etching conditions in which sputter etching is not effective. As can be seen from this figure, no columnar residue is generated at a depth of 9 μm or more.

[0015] In the above embodiment, GaAs is replaced with SiCl.
Although the case where etching is performed using a mixed gas of BCl3 and Cl2 is shown, other compound semiconductors such as InP may be used, and the etching gas may also be etched using a mixed gas of BCl3 and Cl2.
A mixed gas of l2 or a methane gas such as CH4 may be used.

Furthermore, the etching apparatus may be a commonly used parallel plate type RIE.

Furthermore, although the above embodiments have shown two-stage etching, the present invention is characterized by using conditions that have no sputter etching effect for the first stage of etching, so that it is possible to perform etching in three or four stages. I don't mind.

[0018]

As described above, according to the method of manufacturing a semiconductor device according to the present invention, multiple levels of step etching are performed using the plasma etching method, and the first stage of etching is performed under conditions with less sputter etching effect. Since this is done, there is no deterioration of the etched cross-sectional shape such as columnar residue, high-accuracy high-speed etching can be realized, and the via holes can be well metalized.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the number of columnar residues with respect to the etching depth in the first step in the method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view during etching by a conventional semiconductor device manufacturing method.

FIG. 4 is a cross-sectional view of an etching process in which columnar residues are generated by a conventional semiconductor device manufacturing method.

FIG. 5 is a diagram showing the pressure dependence of etching depth according to a conventional semiconductor device manufacturing method.

[Explanation of symbols]

1 Compound semiconductor substrate 2 Etching mask 3 Via hole opening 4 Undercut 5 Columnar residue

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device comprising a step of forming via holes on a semiconductor device substrate by etching using a mask, wherein the etching step uses plasma etching and is first performed under conditions with a low sputter etching effect. 1. A method for etching a semiconductor device, the method being a multi-step etching process including etching.