JPH04296964A - Sub-cpu start control system - Google Patents

Sub-cpu start control system

Info

Publication number
JPH04296964A
JPH04296964A JP4974891A JP4974891A JPH04296964A JP H04296964 A JPH04296964 A JP H04296964A JP 4974891 A JP4974891 A JP 4974891A JP 4974891 A JP4974891 A JP 4974891A JP H04296964 A JPH04296964 A JP H04296964A
Authority
JP
Japan
Prior art keywords
sub
cpu
cpus
order
started
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4974891A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Kokubo
小久保 光洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4974891A priority Critical patent/JPH04296964A/en
Publication of JPH04296964A publication Critical patent/JPH04296964A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE:To omit the waiting time of a main CPU by changing the starting order of sub-CPUs according to the starting propriety of the sub-CPUs when these sub-CPUs are started by the main CPU. CONSTITUTION:A main CPU 1 starts successively the sub-CPUs 4, 6 and 8. If one of these sub-CPUs could not be started since it is under processing, this sub-CPU is skipped and the next sub-CPU is started. At the same time, the starting order of the skipped sub-CPU is changed and recorded in a memory 2. The subsequent sub-CPU 4, 6 and 8 are started in the order recorded in the memory 2.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は、複数のCPUから構
成される計算機システムのサブCPU起動順序に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sub-CPU activation order in a computer system composed of a plurality of CPUs.

【0002】0002

【従来の技術】図3に従来のサブCPU起動管理方式を
示す。この方式では、サブCPU起動管理プログラムが
機械的に各サブCPUを一定順序で起動する。
2. Description of the Related Art FIG. 3 shows a conventional sub-CPU startup management system. In this method, a sub-CPU activation management program mechanically activates each sub-CPU in a fixed order.

【0003】次に動作について説明する。サブCPU起
動管理プログラムが起動されると、処理が開始される。 (ステップ22)サブCPU起動管理プログラムは先ず
サブCPU1が起動可能状態にあるか否かを調査する。 (ステップ23)起動可能状態であれば、サブCPU1
を起動し、(ステップ24)次いでサブCPU2が起動
可能か否か調査する。(ステップ25)もし、サブCP
U1が起動可能状態でなければ、サブCPU1が起動可
能状態になるまで待ち、サブCPU1を起動する。(ス
テップ23)以降、サブCPUの数n個だけ、上記処理
を繰り返す。(ステップ25〜ステップ28)上記処理
が全て終了すると、その周期の処理は終了となり(ステ
ップ29)、再びサブCPU起動管理プログラムが起動
される。
Next, the operation will be explained. When the sub-CPU activation management program is activated, processing begins. (Step 22) The sub-CPU activation management program first investigates whether the sub-CPU 1 is in a bootable state. (Step 23) If the state is ready to start, sub CPU1
(Step 24) Next, it is investigated whether the sub CPU 2 can be started. (Step 25) If the sub CP
If U1 is not in the bootable state, wait until the sub CPU1 becomes bootable, and then start the sub CPU1. (Step 23) From then on, the above process is repeated for the number n of sub-CPUs. (Steps 25 to 28) When all of the above processing is completed, the processing for that cycle is completed (Step 29), and the sub CPU activation management program is activated again.

【0004】0004

【発明が解決しようとする課題】従来のサブCPU起動
管理方式は、以上のような処理を行っているので、サブ
CPUが起動可能でなければ、起動可能となるまで待た
なければならず、その間メインCPU側では処理を行え
ず、そのため定周期の時間を長くする必要があり、処理
速度が遅くなる等の課題があった。
[Problem to be Solved by the Invention] The conventional sub-CPU startup management method performs the processing described above, so if the sub-CPU cannot be started, it must wait until it becomes possible to start. Processing cannot be performed on the main CPU side, so it is necessary to lengthen the periodic period, resulting in problems such as slow processing speed.

【0005】この発明は、上記のような課題を解決する
ためになされたもので、メインCPUの待ち時間をなく
し、処理速度を向上させる事を目的とする。
The present invention has been made to solve the above-mentioned problems, and its purpose is to eliminate the waiting time of the main CPU and improve processing speed.

【0006】[0006]

【課題を解決するための手段】この発明に係るサブCP
U起動管理方式は、メインCPUがサブCPUを起動す
る時に起動不可能であれば、そのサブCPUの起動をス
キップし、以降の周期において、同様のスキップ処理を
行わせない様に、変更した起動順序をメモリに格納して
おく。
[Means for solving the problem] Sub-CP according to the present invention
The U startup management method skips the startup of the sub CPU if it is unable to start it when the main CPU starts the sub CPU, and uses a modified startup method so that the same skip processing is not performed in subsequent cycles. Store the order in memory.

【0007】[0007]

【作用】この発明におけるサブCPU起動方式は、起動
順序をメモリに格納しておき、その順序に従って起動さ
れるので、サブCPUが起動不可能の場合に起動順序を
変更し、変更した起動順序をメモリに格納することによ
り、以降の周期では変更した順序で起動される。
[Operation] The sub-CPU starting method in this invention stores the starting order in memory and starts up according to that order. Therefore, if the sub-CPU cannot be started, the starting order is changed and the changed starting order is changed. By storing them in memory, they will be activated in the changed order in subsequent cycles.

【0008】[0008]

【実施例】図1に発明の実施例を示す。メインCPU1
は子局5、7、9のサブCPU4、6、8に仕事をさせ
ながら、サブCPU4、6、8に対して上位処理を行う
。各々のサブCPUを伝送路10を通して、順番に通信
を行うが、いずれかのサブCPUが処理中等で起動不可
能であれば、起動をスキップすると共に主局3中のメモ
リ2に変更した起動順序を格納する。以降の周期では、
メインCPU1はメモリ2を参照しながらサブCPU4
、6、8を起動する。
Embodiment FIG. 1 shows an embodiment of the invention. Main CPU1
performs upper-level processing for the sub CPUs 4, 6, and 8 while making the sub CPUs 4, 6, and 8 of the slave stations 5, 7, and 9 work. Communication is performed in order with each sub CPU through the transmission line 10, but if any sub CPU cannot be started due to processing etc., the start up is skipped and the changed start order is changed to the memory 2 in the main station 3. Store. In subsequent cycles,
Main CPU 1 refers to memory 2 while sub CPU 4
, 6, and 8.

【0009】図2に、本サブCPU起動方式のフローチ
ャートを示す。サブCPU起動管理プログラムが起動さ
れると、処理が開始される。(ステップ11)サブCP
U起動管理プログラムは先ずサブCPU1が起動可能状
態にあるか否かを調査する。(ステップ12)起動可能
状態であれば、サブCPU1を起動し(ステップ13)
次いでサブCPU2が起動可能か否かを調査する。(ス
テップ15)サブCPU1が起動可能状態でなければ、
サブCPUの処理をスキップし、起動順序の変更を行い
、メモリ2に格納する。(ステップ14)以降サブCP
Uの数n個だけ、上記処理を繰り返す。(ステップ15
〜20)上記処理が全て終了すると、その周期の処理は
終了となり、(ステップ21)再びサブCPU起動管理
プログラムが起動される。以降の周期では、変更された
起動順序で、メモリ2に記録された起動順序に従って起
動される。この処理は毎周期行われ、常に最適な順序で
起動される。
FIG. 2 shows a flowchart of this sub-CPU startup method. When the sub-CPU activation management program is activated, processing begins. (Step 11) Sub CP
The U boot management program first investigates whether the sub CPU 1 is in a bootable state. (Step 12) If the state is ready to start, start sub CPU1 (Step 13)
Next, it is investigated whether the sub CPU 2 can be started. (Step 15) If sub CPU1 is not in a bootable state,
The processing of the sub CPU is skipped, the startup order is changed, and the result is stored in the memory 2. (Step 14) Sub CP
The above process is repeated for the number n of U's. (Step 15
~20) When all of the above processes are completed, the process for that cycle is completed (step 21), and the sub CPU activation management program is activated again. In subsequent cycles, the devices are activated in accordance with the changed activation order and the activation order recorded in the memory 2. This process is performed every cycle and is always activated in the optimal order.

【0010】なお、上記実施例では、複数のCPUより
構成される計算機システムについてのものであるが、単
一のCPUの場合でも複数のモジュールから構成され、
そのモジュールが周期的に起動される場合等にも当然適
用可能である。
[0010]Although the above embodiment concerns a computer system composed of a plurality of CPUs, even in the case of a single CPU, it is composed of a plurality of modules.
Naturally, the present invention can also be applied to cases where the module is activated periodically.

【0011】[0011]

【発明の効果】以上のように、この発明によれば、メイ
ンCPUが他のサブCPUとのタイミングを測り、常に
適切な順序で起動できるので、メインCPUの待ち時間
がなくなり、計算機の高速処理が可能となる。
As described above, according to the present invention, the main CPU can measure the timing with other sub-CPUs and always start them in the appropriate order, eliminating the waiting time of the main CPU and increasing the speed of computer processing. becomes possible.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】この発明の実施例1を示す計算機システムの構
成図である。
FIG. 1 is a configuration diagram of a computer system showing a first embodiment of the present invention.

【図2】この発明の実施例1のサブCPU起動管理方式
の動作の説明をするフローチャートである。
FIG. 2 is a flowchart illustrating the operation of the sub-CPU activation management method according to the first embodiment of the present invention.

【図3】従来のサブCPU起動管理方式を説明するフロ
ーチャートである。
FIG. 3 is a flowchart illustrating a conventional sub-CPU activation management method.

【符号の説明】[Explanation of symbols]

1  メインCPU 2  メモリ 4  サブCPU 6  サブCPU 8  サブCPU 1 Main CPU 2 Memory 4 Sub CPU 6 Sub CPU 8 Sub CPU

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  1個のメインCPUにより複数のサブ
CPUを順次周期的に起動して処理を行わせる計算機シ
ステムのサブCPU起動管理方式において、上記メイン
CPUにより起動を行ったサブCPUの起動可否により
、サブCPUの起動順序を変更することを特徴とするサ
ブCPU起動管理方式。
Claim 1: In a sub-CPU activation management method for a computer system in which one main CPU sequentially and periodically activates a plurality of sub-CPUs to perform processing, whether or not the sub-CPUs activated by the main CPU can be activated or not. A sub-CPU startup management method characterized by changing the startup order of sub-CPUs.
JP4974891A 1991-03-14 1991-03-14 Sub-cpu start control system Pending JPH04296964A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4974891A JPH04296964A (en) 1991-03-14 1991-03-14 Sub-cpu start control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4974891A JPH04296964A (en) 1991-03-14 1991-03-14 Sub-cpu start control system

Publications (1)

Publication Number Publication Date
JPH04296964A true JPH04296964A (en) 1992-10-21

Family

ID=12839804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4974891A Pending JPH04296964A (en) 1991-03-14 1991-03-14 Sub-cpu start control system

Country Status (1)

Country Link
JP (1) JPH04296964A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012174220A (en) * 2011-02-24 2012-09-10 Fujitsu Frontech Ltd Server management device, server management program, server management method, and server management system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012174220A (en) * 2011-02-24 2012-09-10 Fujitsu Frontech Ltd Server management device, server management program, server management method, and server management system

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