JPH04296075A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device manufactured through a hetero epitaxy method and provided with a growth layer of high quality by a method wherein the growth layer is lessened in through dislocation caused by misfit dislocations induced at an interface between a substrate and the growth layer. CONSTITUTION:When semiconductor layers 21, 22, 4, 6, and 8 different in lattice contact are laminated on a semiconductor substrate 1, a semiconductor layers of high quality can be obtained by providing one or more of single-layered distorted films 3, 5, and 5 smaller than a critical value in thickness or one or more of distorted layers larger than a critical value in thickness to the semiconductor layers concerned. Most of through location disappears in the single-layered distorted layers smaller or larger than a critical value in thickness, and as new misfit dislocation is hardly induced in the distorted layers smaller than a critical value in thickness, semiconductor layers of high quality can be obtained.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor device formed by stacking different types of semiconductor layers with different lattice constants, and more particularly to an electronic optical integrated device formed by stacking an electronic element and an optical element on the same substrate. The present invention relates to a semiconductor device particularly suitable for application to elements (OEIC, etc.).

0002

[Prior Art] In heteroepitaxy, in which semiconductor layers with different lattice constants are laminated on a semiconductor substrate, it is known that misfit dislocations occur due to the difference in lattice constant and thermal expansion coefficient between the substrate and the grown layer. It is being Removal of these misfit dislocations is the biggest challenge in heteroepitaxy. Conventionally, as described in the 51st Annual Conference of the Japan Society of Applied Physics (29p-T-3), a strained superlattice layer in which two types of semiconductor layers with different lattice constants are alternately repeated multiple times is used at least once. By introducing it into the growth layer, the propagation of misfit dislocations generated at the interface between the semiconductor substrate and the growth layer is suppressed, and subsequent dislocations within the growth layer are reduced. It is known that most threading dislocations are bent and annihilated in the lateral direction along the grown layer, mainly at the substrate-side interface of the strained superlattice layer introduced into the grown layer. It is known that introducing strained superlattice layers multiple times is more effective in reducing threading dislocations, as described in the above-mentioned proceedings.

0003

[Problems to be Solved by the Invention] Even in the above-mentioned conventional technology, the propagation of misfit dislocations generated at the interface between the semiconductor substrate and the growth layer is suppressed by the strained superlattice layer (a layer in which a plurality of strained thin films are laminated), and the subsequent This has the effect of reducing dislocations within the grown layer. However, the total thickness of the strained layers in the strained superlattice layer tends to exceed the critical thickness, and many heterointerfaces in the strained superlattice become a cause of dislocation generation, resulting in new misfit dislocations. For this reason, it was found that these new misfit dislocations propagate into the subsequent growth layer, and the effectiveness of dislocation reduction does not improve. Furthermore, since the superlattice structure is introduced multiple times, the growth layer structure becomes complicated. The present invention suppresses the propagation of misfit dislocations generated at the interface between the semiconductor substrate and the growth layer, and eliminates the generation of new misfit dislocations at the interface of the strained layer introduced into the growth layer, thereby producing high-quality semiconductors. The purpose is to obtain a growth layer. Furthermore, another object of the present invention is to simplify the layer structure and more easily obtain a high quality semiconductor growth layer.

0004

[Means for Solving the Problems] In order to achieve the above object, in the present invention, a strained ultra-thin film having a thickness below the critical film thickness is introduced at least once as a single layer instead of the conventional strained superlattice layer. Furthermore, in order to more effectively obtain a high-quality semiconductor growth layer, the present invention provides that at least the first strained layer introduced multiple times in a single layer has a thickness equal to or greater than the critical film thickness, and at least the last strained layer during growth. This is done once using a strained thin film having a thickness less than the critical film thickness.

[0005] Here, a "strained thin film" is a thin film that has a lattice constant different from that of an adjacent semiconductor layer. Usually, there are two adjacent semiconductor layers, but this includes cases where only one of them has a different lattice constant. Specifically, the case where the lattice constant value is intermediate between the values of the two layers sandwiching the thin film, or
It is also possible in the present invention to have a lattice constant value that is even larger than the value of the lattice constant of the two layers sandwiching the thin film. In addition, "introducing a single layer of strained thin films multiple times" means interposing a sufficiently thick semiconductor layer thicker than the strained thin films between the strained thin films. As a result, the present invention has a form different from conventional superlattice structures. That is, the conventional superlattice structure is a laminated structure of a plurality of thin films, but the dislocation reduction region according to the present invention has a sufficient thickness of, for example, 0.1 μm or more and 2 μm or less, preferably 0.2 μm or more and 1 μm or less. A plurality of strained thin films are introduced through the semiconductor layer. Furthermore, when referring to a "strained layer" in this specification, it is understood that there is no particular restriction on the film thickness. The strained layer also includes a strained superlattice structure.

As described above, according to the present invention, in a semiconductor device such as an electronic optical semiconductor device having an electronic element section having an electronic active region and an optical element section having an optical active region,
For example, the electronic device portion is provided on a first semiconductor substrate region having a first lattice constant, and the optical device portion is provided on a second semiconductor substrate region having a second lattice constant different from the first lattice constant. A semiconductor device is provided in which a dislocation reduction region is disposed between the first and second semiconductor substrate regions, and the dislocation reduction region has a single layer of a strained thin film. It is important that this single-layer strained thin film has a thickness below a critical film thickness at which misfit dislocations begin to occur. Further, it is preferable that a plurality of strained thin films are provided in the dislocation reduction region, and the above-mentioned single-layer strained thin film is disposed above the plurality of strained thin films (formed last during growth). Furthermore, in order to further enhance the effects of the present invention, it is preferable to introduce a plurality of single-layer strained thin films into the dislocation reduction region. When introducing a plurality of strained thin films, it is important to arrange a semiconductor layer having a thickness of 0.1 μm or more and 2 μm or less (preferably 0.2 μm or more and 1 μm or less) between the strained thin film layers. If the thickness of this intervening layer becomes extremely small and becomes equal to or less than the strained thin film described above, it becomes equivalent to a conventional superlattice structure and the effects of the present invention cannot be obtained. Furthermore, when integrating electronic elements and optical elements, it is important to form these elements on substantially the same plane. For this purpose, it is effective, for example, to etch the first semiconductor region to form a recess, and to arrange the dislocation reduction region thereon.

[0007]

[Effect] In the conventional dislocation reduction method of introducing strained superlattice layers multiple times as shown in Figure 4, most of the threading dislocations due to the propagation of misfit dislocations generated at the interface between the substrate and the growth layer occur in the strained superlattice layer. However, new misfit dislocations occur at other interfaces within the strained superlattice layer. The number of such misfit dislocations is smaller than the number of misfit dislocations that occur at the interface between the substrate and the growth layer, which have a large lattice constant difference, because the lattice constant difference is small, but some of them are within the same strained superlattice layer. It disappears and a part of it propagates to the next growth layer. For this reason, dislocation reduction is not performed effectively.

However, when a strained ultra-thin film with a thickness below the critical thickness is introduced as a single layer as in the present invention, threading dislocations disappear at the interface of the strained layer, and since the thickness of the strained layer is below the critical thickness, No new misfit dislocations occur either. In the present invention, as in the case of strained superlattice layers, not all threading dislocations are annihilated at the interface of one strained layer. A portion propagates to the next growth layer. However, since new misfit dislocations are not generated, threading dislocations are definitely reduced. Furthermore, by introducing the strained layer multiple times, most of the threading dislocations are eliminated, and a high quality semiconductor layer can be obtained.

In addition, threading dislocations are more effectively bent laterally and annihilated in strained layers having a film thickness greater than the critical film thickness (
(Although new misfit dislocations may occur), the present invention involves making the initial strained layer of the strained layer introduced multiple times to have a thickness equal to or greater than the critical thickness, and then introducing a strained layer having a thickness equal to or less than the critical thickness at least once. In this structure, threading dislocations caused by a large number of misfit dislocations generated at the interface between the substrate and the grown layer are more effectively quenched in the strained layer with a thickness greater than the initial critical thickness. New misfit dislocations also occur in this strained layer (very small in number compared to the number of misfit dislocations at the interface between the substrate and the grown layer), but these are eliminated by the next strained layer having a thickness below the critical film thickness. Therefore, a semiconductor layer of significantly higher quality can be obtained than in the case of strained layers whose thicknesses are all below the critical thickness.

0010

EXAMPLES Example 1 An example of the present invention will be described below with reference to FIGS. 1 and 2 in the case of heteroepitaxy for growing InP on a GaAs substrate.

As shown in FIG. 1, n-In is deposited on an n+-GaAs substrate 1 by metal organic chemical vapor deposition (MOCVD).
A P layer 21 (thickness: 2.0 μm) is grown. After the growth is temporarily interrupted, heat treatment is performed in a PH3 atmosphere. This heat treatment may include normal high temperature annealing (e.g. 700 to 800°C) or thermal cycle annealing (e.g. 200°C⇔800°C).
(repeated multiple times) is often used. In this example,
Thermal cycle annealing was employed and three thermal cycles were performed under the above conditions. After that, the InP layer 22 (thickness 1
．． 0 μm), and further grown an n-GaInP strained thin film I3,
n-InP layer 4 (thickness 0.5 μm), n-GaInP strained thin film II5, n-InP layer 6 (thickness 0.5 μm), n-
GaInP strained thin film III 7, n-InP layer 8 (thickness 2.
0 μm) are grown sequentially. Furthermore, undoped G on top of this
aInAsP active layer 9 (wavelength 1.55 μm), p-In
P layer 10 (thickness 1.5 μm), p+ -GaInAsP
A layer 11 (thickness 0.3 μm) is grown and DH (Double
e. Heterostructure) laser structure was formed. InP layers 8 and 10 functioned as cladding layers, and GaInAsP layer 11 was provided to obtain ohmic contact. In this embodiment, the GaInP strained thin film is introduced three times, but the number is not limited to this number. Further, the GaInP strained thin films I to III all had a composition of Ga0.1In0.9P and a thickness of 10 nm, which was less than the critical film thickness. Even in this strained thin film, as shown in Figure 2, strain (ratio of lattice constant difference)
The composition is not limited to this, as long as an appropriate amount of strain and a thickness (region A) below the critical thickness are selected for the InP layer from the relationship between and the critical thickness. Also other materials (e.g. GaInAs, GaI
nAsP, etc.) may also be used. Furthermore, n+ -GaA
An appropriate intermediate layer may be inserted between the s-substrate 1 and the n-InP layer 21, or a two-stage growth process in which the n-InP layer 21 is initially grown at a low temperature may be adopted.

According to this embodiment, the number of threading dislocations in the n-InP layer 8 resulting from misfit dislocations generated at the interface between the n + -GaAs substrate 1 and the n-InP layer 21 is determined by thermal cycle annealing and the InP layer. The effect of the GaInP strained thin films I to III introduced therein resulted in a reduction of 20 to 30% compared to the conventional structure using a strained superlattice layer as shown in FIG. The dislocation density in the InP layer 8 according to this example is expressed as H3PO4
:HBr=5-7 when measured by etching with 2:1 solution
×106/cm2. Furthermore, compared to conventional strained superlattice structures, the strained layer is simplified to a single layer, making crystal growth easier. The characteristics of the device formed on the InP layer 8 are InP
Although it depends on the crystallinity of the layer 8, the laser characteristics of this example also showed improvements in threshold current value, life span, etc. compared to the conventional structure.

In this embodiment, a DH laser is placed on the n-InP layer 8.
Although the present invention is applicable to all cases in which layer structures corresponding to various devices are formed on this layer, the n- and p-type doping may be reversed. . In addition, although this example only showed the heteroepitaxy of InP on a GaAs substrate,
It may be on a GaAs layer epitaxially grown on another semiconductor substrate, such as GaAs on a Si substrate, InP on a Si substrate,
The present invention can also be applied to heteroepitaxy of other materials such as InAs on an InP substrate. Also III
It is applicable not only to -V group compound semiconductors but also to II-VI group compound semiconductors.

Example 2 Another embodiment of the invention will be explained with reference to FIG. 1 as well.

The basic layer structure and growth method are the same as in Example 1, so their explanation will be omitted. However, the composition of the GaInP strained layer I3 shown in FIG.
5P, and the thickness is 10 nm so that it is more than the critical film thickness.
I made it.

According to this example, the effect of reducing threading dislocations became more remarkable than in Example 1 by making the initial strained layer thickness equal to or greater than the critical film thickness shown in FIG. 2 (region B). This is because the propagation of threading dislocations is more effectively suppressed by the GaInP strained layer exceeding the critical film thickness, or the threading dislocations are bent in the lateral direction and disappear. Misfit dislocations that occur at the upper interface of this strained layer because the critical film thickness is exceeded propagate further to the next InP layer, but this dislocation is also inhibited from propagating by the next GaInP strained layer whose thickness is below the critical film thickness. decrease or disappear. The dislocation density of the InP layer 8 according to this example is 3~
The density was further reduced to 5×10 6 /cm 2 , and a high quality InP layer was obtained. Additionally, the laser characteristics were further improved.

Embodiment 3 Another embodiment of the present invention will be explained with reference to FIG. In this example, the strained superlattice layer is introduced twice (
After the layers 31 and 51), a single strained layer 7 is further formed. The other layer structure is the same as in Example 1. In the figure, the same reference numerals as in FIG. 1 indicate the same configurations. The strained superlattice layers 31 and 51 were composed of five periods of a Ga0.1In0.9P layer (50 Å) and an InP layer (50 Å). Even when the strained superlattice layer was introduced a plurality of times in this manner and only the uppermost strained layer was composed of a single strained layer, the same effect as in Example 1 was obtained. Of course, the number of times the strained superlattice layer and the single strained layer are introduced is not limited to the number of times used in this embodiment.

Embodiment 4 A case where the present invention is applied to an opto-electronic integrated device (OEIC) will be explained with reference to FIG. In the figure, the same reference numerals as in FIG. 1 indicate the same configurations.

A field effect transistor (FE) which functions as a laser drive circuit is provided on a part of the semi-insulating GaAs substrate 1a.
Form an ion implantation region T). After that, a part of the substrate is removed by etching as shown in the figure. Heteroepitaxy similar to that in Example 1 is performed on this etched portion to form a laser structure. The laser structure in this example is BH
(Buried Heterostructure)
A semi-insulating InP layer 13 was used as the buried layer. Thereafter, an etching process was performed, and then a SiO2 film 14 and an electrode 15 were formed to produce an OEIC.

The operation of driving a semiconductor laser using an FET in the OEIC according to this example was confirmed. This is because a high quality heteroepitaxial film can now be obtained due to the dislocation reduction effect of the present invention. It goes without saying that the application of the present invention is not limited to the structure of the OEIC shown in this embodiment.

[0021]

Effects of the Invention As explained above, in the present invention, the strained layer for the purpose of reducing threading dislocations is composed of a single strained layer with a thickness below the critical film thickness instead of the conventional strained superlattice layer. While having the effect of suppressing dislocations, no new misfit dislocations are generated at the interface of the strained layer. Therefore, it has the advantage that dislocations can be reduced more effectively and a high quality semiconductor layer can be easily obtained. Furthermore, the layer structure is simplified and crystal growth is easy.

Further, threading dislocations can be more effectively reduced by making at least one of the initial strained layers have a thickness equal to or greater than the critical thickness, and then introducing strained layers having a thickness equal to or less than the critical thickness. This is because most of the threading dislocations originating from a large number of misfit dislocations generated at the interface between the substrate and the growth layer are efficiently suppressed by the strained layer set to a thickness greater than or equal to the critical film thickness. Moreover, the misfit dislocations generated by this strained layer are also eliminated by the next strained layer having a thickness below the critical film thickness. Therefore, dislocations can be reduced more effectively and a semiconductor layer of higher quality can be obtained. Therefore, there is an advantage that the characteristics of devices formed on these semiconductor layers are improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a diagram showing the relationship between strain amount and critical film thickness.

FIG. 3 is a cross-sectional view of a semiconductor device showing another embodiment of the present invention.

FIG. 4 is a cross-sectional view of a conventional semiconductor device.

FIG. 5 is a cross-sectional view of a semiconductor device in which the present invention is applied to an optoelectronic integrated device.

[Explanation of symbols]

1...n+-GaAs substrate, 1a...semi-insulating GaAs substrate, 21, 22, 4, 6, 8...n-InP layer, 10...p-
InP layer, 3...n-GaInP strained layer I, 5...n-GaI
nP strained layer II, 7...n-GaInP strained layer III, 31,
51,71...Strained superlattice layer, 9...GaInAsP active layer,
11...p+-GaInAsP layer, 12...p-InP layer,
13... Semi-insulating InP layer, 14... SiO2 film, 15... Electrode, 16... Ion implantation region

Claims (16)

[Claims] 1. A first semiconductor layer having a first lattice constant, a second semiconductor layer having a second lattice constant, and dislocations disposed between the first and second semiconductor layers. 1. A semiconductor device comprising a dislocation reduction region, the dislocation reduction region having a single layer of a strained thin film. 2. A substrate, an active region made of a semiconductor having a lattice constant different from that of a semiconductor constituting the substrate, and a dislocation reduction region disposed between the substrate and the active region. 1. A semiconductor device comprising: a dislocation reduction region having a single layer of a strained thin film. 3. The semiconductor device according to claim 2, wherein the dislocation reduction region has a plurality of strained layers. 4. The semiconductor device according to claim 1, wherein the strained thin film has a thickness equal to or less than a critical thickness at which misfit dislocations begin to occur. 5. The semiconductor device according to claim 3, wherein at least one of the plurality of strained layers has a thickness equal to or greater than a critical thickness at which misfit dislocations begin to occur, and the other strained layers have a thickness equal to or less than the critical thickness. , and the strained layer having a thickness equal to or greater than a critical thickness is located closer to the substrate than the strained layer having a thickness equal to or less than the critical thickness at which misfit dislocations begin to occur. 6. The semiconductor device according to claim 1, wherein the dislocation reduction region has a strained superlattice structure. 7. A semiconductor device, wherein the semiconductor device according to claim 1 or 2 is an optoelectronic integrated device. 8. A first semiconductor substrate, an electronic device region provided on the first semiconductor substrate, a dislocation reduction region provided on the first semiconductor substrate, and a dislocation reduction region provided on the dislocation reduction region. and an optical element region provided in the semiconductor device, wherein the dislocation reduction region has a single-layer strained thin film. 9. An electronic element section having an electronic active region and an optical element section having an optical active region, the electronic element section being provided on a first semiconductor substrate region having a first lattice constant. , the optical element section is provided on a second semiconductor substrate region having a second lattice constant different from the first lattice constant,
A semiconductor device characterized in that a dislocation reduction region is disposed between the first and second semiconductor substrate regions, and the dislocation reduction region has a single layer of a strained thin film. 10. The semiconductor device according to claim 9,
A semiconductor device characterized in that the single-layer strained thin film has a thickness below a critical film thickness at which misfit dislocations begin to occur. 11. The semiconductor device according to claim 9,
A semiconductor device characterized in that the dislocation reduction region has a plurality of strained layers, and the single-layer strained thin film is disposed above the plurality of strained layers. 12. The semiconductor device according to claim 9,
A semiconductor device, wherein the dislocation reduction region has a plurality of layers of the single-layer strained thin film. 13. The semiconductor device according to claim 12, wherein the dislocation reduction region includes a semiconductor layer having a thickness of 0.1 μm or more and 2 μm or less, disposed between the plurality of strained thin films. semiconductor devices. 14. The semiconductor device according to claim 12, wherein the dislocation reduction region includes a semiconductor layer having a thickness of 0.2 μm or more and 1 μm or less, disposed between the plurality of strained thin films. semiconductor devices. 15. The semiconductor device according to claim 9,
A semiconductor device, wherein the dislocation reduction region is disposed on a recess formed in the first semiconductor substrate region. 16. The semiconductor device according to claim 9,
A semiconductor device, wherein the electronic element section and the optical element section are formed on substantially the same surface.