JPH0429558A - Gate drive circuit of voltage driven type semi-conductor element - Google Patents

Gate drive circuit of voltage driven type semi-conductor element

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Publication number
JPH0429558A
JPH0429558A JP13442190A JP13442190A JPH0429558A JP H0429558 A JPH0429558 A JP H0429558A JP 13442190 A JP13442190 A JP 13442190A JP 13442190 A JP13442190 A JP 13442190A JP H0429558 A JPH0429558 A JP H0429558A
Authority
JP
Japan
Prior art keywords
voltage
gate
gate voltage
semiconductor element
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13442190A
Other languages
Japanese (ja)
Inventor
Takafumi Kawai
河合 隆文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP13442190A priority Critical patent/JPH0429558A/en
Publication of JPH0429558A publication Critical patent/JPH0429558A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce a loss (at the time of ON) in a regular time while minimizing a sharp rise of a main circuit voltage at the time of switching, by providing a means of making the absolute value of a gate voltage of a semiconductor element rather low at the time of turn-OFF of the element and increasing this absolute value of the gate voltage gradually when the element turns in an OFF state and a means of increasing the absolute value of the gate voltage gradually at the time of turn-OFF. CONSTITUTION:When a signal input 01 changes from an OFF instruction over to an ON instruction, a reverse bias switch 3-2 turns OFF and a forward bias switch 3-1 turns ON. In this initial state, an equivalent capacity CS being parasitic between a gate G and an emitter E of a voltage driven type semiconductor element 6 is charged with electricity of a voltage -E2. Besides, a voltage E1 of a forward bias power source 1 is impressed between the gate G and the emitter E of the voltage driven type semiconductor element 6. In this case, a gate voltage VGE rises at the initial value -E2, a final achievable target value E1 - VZD1 and a time constant CS XRG. Thereafter, the gate voltage VGE increases, a charging current of the equivalent capacity CS decreases, a Zener diode ZD 1 is thereby put in an OFF state, and the gate voltage rises gradually at a final achievable value E1 and a time constant CS X(RG + R1).

Description

【発明の詳細な説明】[Detailed description of the invention] 【産業上の利用分野】[Industrial application field]

この発明はI(1,BT、FETなどの電圧駆動形半導
体素子のスイッチング(ターンオン、ターンオフ)のた
めにこの半導体素子のゲートを駆動する回路、 特にこのスイッチング時における主回路電圧のはね上が
りを抑制し、また定常時はこの半導体素子のオン、オフ
の安定度を高め得るようにした電圧駆動形半導体素子の
ゲート駆動回路に関する。 なお以下各図において同一の符号は同一もしくは相当部
分を示す。
This invention is a circuit that drives the gate of a voltage-driven semiconductor element such as I(1, BT, FET, etc.) for switching (turn-on, turn-off) this semiconductor element, and in particular suppresses the rise in main circuit voltage during this switching. The present invention also relates to a gate drive circuit for a voltage-driven semiconductor device that is capable of increasing the on/off stability of the semiconductor device during steady state.The same reference numerals in the following figures indicate the same or corresponding parts.

【従来の技術】[Conventional technology]

第3図は電圧駆動形半導体素子の従来のゲート駆動回路
を示す。同図において外部よりロジック演算回路5に電
圧駆動形半導体素子6へのオン・オフ指令01が入力さ
れると、ロジック演算回路5では信号人力01を絶縁増
巾し、順逆切換スイッチ3に必要なオン・オフ信号5a
として伝達する。 ここでオン指令の場合、順逆切換スイッチ3内の順バイ
アススイッチ3−1がオンし、順バイアス電源1の電圧
E1が、ゲート抵抗RGを介し、電圧駆動形半導体素子
6のゲー)GとエミッタEとの間に順バイアスの電圧と
して加わる。 他方、オフ指令の場合、順逆切換スイッチ3内の逆バイ
アススイッチ3−2がオンし、逆バイアス電源2の電圧
E2が、ゲート抵抗RGを介し、電圧駆動形半導体素子
6のゲートG、エミッタE間に逆バイアスの電圧−E2
として加わる。但し以上の動作において順バイアススイ
ッチ3−1と逆バイアススイッチ3−2が同時にオンし
て、順バイアス電源Elと逆バイアス電源E2が短絡し
ないように、ロジック演算回路5が制御している。 第4図は第3図の回路における半導体素子6のゲート電
圧波形の例を示す、但しこの電圧制御形半導体素子6は
ゲート電圧VGtが正電圧のときオンする素子とする。 ロジック演算回路5への信号人力01がオン指令になる
と、順逆切換スイッチ3により、ゲート電圧v、tは−
E2からElへと切り換わり、電圧制御形半導体素子6
はオンする。 但しゲート抵抗RGと電圧制御形半導体素子6のゲート
G、エミッタE間の等価容量C3により、ゲート電圧V
GEはある時定数をもって切り換わる。 また信号人力01がオフ指令になると、同様にある時定
数をもって、ゲート電圧vGxはElから−E2へと切
り換わり、電圧制御形半導体素子6はオフする。
FIG. 3 shows a conventional gate drive circuit for a voltage-driven semiconductor device. In the same figure, when an on/off command 01 to the voltage-driven semiconductor element 6 is inputted to the logic operation circuit 5 from the outside, the logic operation circuit 5 insulates and amplifies the signal input 01, On/off signal 5a
Communicate as. In the case of an on command, the forward bias switch 3-1 in the forward/reverse changeover switch 3 is turned on, and the voltage E1 of the forward bias power supply 1 is applied to the gate (G) and emitter of the voltage-driven semiconductor element 6 via the gate resistor RG. It is applied as a forward bias voltage between E and E. On the other hand, in the case of an off command, the reverse bias switch 3-2 in the forward/reverse changeover switch 3 is turned on, and the voltage E2 of the reverse bias power supply 2 is applied to the gate G and emitter E of the voltage-driven semiconductor element 6 via the gate resistor RG. Reverse bias voltage between −E2
Join as. However, in the above operation, the logic operation circuit 5 controls so that the forward bias switch 3-1 and the reverse bias switch 3-2 are turned on at the same time and the forward bias power source El and the reverse bias power source E2 are not short-circuited. FIG. 4 shows an example of the gate voltage waveform of the semiconductor element 6 in the circuit of FIG. 3. However, this voltage-controlled semiconductor element 6 is an element that turns on when the gate voltage VGt is a positive voltage. When the signal 01 to the logic operation circuit 5 is turned on, the forward/reverse changeover switch 3 changes the gate voltages v and t to -
Switching from E2 to El, the voltage controlled semiconductor element 6
turns on. However, due to the gate resistance RG and the equivalent capacitance C3 between the gate G and emitter E of the voltage-controlled semiconductor element 6, the gate voltage V
GE switches with a certain time constant. When the signal input 01 becomes an off command, the gate voltage vGx similarly switches from El to -E2 with a certain time constant, and the voltage-controlled semiconductor element 6 turns off.

【発明が解決しようとする課8】 しかしながら第3図のゲート駆動回路では順バイアス電
源電圧El、逆バイアス電源電圧−E2は固定であり、
このゲート電圧を高めると、電圧駆動形半導体素子は定
常時、ノイズ等による外乱を受は難くなり、そのオン、
オフの動作状態の安定度が高まり、スイッチング速度も
速くなるが、他方スイッチング速度が速いと、主回路の
配線インダクタンスによる電圧のはね上がりが太き(な
り、素子の絶対最大定格電圧を越えてしまう場合がある
。 これはターンオフ時は、電源より電圧制御形半導体素子
までの前記配線インダクタンスのため、電流が減少する
ことにより、この配線インダクタンスのエネルギが電圧
のはね上がりを惹起し、他方、ターンオン時は、ブリッ
ジ結線のインバータ回路等の場合、対向アームのダイオ
ードにフライホイルモードの電流が流れていた時に、電
圧制御形半導体素子のターンオンにより、そのターンオ
ンした素子に電流が転流し、対向アームのダイオードの
逆回復時の電圧のはね上がりを生ずるためである。 またゲート抵抗RGを大きくすれば、スイ・プチング速
度が遅くなり、主回路の配線インダクタンスによる電圧
のはね上がりは小さくなるが、スイッチング速度が遅く
なる影響でスイッチング損失が増大するという悪影響が
ある。 そこで本発明はこの問題を解消し得る電圧駆動形半導体
素子のゲート駆動回路を提供することを課題とする。
[Problem to be Solved by the Invention 8] However, in the gate drive circuit shown in FIG. 3, the forward bias power supply voltage El and the reverse bias power supply voltage -E2 are fixed,
When this gate voltage is increased, the voltage-driven semiconductor element becomes less susceptible to disturbances such as noise during steady state, and its on-state and
The stability of the off-state operating state increases and the switching speed increases, but on the other hand, when the switching speed is high, the voltage jump due to the wiring inductance of the main circuit increases (and may exceed the absolute maximum rated voltage of the element). This is because at turn-off, due to the wiring inductance from the power supply to the voltage-controlled semiconductor element, the current decreases, and the energy of this wiring inductance causes a voltage jump; on the other hand, at turn-on, In the case of a bridge-connected inverter circuit, etc., when a flywheel mode current is flowing through the diode in the opposing arm, when the voltage-controlled semiconductor element turns on, the current is commutated to the turned-on element, and the reverse flow of the diode in the opposing arm occurs. This is because a voltage jump occurs during recovery.Also, if the gate resistance RG is increased, the switching speed will be slowed down, and the voltage jump due to the wiring inductance of the main circuit will be reduced, but due to the effect of slowing the switching speed. This has the adverse effect of increasing switching loss.An object of the present invention is therefore to provide a gate drive circuit for a voltage-driven semiconductor element that can solve this problem.

【課題を解決するための手段] 前記の課題を解決するために本発明の回路は、rゲート
電圧の2つの極性に応じてそれぞれオン9オフする電圧
駆動形半導体素子のゲートを駆動する回路において、 前記半導体素子のターンオフ時にそのゲート電圧の絶対
値を低目にし、この半導体素子が定常のオフ状態に入る
と徐々にこのゲート電圧の絶対値を上げる手段(ツェナ
ダイオードZD2.抵抗R2など)、および前記半導体
素子のターンオン時にそのゲート電圧の絶対値を低目に
し、この半導体素子が定常のオン状態に入ると、徐々に
このゲート電圧の絶対値を上げる手段(ツェナダイオー
ドZDI、抵抗R1など)を備えたJものとする。 【作 用】 第2図は本発明による電圧駆動形半導体素子に印加させ
るゲート電圧V、の波形図である。信号人力01がオフ
指令からオン指令に切り換ると、ゲート電圧■1はある
時定数τ1にて、最終到達ゲート電圧E1より小さい値
(第2図では1/2E、)を目標に立ち上がる。そのの
ちターンオン完了前後に1/2E、から再びElを目標
にある時定数τ2(τ、〉τI)でゲート電圧は増加す
る。これにより、ターンオン時は速すぎないターンオン
時間のため、電圧のはね上がりが最適値に納まり、また
定常オン時は高いゲート電圧のため、外乱に強い安定し
たオン状態と、電圧駆動形半導体素子の低飽和電圧(低
損失)とが得られる。 また同様に信号人力01がオン指令からオフ指令に切り
換ると、ゲート電圧VGEはある時定数τ。 にて最終到達ゲート電圧−E2より絶対値が小さい値(
第2図では−t/2Ez)を目標に立ち上がる。 その後ターンオフ完了前後に一1/2EZから再びE2
を目標にある時定数τ4(τ4〉τ3)でゲート電圧の
絶対値は増加する。これによりターンオフ時は速すぎな
いターンオフ時間のため、電圧のはね上がりが最適値に
納まり、また定常オフ時には十分絶対値の大きなゲート
電圧のため、電圧駆動形半導体素子は外乱に強い安定し
たオフ状態となる。
[Means for Solving the Problems] In order to solve the above problems, the circuit of the present invention is a circuit for driving the gate of a voltage-driven semiconductor element that turns on and off depending on two polarities of the r gate voltage. , means for lowering the absolute value of the gate voltage when the semiconductor element is turned off, and gradually increasing the absolute value of the gate voltage when the semiconductor element enters a steady OFF state (Zena diode ZD2, resistor R2, etc.); and a means (Zena diode ZDI, resistor R1, etc.) that lowers the absolute value of the gate voltage when the semiconductor element is turned on, and gradually increases the absolute value of the gate voltage when the semiconductor element enters a steady on state. Let J with . [Operation] FIG. 2 is a waveform diagram of the gate voltage V applied to the voltage-driven semiconductor element according to the present invention. When the signal power 01 switches from the off command to the on command, the gate voltage ■1 rises with a certain time constant τ1, aiming at a value smaller than the final gate voltage E1 (1/2E in FIG. 2). Thereafter, the gate voltage increases from 1/2E before and after turn-on is completed, again with a time constant τ2 (τ,>τI) aiming at El. As a result, the turn-on time is not too fast during turn-on, so the voltage jump is kept within the optimum value, and the high gate voltage during steady-on operation provides a stable on state that is resistant to external disturbances and a low voltage drive type semiconductor device. Saturation voltage (low loss) can be obtained. Similarly, when the signal human power 01 switches from an on command to an off command, the gate voltage VGE has a certain time constant τ. A value whose absolute value is smaller than the final reached gate voltage -E2 at (
In Fig. 2, the target is -t/2Ez). After that, E2 again from 1 1/2 EZ before and after the turn-off is completed.
The absolute value of the gate voltage increases with a certain time constant τ4 (τ4>τ3). As a result, at turn-off, the turn-off time is not too fast, so the voltage jump is within the optimum value, and at steady-state off, the gate voltage has a sufficiently large absolute value, so voltage-driven semiconductor devices can maintain a stable off-state that is resistant to external disturbances. Become.

【実施例】【Example】

第1図は本発明の一実施例としての回路図で、第3図に
対応するものである。第1図においては第3図に対し順
バイアススイッチ3−1に直列に抵抗R1が挿入され、
さらにこの抵抗R1に並列に、かつ順バイアス電源1を
阻止する極性にツェナダイオードZDIが接続されてい
る。そしてまた逆バイアススイッチ3−2にも同様に直
列に抵抗R2が挿入され、さらにこの抵抗R2と並列に
、かつ逆バイアス電源2を阻止する極性にツェナダイオ
ードZD2が接続されている。 ロジック演算回路5に与えられる信号人力01がオフ指
令より、オン指令に切換ねると、逆バイアススイッチ3
−2がオフ、順バイアススイッチ31がオンとなる。こ
の初期状態では電圧駆動形半導体素子6のゲートG、エ
ミッタE間に寄生する等価容量C5は−E2の電圧に充
電されている。 またツェナダイオードZDIのツェナ電圧v2DIは順
バイアス電源電圧E、より低い電圧値に設定しである。 従って始めはツェナダイオードZDIがオンすることに
なり、順バイアス電源1の電圧E、は順バイアススイッ
チ3−1.ツェナダイオードZD1.ゲート抵抗R,を
通り、電圧駆動形半導体素子6のゲートG、エミッタE
間に印加される。この場合、ゲート電圧vexは初期値
−E2.最終到達目標値E、 −V、□9時定数c、X
Reで(つまり速すぎない立上がり時間で)立ち上がる
。その後、ゲート電圧■、が増大し、等価容量C3の充
tii流が減少して、この充電を流による抵抗R1の電
圧降下がツェナ電圧■2ゎ、以下の状態になると、ツェ
ナダイオードZDIはオフ状態となり、ゲート電圧■1
は最終到達値Elf時定数C8x (RG +Rυにて
ゆっくりと上昇していく。 他方、信号人力01がオン指令よりオフ指令に切換る時
も同様で、順バイアススイッチ3−1がオフ、逆バイア
ススイッチ3−2がオンとなり、等価容量C5が反転充
電される。この場合、ツェナダイオードZD2のツェナ
電圧v2□は逆バイアス電源2の電圧E2より低い電圧
値に設定されているので、初めはツェナダイオードZD
2がオンすることにより、ゲート電圧■Gやは初期値E
1.最終到達値−(E2−V2D、)、時定数Cs X
 Rc T: (ツまり速すぎない立下がり時間で)立
下り、その後、ツェナダイオードZD2がオフすると、
ゲート電圧■1は最終到達値−E2.時定数c s x
 (RG+R,)にてゆっくりと下降していく。 このように適当なEI+  EIV2DI+VZ11Z
+R1+R2,R,の値を選べば、第2図のタイムチャ
ートが得られることになる。
FIG. 1 is a circuit diagram as an embodiment of the present invention, and corresponds to FIG. 3. In FIG. 1, in contrast to FIG. 3, a resistor R1 is inserted in series with the forward bias switch 3-1,
Furthermore, a Zener diode ZDI is connected in parallel with this resistor R1 and has a polarity that blocks the forward bias power supply 1. Similarly, a resistor R2 is inserted in series with the reverse bias switch 3-2, and a Zener diode ZD2 is connected in parallel with the resistor R2 and has a polarity that blocks the reverse bias power supply 2. When the signal 01 given to the logic operation circuit 5 switches from the off command to the on command, the reverse bias switch 3
-2 is turned off, and the forward bias switch 31 is turned on. In this initial state, the equivalent capacitance C5 parasitic between the gate G and emitter E of the voltage-driven semiconductor element 6 is charged to a voltage of -E2. Furthermore, the Zener voltage v2DI of the Zener diode ZDI is set to a lower voltage value than the forward bias power supply voltage E. Therefore, the Zener diode ZDI is initially turned on, and the voltage E of the forward bias power supply 1 is changed to the forward bias switch 3-1. Zener diode ZD1. Passing through the gate resistor R, the gate G and emitter E of the voltage-driven semiconductor element 6
applied in between. In this case, the gate voltage vex is the initial value -E2. Final target value E, -V, □9 time constant c, X
It rises at Re (that is, with a rise time that is not too fast). After that, the gate voltage (2) increases, the charging current of the equivalent capacitance C3 decreases, and when the voltage drop across the resistor R1 due to this charging current becomes less than the Zener voltage (2), the Zener diode ZDI turns off. state, and the gate voltage ■1
is the final reached value Elf time constant C8x (RG + Rυ). On the other hand, when the signal human power 01 switches from the on command to the off command, the forward bias switch 3-1 is turned off and the reverse bias is turned off. The switch 3-2 is turned on, and the equivalent capacitance C5 is reversely charged.In this case, since the Zener voltage v2□ of the Zener diode ZD2 is set to a voltage value lower than the voltage E2 of the reverse bias power supply 2, the Zener voltage V2□ is initially Diode ZD
2 turns on, the gate voltage ■G becomes the initial value E
1. Final reached value - (E2 - V2D,), time constant Cs
Rc T: falls (with a falling time that is not too fast), then when Zener diode ZD2 turns off,
Gate voltage ■1 is the final reached value -E2. time constant c s x
It slowly descends at (RG+R,). In this way, suitable EI + EIV2DI + VZ11Z
If the value of +R1+R2,R, is selected, the time chart shown in FIG. 2 will be obtained.

【発明の効果】【Effect of the invention】

本発明によれば、スイッチング時にゲート電圧の立上が
り(立下り)時間を増加させずにその絶対値を低目にし
、スイッチング完了前後より、ゲート電圧を高く変化さ
せるようにしたので、従来のゲート駆動回路に若干の部
品を追加するのみで、スイッチング時の主回路電圧のは
ね上がりを最小限にしながら、定常時の電圧駆動形半導
体素子の損失(オン時)の減少ができ、かつ外乱に強い
ゲート駆動回路を実現することができる。
According to the present invention, the absolute value of the gate voltage is made low without increasing the rise (fall) time of the gate voltage during switching, and the gate voltage is changed higher than before and after the completion of switching. By simply adding a few components to the circuit, it is possible to minimize the rise in main circuit voltage during switching, reduce the loss (when on) of voltage-driven semiconductor elements in steady state, and provide a gate drive that is resistant to external disturbances. The circuit can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例としての回路図、第2図は同
じく第1図に基づくゲート電圧のタイムチャート、 第3図は第1図に対応する従来の回路図、第4図は第3
図に基づくゲート電圧の例を示すタイムチャートである
。 01:信号入力、1:順バイアス電源、2:逆バイアス
ミ源、3:順逆切換スイッチ、3−1:順バイアススイ
ッチ、3−2二逆バイアススイツチ、RG :ゲート抵
抗、5:ロジック演算回路、6:電圧駆動形半導体素子
、ZDI、ZD2 :ツエナダイオード、R1,R2:
抵抗、C5:等価容量。 第3図 第4図
FIG. 1 is a circuit diagram as an embodiment of the present invention, FIG. 2 is a gate voltage time chart based on FIG. 1, FIG. 3 is a conventional circuit diagram corresponding to FIG. 1, and FIG. Third
5 is a time chart showing an example of gate voltage based on the figure. 01: Signal input, 1: Forward bias power supply, 2: Reverse bias source, 3: Forward/reverse changeover switch, 3-1: Forward bias switch, 3-2 two reverse bias switches, RG: Gate resistance, 5: Logic operation circuit, 6: Voltage driven semiconductor element, ZDI, ZD2: Zener diode, R1, R2:
Resistance, C5: equivalent capacitance. Figure 3 Figure 4

Claims (1)

【特許請求の範囲】 1)ゲート電圧の2つの極性に応じてそれぞれオン,オ
フする電圧駆動形半導体素子のゲートを駆動する回路に
おいて、 前記半導体素子のターンオフ時にそのゲート電圧の絶対
値を低目にし、この半導体素子が定常のオフ状態に入る
と徐々にこのゲート電圧の絶対値を上げる手段、および
前記半導体素子のターンオン時にそのゲート電圧の絶対
値を低目にし、この半導体素子が定常のオン状態に入る
と、徐々にこのゲート電圧の絶対値を上げる手段を備え
たことを特徴とする電圧駆動形半導体素子のゲート駆動
回路。
[Claims] 1) In a circuit that drives the gate of a voltage-driven semiconductor element that turns on and off depending on two polarities of the gate voltage, the absolute value of the gate voltage is set to a low level when the semiconductor element is turned off. means for gradually increasing the absolute value of the gate voltage when the semiconductor element enters a steady OFF state, and a means for lowering the absolute value of the gate voltage when the semiconductor element is turned on, so that the semiconductor element enters a steady ON state. 1. A gate drive circuit for a voltage-driven semiconductor device, comprising means for gradually increasing the absolute value of the gate voltage when the gate voltage enters a state.
JP13442190A 1990-05-24 1990-05-24 Gate drive circuit of voltage driven type semi-conductor element Pending JPH0429558A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13442190A JPH0429558A (en) 1990-05-24 1990-05-24 Gate drive circuit of voltage driven type semi-conductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13442190A JPH0429558A (en) 1990-05-24 1990-05-24 Gate drive circuit of voltage driven type semi-conductor element

Publications (1)

Publication Number Publication Date
JPH0429558A true JPH0429558A (en) 1992-01-31

Family

ID=15127997

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13442190A Pending JPH0429558A (en) 1990-05-24 1990-05-24 Gate drive circuit of voltage driven type semi-conductor element

Country Status (1)

Country Link
JP (1) JPH0429558A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7710187B2 (en) 2007-09-12 2010-05-04 Mitsubishi Electric Corporation Gate drive circuit
US9461640B2 (en) 2012-12-21 2016-10-04 Mitsubishi Electric Corporation Switching element drive circuit, power module, and automobile

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7710187B2 (en) 2007-09-12 2010-05-04 Mitsubishi Electric Corporation Gate drive circuit
US8610485B2 (en) 2007-09-12 2013-12-17 Mitsubishi Electric Corporation Gate drive circuit
US9461640B2 (en) 2012-12-21 2016-10-04 Mitsubishi Electric Corporation Switching element drive circuit, power module, and automobile
DE112012007247B4 (en) 2012-12-21 2022-11-10 Mitsubishi Electric Corporation Control circuit for a switching element, power module and motor vehicle

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