JPH0429486A - Time base correcting circuit for video signal - Google Patents

Abstract

PURPOSE:To accurately eliminate the jitter and to stabilize a circuit by eliminating the high frequency component of the phase distortion from a first pilot signal by a first phase distortion correcting means and outputting the result as a second pilot signal and modulating the phase of this signal by a second phase distortion correcting means. CONSTITUTION:When the output signal of a frequency dividing circuit 25 is supplied to the other input terminal of a phase comparing circuit 21, a signal thetae indicating the phase difference is outputted from the phase comparing circuit 25. This signal thetae has the high frequency component eliminated by a loop filter 22. A phase error detecting circuit 33 detects and outputs the phase error (jitter) between a horizontal synchronizing signal and a write signal WCK. The value of this jitter is latched in a latch circuit 32 and is converted to a voltage signal VT through a DAC 31 and is outputted. This voltage signal VT is supplied to a phase modulating circuit 27 through a loop filter 29. Thus, the operation is stabilized because the loop gain of one PLL circuit is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a video signal time axis correction circuit suitable for use in a MUSE type video disc player.

"Conventional Technology" In recent years, so-called high-definition television (high-definition television) has become widespread as a video technology for professional use, and it is expected that it will become widespread in consumer equipment in the future.

Therefore, it is desired to develop a video disc player that can play high-definition video. However, since the bandwidth of high-definition video exceeds 20 MHz, it is considered advantageous to convert it to a MUSE signal, compress the bandwidth to about 8 MHz, and perform FM modulation before recording, rather than recording it as is.

By the way, jitter (phase distortion) inevitably occurs in the reproduction signal of a video disc player due to drive errors in the rotation system of the video disc or eccentricity of the disc. For this reason, in current NTSC video disc players, time axis correction (jitter correction) is performed by using a horizontal synchronization signal or a color burst signal for phase detection.

However, since the MUSE system was originally developed as a band compression technology for satellite broadcasting, a positive synchronization system in which the synchronization signal level is within the video signal level is adopted in order to increase the S/N ratio. Therefore, it is difficult to detect a synchronization signal by amplitude separation as in the current NTSC system. Furthermore, the MUSE signal is not provided with anything equivalent to a color burst signal.

Therefore, the pilot signal (pilot carrier) is
A technique has been developed in which the pilot signal is superimposed on the SE signal and time base correction is performed based on this pilot signal. Here, the pilot signal frequency f9 is the horizontal synchronization signal frequency f, 4(-3
3,75kHz) and in an interleaved relationship (
It is preferable to set the value to be a half-integer multiple (in order to prevent vertical striped noise from occurring on the screen), so f, = (135/2) f,! = 2.2781
A frequency of 25 MHz −=equation (+) is selected. In addition, the level of the pilot signal is set to FM modulated MUSE so as not to generate beats etc. in the playback output.
It is set to -20 dB or less with respect to the signal.

The time base correction technique using this pilot signal will be briefly explained. First, separate the pilot signal from the MUSE signal, and from the separated pilot signal f w = 480 f
H= 18.2MHz ”'”'Formula (2
) generate a write signal having a write frequency f,
The MUSE signal is sampled in synchronization with this write signal. Here, since the pilot signal separated from the MUSE signal contains jitter generated in the rotation system, which is also included in the MUSE signal, the write signal generated from this also contains jitter. sampled M
The USE signal is sequentially written into the memory in synchronization with the write signal. Next, using a crystal oscillator etc., f R = f W = 16.2 MHz
--- A read signal having a read frequency of 1.8 as shown in equation (3) is generated, and the contents of the memory are read out and DA-converted in synchronization with this read signal. Since this read signal does not include jitter, the D
The A-converted 1 MUSE signal is in a state in which jitter has been removed.

By the way, the technique described above is based on the premise that the jitter of the pilot signal (or write signal) and the jitter of the MUSE signal are completely synchronized. However, it is known that in reality, the jitter of the pilot signal and the jitter of the MUSE signal are not completely synchronized. The reason for this will be explained below.

(i) First, although the MUSE signal is band-compressed compared to high-definition signals, it has a relatively wide band (approximately 8 MHz).
z). Therefore, it is difficult to provide perfect linear characteristics to a transmission system for recording (cutting) and reproducing video discs. If the transmission characteristics are non-linear, the level of the pilot signal is set to be extremely low (-20 dB or less).1 As a result, the pilot signal is phase modulated under the influence of the M [J S E signal, and the new r This phase distortion occurs in the pilot signal.

(11) By making the level of the pilot signal extremely low, the S/N ratio inevitably decreases.

As a result, even if it is assumed that there is no phase distortion as described in (i) above, a phase error is added to the pilot signal.

(Mountain) To generate a write signal from a pilot signal,
- PLL (phase locked loop) circuits are used for boat fishing. In this PLL circuit, the write frequency f changes following the change in the pilot frequency f9. However, when the pilot frequency f changes,
A certain amount of follow-up period is required until the write frequency f8 is completely synchronized with the pilot frequency f2. That is, during this follow-up period, the write signal is not synchronized with the MUSE signal.

For reasons (i) to (mountains) above, a write signal that is simply phase-synchronized with the pyro note signal has a jitter of about 60 nsec (1 clock of a 12.6 MHz write signal) at maximum, although it varies depending on the circuit configuration. remains. Therefore, this write signal is no longer synchronized with the sample point of the MUSE signal, which assumes sample value transmission, and eventually D
The A-converted MUSE signal is accompanied by waveform distortion.

In view of the above-mentioned circumstances, various time axis correction techniques have been proposed as described below.

■According to the technology disclosed in Japanese Patent Application Laid-open No. 1-95681, first, a jitter correction mirror is provided in the path of a laser beam for reading a video disc, and this jitter correction mirror is driven based on the phase fluctuation of a pilot signal. By doing this, coarse time correction is performed. Furthermore, the MUSE decoder connected to the video disc player plays MUS.
Highly accurate jitter correction is performed by detecting the phase fluctuation of the horizontal synchronization signal of the E signal and feeding back the detection result to the drive circuit of the jitter correction mirror.

■At the 1988 National Conference of the Television Society 8-19, a technique was proposed to remove jitter, which could not be removed by a video disc player, in a MUSE decoder. Specifically, the amount of jitter is determined by the playback MU.
It is detected from the phase error of the horizontal synchronization signal of the SE signal (in this respect it is the same as the above-mentioned prior art ①), and based on the detection result, the phase of the sampling clock of the AD converter for sampling the MUSE signal is controlled. do. Furthermore, three stages of registers connected in series are provided after the AD converter, and jitter is corrected by sequentially latching the sampling results while controlling the phases of the operating clocks of these registers.

"Problems to be Solved by the Invention" By the way, according to the above-mentioned prior art (2), jitter is detected using a pilot signal and a horizontal synchronization signal, but as a jitter correction means, only one jitter correction mirror is provided. It is. Therefore, there is a problem in that the loop gain inevitably becomes large and it is difficult to avoid unstable operation. Furthermore, since the jitter correction is performed using a mechanical structure, there is a drawback that accuracy and durability are poor.

Further, according to the prior art (2), the configuration of the MUSE decoder is extremely complicated and has the disadvantage of being expensive.

The present invention has been made in view of the above-mentioned circumstances, and is capable of accurately removing jitter, has excellent stability, and
It is an object of the present invention to provide a video signal time base correction circuit that can be manufactured at low cost.

"Means for Solving the Problems" In order to solve the above problems, the present invention provides a method for reproducing a video signal in which a main signal including a synchronization signal and a first pilot signal of a predetermined period are superimposed. A time axis correction circuit that temporarily stores the signal by synchronizing it with a write clock that follows the main signal and removes phase distortion caused by a rotation system, etc. by reading it out using a reference clock adds newly generated phase distortion after signal separation. a first phase distortion correction means for removing a high frequency component of the newly generated phase distortion from the first biloft signal and outputting it as a second pilot signal; a second phase that detects a phase difference between the synchronization signal and the second pilot signal, phase-modulates the second pilot signal so that this phase difference becomes small, and outputs it as a write clock; It is characterized by comprising a distortion correction means.

"Operation" First, the first phase distortion correction means removes a high frequency component of phase distortion from the first pilot signal and outputs it as a second pilot signal.

Next, the second phase distortion correction means extracts the synchronization signal from the main signal, detects the phase difference between this synchronization signal and the second pilot signal, and adjusts the second pilot signal so that this phase difference becomes small. phase modulate the pilot signal. Therefore, the residual component of phase distortion is removed by the second phase distortion correction means.

"Example" Next, one embodiment of the present invention will be described with reference to FIG.

A. MUSE Signal Regeneration First, the basic configuration for reproducing the MTJSE signal will be explained. In FIG. 1, reference numeral 1 denotes a video disk on which an FM-modulated MUSE signal is recorded, and is rotated by a spindle motor 17 at a predetermined speed.

2 is a pickup, which emits a laser beam onto the track of the video disc 1 and detects the reflected light.
Read the modulated MUSE signal. This FM modulated MUSE signal is amplified by the head amplifier 3,
(bypass filter) 4 and an RF equalizer 5 to form a waveform, and then PM demodulated in an FM demodulation circuit 6.

Next, the MUSEi signal output from the FM demodulation circuit 6 is L
The signal is supplied to an ADC (analog/digital converter) 8 via a PP (low pass filter) 7. On the other hand, A
A write signal WCK is supplied from the phase modulation circuit 27 to DC8. This write signal WCK is r,=+6
．． It has a frequency of 2 MHz (see equation (2)), and the MUSE signal is sampled in synchronization with this frequency. The sampling results are then sequentially supplied to the memory 9. A write signal WCK is also supplied to the memory 9 from the phase modulation circuit 27, and in synchronization with this, the sampling results of the MUSE signal are sequentially written.

Next, 13 is a reference clock oscillator, and a write signal W
A continuous signal RCK having the same frequency as CK and containing no jitter is output. In synchronization with this successive signal RCK,
The contents of the memory 9 are read out in the order in which they were written, and the successive results are latched into the latch circuit 10. Then, the output signal of the latch circuit 0 is converted to an analog signal via the DAC (digital/analog converter) 11, and the LP
It is output as a MUSE signal via F (low pass filter) 12.

B. Configuration of spindle motor drive system Next, a configuration for rotating the spindle motor 17 at a constant speed will be described.

First, 18 is a pilot detection circuit which extracts a pilot signal of frequency fp (see equation (1)) from the output signal of the head amplifier 3 and outputs it.

This pilot signal is converted to a predetermined frequency via the frequency dividing circuit 36 and is supplied to one input terminal of the phase comparison circuit 15. On the other hand, the continuous output signal RCK outputted from the reference clock oscillator 13 is converted to the above-mentioned predetermined frequency via the frequency dividing circuit 14, and is supplied to the other input terminal of the phase comparison circuit 15.

Next, the phase comparator circuit 15 detects the phase difference between the output signals of the frequency dividing circuit 36.14 and supplies it to the motor driver 16. Then, the motor driver 16 adjusts the rotation speed of the spindle motor 17 so that this phase difference becomes small.

As a result, the rotation speed of the spindle motor 17 becomes constant in synchronization with the read signal RCK.

C. Configuration of PLL Circuit 20 Next, details of jitter correction by the PLL circuit 20 and the like will be explained.

First, the frequency f output from the pilot detection circuit 18
The P pilot signal is frequency-divided by 18 via the frequency dividing circuit 19 and supplied to one input terminal of the phase comparison circuit 21 . That is, the frequency of the output signal of the frequency divider circuit 19 is f p / 18 = 126.5625 kHz
・--Equation (4) is obtained. Although the details will be described later, a signal having the same frequency as this is also output from the frequency dividing circuit 25. Then, the output signal of the frequency dividing circuit 25 or the phase comparator circuit 21
When supplied to the other input terminal, a signal θ indicating the phase difference of the rain sound is generated.
, is output from the phase comparator circuit 25.

The high frequency component of this signal θ is removed through a loop filter 22, and the signal is applied to a vCO (li pressure controlled oscillator) 23 as a voltage signal v6. vC023 is 97.2M
It is a Hz oscillator, and the oscillation frequency is finely adjusted by the voltage signal Va. Next, the output signal of VCO23 is
The frequency is divided by 6 through the frequency dividing circuit 24, and the frequency is 16.
It becomes 2MHz. Next, the output signal of the frequency dividing circuit 24 is divided by 128 via the frequency dividing circuit 25, and the frequency is divided by 128.
6.5625 kHz and is supplied to the other input terminal of the phase comparator circuit 21. This frequency is equal to the frequency of the output signal of the frequency dividing circuit 18 (see equation (4)). Furthermore, if there is a phase difference between the two signals, this phase difference is output as the signal θ from the phase comparator circuit 21, and the loop filter 22 and VC0
23 are sequentially controlled so that the phases match. In this way, each of the above-mentioned components 21 to 25 is a PLL-
(phase locked loop) circuit 20 is configured.

By the way, the frequency of the pilot signal extracted via the pilot detection circuit 18 is always the pilot frequency rp
(see equation (1)), and includes jitter due to various factors.

This jitter is caused by (i) components caused by eccentricity of the video disc l or fluctuations in the rotation speed of the spindle motor 17 (hereinafter referred to as jitter (1)), and (ii) nonlinearity of the transmission system of the M Lt SE signal. Depending on the characteristics, a component (hereinafter referred to as jitter (11)) is generated when the pilot signal is phase modulated under the influence of the MUSE signal.
and (iii) a component due to phase noise added to the pilot signal (hereinafter referred to as jeddah (mountain)).

Jitter (1) is jitter that both the MUSE signal and the pilot signal have, and is caused by mechanical factors, so it has a relatively low frequency. on the other hand,
Jitter (11) and (iii) are jitters that only the pilot signal has, and are caused by the level or frequency spectrum of the MUSE signal at any given time, or occur randomly, so they are jitters that occur from relatively low frequencies to high frequencies. It's spreading. Then, the PLL circuit 20 described above synchronizes the write signal WCK with jitter (i) and jitter (1).
Since it is necessary to remove 1) and (iii), jitter (
The time constant of the loop filter 22 is set so that the low frequency jitter, which is the component 1), remains. this is,
This is because if most of the jitter (1) is removed in the PLL circuit 20, it becomes difficult to synchronize the write signal WCK with the MUSE signal.

Therefore, the output signal of the PLL circuit 20 (hereinafter, signal W
CK'), some of the knocks (II) and (iii) remain without being removed. Furthermore, when the pilot frequency fp changes, a predetermined follow-up period is required for the write signal WCK to completely synchronize with the pilot signal in the PLL circuit 20. This causes low-frequency component jitter (hereinafter referred to as knock). ) is added to the new f.

However, by removing at least the high-frequency knock in the loop filter 22, the magnitude of the jitter can be reduced to one period (hereinafter referred to as l) of the write signal WCK (16,2 MHz).
clock).

Here, the phase relationship between the output signal WCK' of the PLL circuit 20 and the pilot signal is shown in FIG. First, signal WCK
' frequency is equal to write frequency f1 16.2M
As mentioned above, the pilot frequency fp is 2.278125 MHz (equation (+
), the nine periods of the pilot signal are the signal WCK'
is equal to 64 periods of . Therefore, if the timings of the rising edge of the pilot signal at time tl and the rising edge of signal WCK' match, then
This timing does not match until the time tlo, at which the cycle has elapsed, is reached. That is, in the PLL circuit 20,
The signal WCK' depends on whether it is locked to the rising edge of the signal WCK' or to the time tl"'-js.
It can be seen that the phase of the signal WCK' can take nine different values, and there is no guarantee that the timing of the signal WCK' will match the sampling timing of the MUSE signal. The details of this point will be described later, but in the phase soft circuit 26, the phase of the signal WCK" is 40°, 80°, . . . based on the phase of the horizontal synchronization signal.
...It is shifted by 280° or 320° to prevent timing errors.

Further, the phase-softened signal WCK'' is further removed from jitter in the phase modulation circuit 27, and the write signal WC
It is output as K.

D, Configuration of HD phase error detection circuit 30 Next, the configuration of the HD phase error detection circuit 30 will be explained.

■Frame synchronization detection circuit 35 First, in the ADC 8, the MUSE signal is sampled in synchronization with the write signal WCK, the sampling result is written to the memory 9, and the frame synchronization detection circuit 3
5.

Here, the signaling system of the MUSE signal is as shown in Fig. 6, as is well known, and the frame pulses provided on lines No. 1 and No. 2 are as shown in Fig. 7 (A). There is. When the frame synchronization detection circuit 35 detects this frame pulse, it supplies a frame synchronization detection signal synchronized with the frame pulse point (see FIG. 7(a)) to the horizontal synchronization detection circuit 34. Furthermore, the MUSE signal sampled in the ADC 8 is sent to the frame synchronization detection circuit 35.
The signal is also supplied to the horizontal synchronization detection circuit 34 via.

■Horizontal synchronization detection circuit 34 The horizontal synchronization signal (I(D)) of the MUSE signal is provided at the first 12 clocks of each line as shown in FIG. When the detection signal is output, it is possible to predict the output timing of the horizontal synchronization signal (HD) in the subsequent lines based on this.The horizontal synchronization detection circuit 34 detects the MUSE signal based on the frame synchronization detection signal. The horizontal synchronizing signal provided at the beginning of each line is detected and supplied to the phase error detection circuit 33.

Here, the waveform of the horizontal synchronizing signal is as shown in FIG. 7(b), and has a level of 50% of the video signal, and the polarity is reversed for each line. Further, the horizontal phase reference point is located at the sixth clock.

(2) Phase error detection circuit 33 Next, the phase error detection circuit 33 detects and outputs the phase error (jitter) between the horizontal synchronization signal and the write signal WCK. The details will be explained below.

First, when the write signal WCK does not contain any jitter, the level of the MUSE signal at the fourth clock is "a", the level at the sixth clock is "b", and the level at the eighth clock is "a". “C
′, as is clear from Figure 7 (b), a+C b −−T−, = 0...Formula (
5) holds true. On the other hand, when the write signal WCK includes jitter, it can be seen that the right side of equation (5) does not become "0" but becomes a value proportional to the jitter. In other words, jitter = ±(b-2) The magnitude of jitter can be determined by calculation as shown in equation (6). Note that in equation (6), the sign of "±" on the right side changes for each line along with the polarity of the horizontal synchronizing signal.

(2) Other configurations The jida value detected via the phase error detection circuit 33 is latched by the latch circuit 32, and then converted to a voltage signal VT via the DAC 31 and output.

In this way, each of the components 31 to 35 receives the write signal WC.
An HD phase error detection circuit 30 is configured to detect a phase error (jedder) between K and the horizontal synchronization signal ( ) (D) of the MUSE signal, and output this phase error as a voltage signal Vt.

Structure of E0 Phase Shift Circuit 26 Next, the DC component (hereinafter referred to as voltage signal V') of the voltage signal V is extracted through the LPF 28, and this voltage signal V is sent to the phase shift circuit 26. Supplied. Here, details of the phase shift circuit 26 will be explained with reference to FIG. 2.

First, the signal WCK' outputted from the PLL circuit 20 (13i!l not shown) is sequentially gated through eight delay circuits 41 to 4g (delay circuits 43 to 46 are shown) to an AND circuit 58.
is supplied to one input terminal of the Here, each delay circuit 41 to 4
The delay time TD of 8 is 1/1 of the period T of the write signal WCK.
It is set to be 9. Also, 50-57 are also A
The circuits are ND circuits (AND circuits 52 to 55 are shown as circuits in the figure), and their negative input terminals (the upper input terminals in the figure) are sequentially connected to the input terminals of each of the delay circuits 41 to 48. Also, 60
is an OR circuit, which outputs the logical sum of the output signals of each AND circuit 50-58. Here, each AND circuit 50 to 58
The signal supplied to each -input of the signal S. -58, the waveform diagram of these signals is shown in FIG.

On the other hand, the voltage signal VT' supplied via the LPP 28 is supplied to the phase difference detection circuit 62. Phase difference detection circuit 6
2 detects the phase error of the horizontal reference phase point from the voltage signal VT' and supplies the detection result to the phase control circuit 61. Based on the detection result of this phase error, the phase control circuit 61 supplies an "l" signal to the other input terminal (lower input terminal in the figure) of any one of the AND circuits 50 to 58, and A “0” signal is supplied to the other input terminal of the AND circuit.

That is, when the phase error is "0°", the AND circuit 5
A “1” signal is supplied to the other input terminal of 0, and the phase error is “4”.
0°, the “L” signal is supplied to the other input terminal of the AND circuit 51, and similarly, each time the phase error increases by 40°, the other input terminal of the subsequent AND circuits 52 to 58 is supplied. To “
l” signal is provided.

Therefore, for example, if the phase error detected by the phase difference detection circuit 62 is "320°", "l" is output from the phase control circuit 61 to the other input terminal of the A N D circuit 58.
signal is supplied, and each other input terminal of the other AND circuit is set to “0”.
” signal is supplied. As a result, the delay circuits 41 to 48
The signal W delayed by 8T/9 (320°) through
CK' is supplied as a signal S to one input terminal of the AND circuit 58, and is supplied to the phase modulation circuit 27 via the AND circuit 58 and the OR circuit 60 in sequence. Hereinafter, the signals S and -S output from the OR circuit 60 will be collectively referred to as "signal WCK".

Configuration of F3 Phase Modulation Circuit 27 Next, the configuration of the phase modulation circuit 27 will be explained with reference to FIG. In the figure, 27i, 27b, ... 27n are
These are n CMOS type inverters, which are sequentially connected in series. The signal WCK'' is input to the inverter 27a, and the output signal of the inverter 27n is output as the write signal WCK.The voltage signal Va is input to the loop filter 29, and after being integrated with an appropriate time constant. , is output as a voltage signal V'r''. voltage signal VT
" is applied as a power supply voltage to the power supply input terminal VDD of these inverters. - In CMOS type inverters used for fishing boats, there is a delay time when a signal passes, but most of this delay time is due to internal capacitance. Therefore, as the power supply voltage increases, the charging time and delay time decrease.In other words, when the voltage signal VT'' increases, the phase of the write signal WCK advances,
Conversely, if the voltage signal VT'' becomes small, the phase of the write signal WCK is delayed.

As described above, it can be seen that according to the configuration of FIG. 4, the jitter of the signal WCK" is removed, and this is controlled and outputted as the write signal WCK so that it matches the phase of the horizontal synchronization signal. That is, the PLL The jitters (ii) and (iii) remaining in the circuit 20 and the knock (iv) newly added in the PLL circuit 20 are removed sequentially through the phase shift circuit 26 and the phase modulation circuit 27. It is possible to suppress the jitter remaining in the signal WCK to about 10 nsec,
Compared to a write signal obtained by simply phase-synchronizing with a pilot signal, it is possible to suppress the magnitude of jitter to about 1/6.

G Summary As mentioned above, the timing of the Samblin knob of the ADC 8 is determined by the 1 write signal WCK output from the phase modulation circuit 27, and when the sampling result is supplied to the 1-(D phase error detection circuit 30), the write signal WCK is output from the phase modulation circuit 27. The phase error of is output as voltage signal ■A, and this voltage signal V
T is supplied to the phase modulation circuit 27 via the loop filter 29. As a result, each of the above components 8, 30.29
It can be seen that numerals 27 and 27 form a PLL circuit. Also, a PLL circuit 20 is installed in that stage.

Therefore, in this embodiment, two independent PLL circuits are provided for phase control of the write signal WCK, and the loop gain of the negative PLL circuit can be made small, resulting in stable operation. . Furthermore, this allows the level of the pilot signal to be reduced, and the adverse effects of the pilot signal on reproduced video and audio signals to be reduced. In addition, jitter correction can be completed inside the video disc player, and MUS E
There is no burden on external equipment such as decoders.

Furthermore, since no mechanical means are used for jitter correction, stability and durability are excellent.

"Effects of the Invention" As explained above, according to the present invention, the first phase distortion correction means removes the high frequency component of the phase distortion imparted to the first pilot signal, and the synchronization signal is extracted from the main signal. a second phase distortion correction means that removes residual components of phase distortion by detecting a phase difference between the synchronization signal and the second pilot signal and phase modulating the second pilot signal so that this phase difference becomes small; Therefore, the amount of correction in both phase distortion correction means can be made relatively small, phase distortion can be accurately removed, and the stability of the circuit is excellent.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video disc player according to an embodiment of the present invention, FIG. 2 is a block diagram of a phase shift circuit 26, FIG. 3 is a waveform diagram of each part in FIG. 2, and FIG. 4 is a phase modulation circuit. 27, FIG. 5 is a waveform diagram of each part of the PLL circuit 20, FIG. 6 is a diagram showing the signal system of the MUSE signal,
FIGS. 7(a) and 7(b) are waveform diagrams of various parts of the MUSE signal. 8...Analog/digital converter (second phase distortion correction means), 20...PLL circuit (No.
phase distortion correction means), 27... phase modulation circuit (
2 loop filters (second phase distortion correction means), 30 HD phase error detection circuits (second phase distortion correction means).

Claims (1)

[Claims] When reproducing a video signal formed by superimposing a main signal including a synchronization signal and a first pilot signal of a predetermined period, the main signal is synchronized with a write clock that follows the main signal. In a time base correction circuit that removes phase distortion caused by a rotating system, etc. by temporarily storing the signal and reading it using a reference clock, the newly generated phase distortion is added to the first pilot signal after signal separation. a first phase distortion correcting means for removing a high frequency component of the phase distortion and outputting it as a second pilot signal; and second phase distortion correction means for detecting a phase difference between the second pilot signal and the second pilot signal, phase-modulating the second pilot signal so that the phase difference becomes small, and outputting the result as a write clock. Signal time base correction circuit.