JPH04291924A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an electrode layer on the upper side from being overlapped with a stepped part at its lowr part, and a protruding part from being produced in the longitudinal direction and to improve the coverage of an interconnection by a method wherein, when an upper electrode layer and a lower electrode layer which sandwich an insulating film is aligned with each other in the transverse direction, the portion of the film thickness of at least the insulating film is added to an alignment margin. CONSTITUTION:A semiconductor device provided with a multilayer interconnection structure in which a plurality of electrode layers 2 to 5 and insulating films 6 to 10 have been arranged alternately is manufactured. At this time, the upper and lower electrode layers 3, 4 sandwiching the insulating film 7 are aligned with each other in the transverse direction. At this time, they are aligned by adding the portion of the film thickness (d) of at least the insulating film 7 to an alignment margin between the upper and lower electrodes. For example, at the multilayer interconnection structure of an SRAM, an insulating film 7 is formed of SiO2 on a second-layer polysilicon layer 3 in a film thickness of 100nm by a CVD method. At this time, when the alignment margin of a stepper is at 0.2mum, the alignment of a third-layer polysilicon layer 4 is performed at a margin alpha of 0.1+0.2=0.3mum.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. Specifically, the present invention relates to a method of positioning between electrode layers in a wiring process of a semiconductor device having a multilayer wiring structure in which an interlayer insulating film and an electrode layer have a multilayer structure.

0002

2. Description of the Related Art Multilayer wiring process technology is an effective technology for creating multiple layers of wiring in an integrated circuit, providing flexibility in connection between elements formed on a substrate, and increasing density. However, since many layers are laminated, the surface of the layer becomes uneven, and the problem of poor step coverage at the step of the metal wiring is likely to occur.

[0003] An explanation will be given below, taking SRAM (static random access memory) as an example.

FIG. 2 is a circuit diagram of a unit memory cell of an SRAM. This SRAM has four transistors T1, T
2, T3, T4 and two high resistances R1, R2. Transistors T3 and T4 each have a load resistance R
1 and R2 in series, and are cross-wired. Each interconnection point is connected to the bit line BL via transistors T1 and T2, which act as transfer gates.
a and BLb. Note that in this specification, the bit lines BLa and BLb correspond to what is normally called the bit lines BL and BL bar. Further, the gates of these transistors T1 and T2 are connected to the word line WL.

Considering the transistor T2, one current terminal region (source S) is connected to the bit line BLb, and the other current terminal region (drain D) is connected to the resistor R2, the gate of the transistor T3, and the transistor T2. T4
connected to the drain of

FIG. 3 shows an example of a cross-sectional structure of one transfer gate transistor T2 of an SRAM manufactured using a conventional multilayer interconnection process.

The multilayer wiring structure of this SRAM consists of a first polysilicon layer 2, a second polysilicon layer 3, and a third polysilicon layer forming polycide wiring and polycide gates on a p-type Si substrate 1. Each electrode layer of the second polysilicon layer 4 and the fourth polysilicon layer 5, and insulating films 6, 7, made of SiO2 alternately formed between these polysilicon layers.
8, an insulating film 9 thereon, and Si doped with boron and phosphorus.
It has a laminated structure with a BPSG layer 10 made of O2. Note that the polysilicon of the electrode layer is doped with impurities and becomes conductive. However, the fourth polysilicon layer is selectively doped with a small amount of impurities and has a high resistivity region. On the p-type substrate 1, there are n+-type semiconductor regions 11,1 which become the drain region and source region of the MOS transistor T2.
2 is formed. Note that portions A and B respectively surrounded by broken lines in FIG. 3 correspond to the connection portions of the source and drain of the transistor T2 in the circuit diagram of FIG.

When patterning the first polysilicon layer 2 (polycide), the word line WL, which is the address line in the circuit diagram of FIG.
Gate electrode layers 2, T3, and T4 are formed at one time. When patterning the second polysilicon layer 3, the power supply VSS line, the bit line BL which is the data line
A polysilicon layer, etc. for raising the surface formed under BLb and BLb are also formed together. When patterning the third polysilicon layer 4, a power supply VCC line, lead lines from the gates of transistors T3 and T4, etc. are formed. When the fourth polysilicon layer 5 is patterned, resistors R1, R2, etc. are formed at the same time. Al wiring is further provided on the polysilicon layer. In order to connect and wire these multilayer electrode layers, the insulating film between the electrode layers is opened and contact holes are formed at predetermined locations.
After performing a pretreatment to remove the native oxide film inside the contact hole, an upper wiring layer, for example, an Al wiring, is formed by sputtering.

The drain region 11 of the transistor T2 is
It is connected to the gate of a transistor T3 (not shown) by the first polycide layer 2, and connected to the resistor R2 formed by the fourth polysilicon layer 5 by the third polysilicon layer 4. Furthermore, the drain region 11 is connected to the drain of the transistor T4. Therefore, in the drain portion of the transistor T2, four polysilicon layers have a complicatedly related shape. The second polysilicon layer 3 on the source region 12 of the transistor T2 is provided to improve connectivity when an Al layer for forming the word line WL is sputtered thereon.

0010

[Problem to be Solved by the Invention] In the manufacturing process according to the conventional technique shown in FIG. 3, when forming the second and third polysilicon electrode layers 3 and 4, the positioning performance is determined by the positioning performance of the conventional exposure stepper device. Positioned by horizontal alignment margins between layers. In that case, if the value is at the very edge of the margin, as shown in FIG.
The third polysilicon layer 4 may overlap the stepped portion. Then, the third layer polysilicon 4 on the insulating film 7
As shown in the figure, the end portion becomes a large protrusion 13, which further pushes up each layer deposited thereon. Finally, due to the upper protrusion shown by the dotted line C, the protrusion casts a shadow on the sputtering during the final formation of the upper layer wiring using Al.
There was a problem in that the Al electrode was not evenly formed on the raised second layer polysilicon 3 (the part indicated by the dotted line A), resulting in poor coverage.

[0011] The purpose of the present invention is to solve the above problems,
When aligning the upper and lower electrode layers in the horizontal direction, the upper electrode layer does not overlap with the step portion below it, thus preventing the generation of vertical protrusions, which is a semiconductor device with good metal wiring coverage. The purpose is to provide a manufacturing method.

0012

[Means for Solving the Problems] In the method for manufacturing a semiconductor device of the present invention, a multilayer wiring structure in which a plurality of electrode layers and insulating films are stacked alternately is arranged, and upper and lower electrode layers sandwiching an insulating film are arranged horizontally between upper and lower electrode layers. At the time of alignment in the direction, alignment is performed by adding at least the film thickness of the insulating film to the alignment margin between the upper and lower electrodes.

[0013]

[Operation] The insulating layer deposited on the stepped portion grows almost uniformly not only on the top surface of the base but also on the side surfaces. Therefore, when an insulating layer is formed on the protrusion, the lateral dimension of the protrusion increases by approximately the thickness of the insulating layer.

[0014] When aligning the upper and lower electrodes, the positions are shifted by an amount corresponding to the thickness of the insulating film, so that the positions of the upper and lower electrode layers in the lateral direction are always shifted by the thickness of the insulating film. Therefore, even if the electrode layer is shifted by a margin determined by the performance of the stepper, the upper electrode layer will not climb onto the stepped portion of the lower insulating layer.

[0015]

Embodiment An embodiment of the method for manufacturing a semiconductor device of the present invention will be described with reference to FIG.

FIG. 1 is a cross-sectional view of the transfer gate portion of an SRAM memory cell manufactured by the method of the embodiment of the present invention at the same location as FIG. 3. Note that the circuit diagram is the same as that in FIG. The multilayer wiring structure of this SRAM consists of a p-type Si substrate 1, a first polysilicon layer 2 made of polycide, a second polysilicon layer 3, a third polysilicon layer 4, and a fourth polysilicon layer 2. A laminated structure of each electrode layer of the polysilicon layer 5, insulating films 6, 7, 8 made of SiO2 alternately formed between the polysilicon layers, an insulating layer 9 thereon, and a BPSG layer 10. It has become. p
On the type substrate 1, n+ type semiconductor regions 11 and 12 which become the drain and source of the MOS transistor T2 are formed.

The drain region 11 of the transistor T2 is
It is connected to the gate of a transistor T3 (not shown) by the first polycide layer 2, and connected to the resistor R2 formed by the fourth polysilicon layer 5 by the third polysilicon layer 4. Drain region 11 is also connected to the drain of transistor T4. Therefore, in the drain portion of the transistor T2, four polysilicon layers have a complicatedly related shape. The second polysilicon layer 3 on the source region 12 of the transistor T2 is provided to improve connectivity when an Al layer for the word line WL format is sputtered thereon.

When patterning the first polysilicon layer 2, the address line WL and the gate electrodes of the transistors T1, T2, T3, T4, etc. in the circuit diagram of FIG. 2 are formed at once. When patterning the second layer of polysilicon layer 3, the polysilicon layer 3 for raising the layer to be formed under the power supply VSS line and the bit lines BLa and BLb, which are data lines, is also formed. Ru. When patterning the third polysilicon layer 4,
A power supply VCC line and lead lines from the gates of transistors T3 and T4 are formed.

When the insulating film 7 is formed on the second polysilicon layer 3 with a thickness of 100 nm using SiO2 by the CVD method, the alignment margin of the stepper is set to 0.2 μm.
Then, the third polysilicon layer 4 is aligned with a margin of 0.1+0.2=0.3 μm. Then, even if the stepper has a maximum margin of positional deviation of 0.2 μm, there is still a margin of 0.1 μm, which is equal to the insulating film thickness d, up to the end (step) of the second polysilicon layer 3. Therefore, as shown in FIG. 1, the third polysilicon layer 4 does not overlap the stepped portion of the insulating film 13 below, and no vertical protrusion is generated.

In other words, the alignment margin α of the upper and lower electrode layers is α=interlayer alignment margin determined by the performance of the stepper +
The insulation film thickness is d.

The subsequent formation of each layer is the same as in the case of FIG. 3, so a description thereof will be omitted. In the description of the embodiments of the present invention, SRAM was targeted; however, the present invention is not limited to the manufacture of SRAM, and the present invention can be applied to other semiconductor devices having a multilayer wiring structure. Needless to say, it can be applied in the same way as the example and the same effect can be obtained.

Although the present invention has been described above with reference to examples, the present invention is not limited thereto. For example, it will be obvious to those skilled in the art that various changes, improvements, combinations, etc. are possible.

[0023]

[Effects of the Invention] As explained above, according to the present invention,
A semiconductor device having desired characteristics can be manufactured without unexpected protrusions occurring in a semiconductor device having multiple wiring layers.

Furthermore, by minimizing the alignment margin, it is possible to minimize the reduction in the degree of integration.

[Brief explanation of the drawing]

FIG. 1: SRAM manufactured by the method of the embodiment of the present invention
FIG.

FIG. 2 is an equivalent circuit diagram of a unit memory cell of SRAM.

FIG. 3 is a partial cross-sectional view of an SRAM manufactured by a conventional technique.

[Explanation of symbols]

1... P-type Si substrate 2... First layer polysilicon layer (polycide) 3... Second layer polysilicon layer 4...
- Third layer polysilicon layer 5... Fourth layer polysilicon layer 6, 7, 8, 9, 10, 13... Insulating film 11, 12... n+ type semiconductor region

Claims (2)

[Claims] Claim 1: Electrode layer (2 to 5) and insulating film (6 to 10
), in which at least the above-mentioned A method for manufacturing a semiconductor device, characterized in that alignment is performed by adding a film thickness (d) of an insulating film to the alignment margin between the upper and lower electrodes. 2. Upper and lower electrode layers (3,
Claim 1, wherein 4) is mainly formed of polysilicon.
A method of manufacturing the semiconductor device described above.