JPH04291855A - Atm cell format conversion system - Google Patents

Abstract

PURPOSE:To make the system small by relaxing an operating speed of a buffer memory in the inside of an exchange switch and decreasing a switch element of a channel. CONSTITUTION:An input format conversion means 3 eliminates a head error code in 1 byte from an inputted cell in 53 bytes to form a serial 52-byte code. Then the 52-byte code is divided and the divided codes are inputted to an exchange switch 2 in parallel in the unit of divisions and the exchange switch implements the exchange processing. The cell exchanged by the exchange switch 2 is outputted from an exchange switch 42 in the unit of plural bytes, an output format conversion means 4 generates a serial 52-byte code and adds a 1 byte header error code again to the 52-byte code to recover the 53-byte code. Moreover, a 1 byte dummy data is added to the 52-byte code to form the 53 byte code. Or 1 byte dummy data is added to the 53 bytes to form a 54-byte code and the processing is similar to the case of using the 54-byte code.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to ATM switching equipment, and more specifically to UNI (User Network In
terface) and NNI (Network Node)
The present invention relates to a method for converting a cell transfer format defined in the ``Interface'' to a cell transfer format within an ATM switch.

0002

2. Description of the Related Art In broadband ISDN, in order to provide users with effective services, of which image communication is a typical example, switching equipment is required to have a large throughput capacity. As a method of economically realizing large-scale ATM switching equipment,
One possibility is to speed up the communication path. However, since the exchange principle of ATM is basically store-and-forward, it is necessary to provide an internal buffer memory, making it difficult to increase the speed of communication channels.

FIG. 15 is a block diagram of a switch section in a conventional ATM exchange. Conventionally, UNI and NN
The cell transfer format input from I was used as is in the ATM switch equipment.

0004

Generally, in order to increase the speed, a method has been considered in which cells are expanded in parallel to reduce the operating speed. However, in the conventional system, even if a 53-byte cell length is parallelized to reduce the speed, the 53-byte number 53 constituting the cell is a prime number, so there is a limit to parallel processing in byte units. Therefore,
Unable to increase highway throughput,
There was a problem in that the switching equipment became large.

For example, in an N-channel exchange with a transfer rate of V as shown in FIG. 16, a memory capable of operating at the maximum speed V must have a capacity equal to the square of N.

SUMMARY OF THE INVENTION An object of the present invention is to provide an ATM cell format conversion system that reduces the operating speed of a buffer memory inside an exchange switch and reduces the number of switch elements in a communication path to make the system more compact.

[0007]

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. The present invention relates to an ATM exchange 1 in which an exchange switch 2 exchanges cells between input and output highways.

The input format conversion means 3 inputs 5
After removing the header error detection code from the 3-byte cell, the cell is divided into a plurality of parts and added to the exchange switch 2 in parallel in units of a plurality of bytes.

The output format conversion means 4 adds a header error detection code to the data obtained in units of a plurality of bytes after the exchange by the exchange switch 2 and outputs the data.

0010

[Operation] The input format conversion means 3 inputs 53
A header error detection code consisting of 1 byte is removed from a cell consisting of bytes to make 1 cell 52 bytes. These 52 bytes are added to the exchange switch 2 in parallel in units of multiple bytes. For example, input 2 bytes, 4 bytes, etc. in parallel. The cells exchanged by the exchange switch 2 are outputted by the exchange switch 2 in similar units of multiple bytes, and are applied to the output format conversion means 4. The output format conversion means 4 generates the removed header error detection code, adds it to the target position, and outputs it.

Since the input cell is converted into a cell consisting of 52 bytes, multiple bytes of data can be added to the exchange switch 2, making it possible to miniaturize the circuit and achieve high-speed exchange.

On the other hand, the same result can be obtained by adding one byte of dummy data instead of removing the header error detection code. Note that at this time, the input is in units of 2 bytes or 6 bytes.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below with reference to the drawings. FIG. 2 is a configuration diagram of an embodiment of the present invention. The cell transfer format specified by the above-mentioned UNI and NNI from input highways #1 to #n is transferred to the format converter (input) I.
Input to S1-ISn. Format converter IS1~
ISn removes HEC (Header Error Detection Code: CRC) from a cell consisting of 53 bytes, converts serially input byte data into parallel byte data consisting of a plurality of bytes, and applies it to the switch section SW.

FIG. 3 shows the first format converter (input)
FIG. 2 is a configuration diagram of an embodiment of IS1 to ISn. Each of the format converters IS1 to ISn includes a FIFO 11, a serial/parallel conversion circuit 12, and an AND gate 13. Cells of 53 bytes are sequentially added to the FIFO 11. When a write clock is input in a state where writing is not prohibited, the write block W is added to the FIFO 11 from the AND gate 13, and the FIFO 11 takes in the data of that cell in units of 1 byte. Note that when HEC is used, writing is prohibited and the clock is not output to the FIFO 11. Therefore, among the cells consisting of 53 bytes, the cells with only the HEC removed are the FIF.
It is stored in O11.

FIG. 5 is a timing chart of the first format conversion. When the write clock is the 5th byte corresponding to the input cell (the 5th byte is the HEC), the write clock is dropped, and the HEC is no longer taken into the FIFO 11. F
The 52-byte data stored in the IFO 11 is read out using the read clock R. At this time, up to the 53rd byte exists, but the 5th byte does not exist, resulting in a cell consisting of 52 bytes in total. This byte serial output data is applied to the serial/parallel conversion circuit 12 and becomes parallel bytes. For example, as shown in Figure 5, if the output is in units of 2 bytes, 1, 2 bytes, 3, 4 bytes, 6,
7 bytes... Here, if the serial/parallel conversion circuit 12 is configured with 52/P bytes, the speed will be V/P. On the other hand, the switch section SW switches the data parallelized in this way and outputs them to the target terminal in 2-byte units. Format converter (output) OS
1 to OSn perform serial conversion from these and set H at the 5th byte.
Open the EC part and convert it to a 53-byte cell.

FIG. 4 shows the first format converter (output)
It is a block diagram of an Example. Data (52/P byte cells) inputted from the switch section SW at a speed of V/P is applied to the serial conversion circuit 14 and converted into 52 byte cells. The data is added to FIFO 15 and stored on the write clock. The 52-byte cell stored in the FIFO 15 is read out using the read clock R, but is inhibited by the AND gate 16 for one clock, and is left open without outputting data during that time. As a result, it is possible to finally output 53 byte cells and the speed V. That is, the FIFO 11 and the serial/parallel conversion circuit 12 are installed on the input side of the exchange switch.
A cell format conversion circuit consisting of a parallel/serial conversion circuit 14 and a FIFO 15 is provided on the output side, and a cell format conversion circuit consisting of a parallel/serial conversion circuit 14 and a FIFO 15 is provided. The output even-numbered byte cells are speed-converted into multiple byte units using a serial/parallel converter and sent to the exchange switch.
The even number byte cells processed in units of multiple bytes from the exchange switch are speed-converted into even number bytes in units of bytes using a parallel/serial converter, and are written to the FIFO 14, and a time position of HEC is set for later insertion at the time of reading. Converting to byte cells.

By the above operation, a cell consisting of a prime number of bytes such as 53 bytes can be converted into a cell consisting of a plurality of parallel bytes, thereby increasing the speed and making the circuit smaller. In the above, the header error detection code HEC is removed and 53
Although the number of bytes is set to 52 bytes, it is also possible to configure 53 bytes to 54 bytes, for example. FIG. 6 is a configuration diagram of an embodiment of the second format conversion sections (input) IS1 to ISn. This second format converter I
In S1 to ISn, if the input is, for example, 53 bytes, the input is taken as is into the FIFO 11, and
The output of the read clock R is prohibited so that an empty area, ie, a dummy area, is provided when outputting to the serial/parallel converter. As a result, the output of the FIFO is 53 as shown in Figure 8.
An empty space is provided after the byte.

The serial/parallel converter 19 receives these 53 bytes +
A total of 54 free byte cells are added, and serial/parallel converter 1
9 outputs parallel cells of 54/P bytes if the speed is V/P, for example. This parallelized information is exchanged by the switch section SW. FIG. 7 is a block diagram of an embodiment of the second format converter. The 54/P byte cells of the speed V/P exchanged by the switch section SW are connected to the parallel/serial converter 2.
0 and is converted into a 54-byte cell. This data is then added to FIFO21. The write clock W applied at this time inhibits the 54th byte so that it is not stored in the FIFO 21. In other words, the write clock applied to the AND gate 22 is set to 5 by the write inhibit signal.
Only the 4th byte is prohibited (see Figure 8), and as a result, F
53 bytes of data is stored in IFO21. Then, 53 bytes of data are output by the read clock. The speed at this time is V.

That is, the FIF is connected to the input side of the exchange switch.
A format converter (input) IS1 to IS3 consisting of a parallel/serial converter 20 and a FIFO 21 is provided on the output side, and a cell format converter consisting of a parallel/serial converter 20 and a FIFO 21 is provided on the output side. Write the cell as it is to the FIFO 17, insert empty data so that it becomes an even byte length cell when reading, then convert the speed into units of multiple bytes in the serial/parallel conversion circuit 19 and send it to the exchange switch SW. The parallel/serial conversion circuit 20 speed-converts the even number byte cells processed in units of multiple bytes from F to even number byte cells in bytes.
The empty data that was inserted when writing to IFO21 is extracted and converted to the original 53-byte cell.

By performing the exchange as described above, cells having a length of 53 bytes can be exchanged in parallel. FIG. 9 is a detailed configuration diagram of the first format converter (input). Also, Figure 1
0 is a detailed configuration diagram of the first format conversion section (output). 9 and 10 show the configuration when the parallel number is 2 bytes.

A 53-byte cell standardized by UNI or NNI is input to the FIFO 11 from the input/output highway. In order to find the position of the HE whose head is the 5th byte from the input 53-byte cell, write clock W is used.
- Add the output of the 53 counter 31 that counts CLK to the comparator 32, and input the HEC time position 4 to port B. When data is sequentially taken into the FIFO 11 by the clock, the comparator 32 outputs a match (L level) at the time of 4. When this match occurs, an L level is applied to one side of the AND gate 13, turning the AND gate 13 off, and the write clock W.CLK is no longer applied to the FIFO 11. Since the write clock W/CLK is not applied during HEC, the FIFO 11 is
Pass EC import. This allows FIFO11
52 bytes of data is stored in . This stored data is sent to the shift register 33 using a read clock R.
- Captured by CLK. This shift register 3
3 is a two-stage register, and 8 with two read clocks.
Take in 2 bytes of data (bit + 8 bits). On the other hand, a signal obtained by dividing the read clock R/CLK by 1/2 by the frequency dividing circuit 34 is applied to the latch circuit 34, and the latch circuit 34 receives the signal taken in by the shift register in response to the 1/2 frequency divided clock. Outputs 2 bytes of data. That is, 16-bit data for two clocks is output. By the above-described operation, the input format can be added to the exchange switch in units of 16 bits.

The data exchanged by the exchange switch is converted into 8 bits by the selector 14. At this time, the selector 14 sequentially selects signals to be applied to the 0 and 1 terminals in response to a clock obtained by dividing the write clock W.CLK by 1/2. Then, the selected byte (8 bits) data is sequentially added to the FIFO 15 and stored. The data stored in the FIFO 15 is a 52-byte cell, and when sequentially read out, the counter 37 always counts 53 counts and adds the output to the comparator. 4, which is the time position of HEC, is added to the B port of the comparator 38, and when the counter 37 is 4, a coincidence signal is output from the comparator (L level). This L level turns off the AND gate 18, and during this time the FIFO1
5 does not output data. Also, at this time, the selector selects the output of the A port and outputs the separately created HEC. Then, in the next stage, that is, after 5, the output of the FIFO 15 is selected in the same way, and finally 53 byte cells are output.

FIGS. 11 and 12 are detailed configuration diagrams of the second format converter (input, output). The format converter (input) has a counter 41 in addition to a FIFO 17 and an AND gate 18, and sequentially outputs read clocks R and CLK.
is counted, and the count value is sent to A of the comparator 42.
Add to port. Further, 53 is added to the B port of the comparator 42. When the counter 41 shows a value of 53, the coincidence signal becomes L level and is output, and is applied to the AND gate 18. Due to this L level, the AND gate 18 is turned off, the read clock is not output, and the FIF
During this time, O17 continuously outputs the same data as the 53rd data. That is, when it reaches 53, the clock is not applied, so the FIFO outputs dummy data. This value is added to shift register 43. The 1st, 2nd, 3rd, 4th, 5th, 6th, ... data sequentially output from the FIFO 17 is added to the shift register 43, and the latch 45 is divided into 2 bytes by the clock frequency divided by 1/2 by the frequency dividing circuit 44. It takes in data in units and outputs it as 16 bits. On the other hand, at the 53rd byte, the 54th byte is not output and is added to the shift register 43 as dummy data, so as a result, the 53rd byte and dummy data are taken into the latch circuit 45 and output as 16-bit data. be done. The input is 53 bytes, but with the above operation it becomes 54 bytes, so parallel data can be output.

On the other hand, the data exchanged by the exchange switch SW is applied to the selector 20 from the exchange switch, and in the selector 20, the write clock W・CLK is divided into 1 by the frequency dividing circuit 51.
Select using the signal divided by /2. That is, one 8 bits are selected in the first half, and the other 8 bits are selected in the second half. The output is then applied to FIFO21. Further, the write counter W.CLK is added to the counter 52, which counts this clock and outputs the count value to the A port of the comparator 53. Further, 53 is input to the B port, and the count is sequentially advanced until the count value reaches 53, and the FIFO 21 takes in the output selected by the selector. When the count value reaches 53, the comparator 53 outputs the L level, so the next count value is 54, which becomes 0, and the AND gate 22 outputs 5.
The fourth write clock W/CLK is not output. Therefore, the FIFO 21 does not take in the 54th data. In addition, the read clock is outputted 53 times, resulting in 53
Byte cells are output. As described above, in the second format converter (input, output), the exchange switch operation can be performed in units of 54 bytes, so input to the exchange switch can be performed in units of 2 bytes.

Although the present invention has been described in detail using the embodiments above, the present invention is not limited to ATMs, UNIs, and NNIs, but can be similarly configured in other exchanges, for example. Further, the same applies not only to 53 bytes but also to other byte numbers such as 59 bytes. Furthermore, the same applies to changing odd numbers to even numbers, not just prime numbers.

FIGS. 13 and 14 are explanatory diagrams for reducing the amount of hardware according to the present invention, and explanatory diagrams for relaxing the operating speed according to the present invention. As shown in FIG. 13, a switch section with n channels and a speed of V is configured, and as in the embodiment, a format conversion section (input) IS1 to ISn, a 2:1 multiplexer, a 1:2 demultiplexer, and a format conversion section. (Output) By providing OS1 to OSn at the input/output, the input becomes n/2, so the capacitance of the switch part becomes n
2/2, which is half the value of the conventional one. Moreover, by simply providing the format converter F, a switching element can be constructed at half the speed of V/2 even if the capacity is the same.

[0027]

[Effects of the Invention] As described above, according to the present invention, the speed of the buffer memory can be reduced by increasing the degree of parallelism of the cell transfer format inside the exchange, thereby making it possible to reduce the use of inexpensive buffer memories with slow access speeds. It is possible. In addition, by increasing the degree of multiplicity per operating speed, the number of switch elements in the communication path can be reduced, resulting in miniaturization.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a configuration diagram of first format conversion (input).

FIG. 4 is a configuration diagram of first format conversion (output).

FIG. 5 is a timing chart of first format conversion.

FIG. 6 is a configuration diagram of a second format converter (input).

FIG. 7 is a configuration diagram of a second format converter (output).

FIG. 8 is a timing chart of second format conversion.

FIG. 9 is a detailed configuration diagram of a first format converter (input).

FIG. 10 is a detailed configuration diagram of a first format converter (output).

FIG. 11 is a detailed configuration diagram of a second format converter (input).

FIG. 12 is a detailed configuration diagram of a second format converter (output).

FIG. 13 is an explanatory diagram of hardware amount reduction in the present invention.

FIG. 14 is an explanatory diagram of moderation of operating speed in the present invention.

FIG. 15 is a configuration diagram of a conventional switch unit.

FIG. 16 is an explanatory diagram of conventional switch speed.

Claims (2)

[Claims] [Claim 1] In an ATM exchange in which cells are exchanged between input and output highways by an exchange switch (2), a header error detection code is removed from an input cell consisting of 53 bytes to make it an even number of bytes, and then the cells are exchanged in parallel in units of multiple bytes. an input format conversion means (3) that is added to the exchange switch (2); and a header error detection code is added to the data obtained by the exchange switch (2) in units of multiple bytes, and output back to the original 53-byte cell. an output format conversion means (4), wherein the exchange switch exchanges cells in parallel units of a plurality of bytes. 2. In an ATM exchange in which cells are exchanged between input and output highways by an exchange switch (2), dummy data is added to an input cell consisting of 53 bytes to make it an even number of bytes, and then the above-mentioned data is transferred in parallel in units of multiple bytes. an input format conversion means (3) added to the exchange switch (2); and an input format conversion means (3) that removes the dummy data from the data obtained by the exchange switch (2) in units of the plurality of bytes, and converts the data into the original 53
The ATM is characterized in that it has an output format conversion means (4) for outputting the data back into byte cells, and the exchange switch exchanges cells in parallel units of a plurality of bytes.
Exchange method.