JPH04291440A - High speed arbitration circuit - Google Patents

Abstract

PURPOSE:To obtain the arbitration time having no relation with the bit number (n) of the arbitration number given to a device in regard to an arbitration circuit of a bus system. CONSTITUTION:The different arbitration numbers (1) of (n) bits are assigned to all devices connected to a bus and then outputted to a bus acquisition control bus consisting of (n) bits. Then the numbers (1) are compared with the arbitration numbers (2) of a bus acquisition control bus consisting of (n) pieces of buses in terms of bits. An arbitration circuit has a system to suppress a case where the signal of a less significant bit number (i-1) of the number (1) is outputted to the bus acquisition control bus when the level of a signal line corresponding to a certain weight bit (i) is lower than the level of the signal line of the same bit (i) of the bus acquisition control bus. In such an arbitration circuit, the number of a bit train where '0' is never put between '1' and '1' of each bit is defined as the number (1) of each device.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitration circuit in a bus system. FIG. 3 is a diagram showing an example of the configuration of a normal bus system. In a bus system such as a multiprocessor system in which a plurality of devices (hereinafter referred to as devices) 2 are connected to a common data bus 1, a certain device 2 among the connected devices 2 is connected to the common data bus 1. 1, the device 2 must obtain control (right to use) the common data bus 1.

[0002] Such a device 2 will be referred to as a master module herein, but a plurality of master modules 2 may simultaneously request bus acquisition for the common data bus 1. A conflict of bus acquisition requests occurs and it must be determined which master module 2 will use the common data bus 1 first. This process is generally called arbitration.

As one of such arbitration methods, each device 2 is provided with an arbitration circuit 2.
0, and assign a mutually different n-bit arbitration number (d0 to dn-1) to each device 2, and the arbitration circuit 2 of each device 2.
0, the master module 2 that wants to use the common data bus 1 outputs the arbitration number (d0 to dn-1) assigned to itself to the bus acquisition control bus 3. Arbitration numbers output above (A0 to A
n-1) The level of the signal line (di) corresponding to the bit i of a certain weight is compared with the level of the bit i of the arbitration number ■ outputted on the bus acquisition control bus 3. is equal to or higher than the level (Ai) of bit i, the lower bit (i-
The arbitration number ■ in 1) is output to the bus acquisition control bus 3, and the level of the signal line corresponding to bit i of the weight becomes the bit of the arbitration number ■ output on the bus acquisition control bus 3. When the level is lower than that of bit i, the lower bit (i-1)
The arbitration number ■ is the bus acquisition control bus.
By operating to suppress output to 3,
The highest level arbitration number at that time is determined on the bus acquisition control bus 3, and the master module 2 with the same number as the arbitration number ■ on the bus acquisition control bus 3 uses the common data bus 1. There are known methods for obtaining rights.

[0004] In such an arbitration method, when the arbitration number (■) assigned to each device is composed of n bits, each master module outputs its own arbitration number (■) and uses the bus acquisition control bus. There is a problem that the time it takes to determine the arbitration number ■ above in 3 (hereinafter referred to as arbitration time) increases by a factor of n2 or n, for example, and as the number of devices increases recently. Then, the arbitration time becomes impossible to ignore.

[0005] Therefore, there is a need for an arbitration circuit that can obtain an arbitration time that is independent of the number n of bits constituting the arbitration number (2).

[0006]

4 to 7 are diagrams illustrating conventional arbitration circuits. FIG. 4(a) shows an example of a circuit that transmits the output of the arbitration logic of each bit to the lower bit, and FIG. 6(b) shows an example of a circuit in which the output of the arbitration logic of each upper bit is distributed to each lower bit to configure the arbitration logic of each bit, and FIG. 6(c) shows the arbitration logic of each bit. shows the truth table of

In the above arbitration method, a single arbitration number (d0 to dn-1) (2) is assigned to all master modules 2, and all master modules 2 requesting to acquire a bus correspond to this number (2). A dot-OR signal is output on the bus acquisition control bus 3 consisting of n signal lines (A0 to An-1).

Therefore, on the bus acquisition control bus 3,
The logical sum of the arbitration numbers ■ of master module 2 that participated in the arbitration is shown, and
Arbitration circuit in each master module 2
20, each master module that participated in the arbitration determines whether its own arbitration number (■) matches the arbitration number (■) indicated on the bus acquisition control bus 3, and transfers the common data bus 1.
Recognize whether you have achieved this.

FIG. 6(c) shows a truth table of this arbitration decision logic. Here, it is assumed that logic "1" is at a higher level than logic "0", and the arbitration number (d0
~dn-1) (2) and the arbitration number (A0 ~ An-1) (2) on the bus acquisition control bus 3 are both shown in positive logic for convenience of explanation.

In the arbitration determination logic of this system, the arbitration numbers (A0 to An-1) on the bus acquisition control bus 3 are determined whether the levels are equal or not.
High, the arbitration number of master module 2 that participated in each arbitration (d0 ~ dn-1
) is outputted onto the bus acquisition control bus 3.

That is, in each bit i, when the arbitration number ■ on the master module 2 side is equal to or higher in level than the arbitration number ■ on the bus acquisition control bus 3, the lower bit (i-1) is When the arbitration number ■ on the master module 2 side is lower than the arbitration number ■ on the bus acquisition control bus 3, the bus acquisition control bus 3 is no longer output on the bus acquisition control bus 3 in the lower bits. Assuming that there is no need to compare the lower bits (
i-1) is suppressed from being output on the bus acquisition control bus 3.

To explain using the truth table in FIG. 6(c), the logic values on the bus side and the module side are "00" and "00", respectively.
01" and "11", the arbitration level on the master module 2 side is equal or higher, so when this logical condition is applied, the lower bit (i-1)
is output to the bus acquisition control bus 3, but when the logical value on the bus side and the module side is "10", the arbitration level on the master module 2 side is
Since it is lower than the arbitration level on the bus side, under this logical condition, the lower bit (i-1) is inhibited from being output to the bus acquisition control bus 3.

[0013]

[Problem to be Solved by the Invention] Figure 4(a) shows this logic condition configured using a serial circuit,
"MPETE" indicates a bus acquisition request signal in the master module 2 having the arbitration circuit 20, and "WIN" indicates bus acquisition.

The first AND circuit 200 in each stage of the arbitration circuit 20 assigns the arbitration numbers (d0 to d6) to the bus acquisition control bus 3.
The OR circuit 201 determines the above logic condition, and the next AND circuit 202 performs control to inhibit transmission to the lower bits.

[0015] When all bits (in this example, 7-bit configuration) of the arbitration number (d0 to d6) of a certain master module 2 are equal to or higher than the arbitration level on the bus side, the arbitration number of the master module 2 is The arbitration number ■ is output on the bus acquisition control bus 3, and the arbitration number ■ on the bus acquisition control bus 3 becomes equal to the arbitration number ■ of the master module 2, so that the arbitration circuit 20 of the master module 2 Then, the bus acquisition signal (WIN) can be obtained.

When each competing master module 2 outputs its own arbitration number ■, a stable arbitration number ■ is sent on the bus acquisition control bus 3.
In other words, the time it takes to determine the highest level arbitration number, that is, the above-mentioned arbitration time, is determined by the arbitration circuit shown in FIG. 4(a) above.
In the case of 20, if multiple master modules 2 participate in the arbitration, the output state changes from the high-order bit with the highest weight to the low-order bit with the low weight, so the arbitration time is relatively large.

Arbitration time in this case (
Tarb), for example, in the document "Institute of Electrical and Electronics Engineers, Micro, D. M. Tau, August 1984,
pp. 28-41” {“IEEE Micro, D. M. T
aub, 1984, 8, P28-P41}, when the arbitration number is n bits, Tarb=4tp+(n+1)t' where tp is the bus (bus acquisition control bus). The propagation delay time, t', is the delay time n of the arbitration circuit, which means that the required time increases in proportion to the number of bits, that is, the number of bits n. However, in the case of the arbitration circuit shown in Figure 4(a) above, the transition from the upper bit to the lower bit requires two stages of negation, or, and and.
Since -1 delay time t' is required, this circuit configuration increases by a factor of n2.

In order to avoid this increase in delay time, a method is known in which, for example, the circuit configuration shown in FIG. 5(b) is used. Regarding this circuit configuration, for example, refer to the document ““IB
M Manual, S-2, Micro Channel Architecture Arbitration”, “IBM Manual, S-2
, Micro Channel Architecture
re Arbitration”.

In this circuit configuration, the arbitration logic (logical sum) condition for each bit is input to the arbitration logic circuit for each bit in the form of AND, and the output of each bit is as shown in FIG. 4(a). Since there is no transition towards the lower bits, the required time when having an n-bit arbitration bus is as shown in D. above. M.
The delay time "Tarb" shown by Mr. Tau is,
There remains a problem that grows by a factor of n.

FIG. 7 is a diagram illustrating an increase in delay time in a conventional arbitration circuit. In this figure, an example is shown in which the arbitration number ■ is composed of, for example, 5 bits, and there are three master modules 2 requesting bus acquisition.

The arbitration number ■ of master module (1) 2 is "01111", and the arbitration number ■ of master module (2) 2 is "1".
0011'', and the arbitration number ■ of the master module (3) is ``10101''.

In this case, the highest level arbitration number "10101" is assigned to the bus acquisition control bus 3.
The time it takes to determine is as follows. First of all,
In "Phase 1", each master module (1),
The logical sum "11111" of the arbitration numbers ■ of (2) and (3) 2 appears as the arbitration number ■ on the bus acquisition control bus 3. Since the arbitration circuit 20 operates to reach this state, a delay of t' is required.

Here, the arbitration number ``11111'' on the bus acquisition control bus 3 and each arbitration number ``11111'' are compared under the logical conditions shown in FIG. 6(c).

Therefore, in "Phase 2", in the arbitration circuit 20 of each master module (1), (2), (3) 2, each arbitration number ■ which is lower in level than the arbitration number ■ on the bus acquisition control bus 3 is As a result, each arbitration number is apparently "00000" as shown in the figure.
, "10000", "10000", and the arbitration number ■ on the bus acquisition control bus 3 is "1".
0000". To reach this state, the above t'
delay.

In the next "phase 3", the arbitration number on the bus acquisition control bus 3 is set to "10000".
and the arbitration number of each master module■
The apparent arbitration number of each master module in this phase is ``00''.
000”, “10011”, “10101”, and the arbitration number ■ on the bus acquisition control bus 3 is
It becomes "10111". To reach this state, the above t'
delay.

Similarly, in the next "Phase 4", the apparent arbitration numbers of each master module 2 are "00000", "10000", and "10000", respectively.
10100'', and the arbitration number ■ on the bus acquisition control bus 3 becomes ``10100''. It takes the above-mentioned delay t' to reach this state.

[0027] In "Phase 5", the apparent arbitration number of each master module 2 is
"00000", "10000", "101" respectively
01", the arbitration number ■ on the bus acquisition control bus 3 becomes "10101", which determines the highest level arbitration number ■, and the arbitration circuit 20 of the master module (3) 2 that has the arbitration number ■ Acquisition signal '
You can get a WIN. Even in this state,
Again, a delay of t' is required.

In such a case, when the arbitration number is 5 bits, a delay of 6t' is required in the arbitration circuit 20, and the above D.
M. The theoretical value of the delay time calculated by Mr. Tau “(n+
1) t'.

As described above, the conventional method of assigning the arbitration number ■ as shown in FIG. When the number of master modules (devices) 2 increases, there is a problem that the time required for the arbitration process cannot be ignored.

In view of the above-mentioned drawbacks of the conventional art, the present invention provides an arbitration circuit in a bus system with an arbitration time "Tarb" that is independent of the number of bits n of the arbitration number given to the master module.
The purpose of this invention is to provide an arbitration circuit that can obtain the following.

[0031]

[Means for Solving the Problems] The above problems are solved by an arbitration circuit configured as follows.

In the bus system, an arbitration circuit 20 is provided for devices 2 connected to the bus 1 to obtain control of the bus, and all of the devices 2 are assigned different n-bit arbitration numbers. In order for each device 2 to acquire control of the bus, the arbitration circuit 20 of each device 2 outputs the arbitration number ■ assigned to itself to the bus acquisition control bus 3 consisting of n bits. Then, compare the level with the arbitration number ■ on the n-bus bus acquisition control bus 3 in bit correspondence, and the level of the signal line corresponding to bit i of a certain weight is the signal of the same bit on the bus acquisition control bus 3. When the level is lower than the output of the bus acquisition control bus 3, the signal of the lower bit number i-1 of the arbitration number of the device 2 is suppressed from being output to the bus acquisition control bus 3. In an arbitration circuit 20 that uses a method in which the highest level arbitration number is determined, a bit string in which "0" is not inserted between "1" and "1" of each bit of the arbitration number The configuration is such that a number consisting of .

[0033]

[Operation] In the present invention, the arbitration number (■) assigned to each master module is composed of a bit string in which no "0" is inserted between "1" and "1" of each bit of the arbitration number (■). It is determined that

That is, 2n, 2n-1,... 2i,
The bit strings corresponding to the weights of 2i-1, . . . 20 are expressed as bn, bn-1, . . . bi, bi-1, .
. . b0, when bi=1, bk=1 (i>k), it is determined as a number with a bit configuration where bs=1 for s where i>s>k.

As an example of such a sequence of numbers, for example, when n=4, 0, 1, 2, 3, 4, 6, 7, 8, 1
The fact that 2, 14, and 15 are obtained is easily understood by bit expansion of each numerical sequence.

When a number composed of such a numerical sequence is given to each master module as an arbitration number ■, the winning master is determined in the above-mentioned arbitration circuit when a match is detected with the arbitration number ■ on the bus acquisition control bus. The bit output of the arbitration number ■ of the module is not stopped, and the bit of the arbitration number ■ of the master module whose level is low and should be defeated is suppressed from being output to the bus acquisition control bus, and then output again. , is never output, so at most two-phase arbitration processing
The winner is determined and is independent of the number n of bits making up the arbitration number ■.

[0037] Therefore, the time required for arbitration can be shortened and is not related to the number of participating master modules, so the greater the number of master modules, the more significant the time reduction effect can be obtained.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram illustrating an example of the configuration of the arbitration circuit of the present invention using a PLD element.

In the present invention, in a bus system, a mutually different n-bit arbitration number ■ is assigned to all devices (master modules) 2 connected to the bus, and each device (master module) 2 The arbitration circuit 20 provided to acquire the control right outputs the n-bit arbitration number ■ to the n-bit bus acquisition control bus 3, and performs arbitration on the n-bit bus acquisition control bus 3. The level of the signal line corresponding to the bit i of a certain weight is compared with the number ■ in correspondence with the bit, and if the level of the signal line corresponding to the bit i of a certain weight is lower than the output of the signal line of the same bit i on the bus acquisition control bus 3, the device 2 The signal of the lower bit number (i-1) of the arbitration number ■ is suppressed from being output to the bus acquisition control bus 3, and the highest level arbitration number ■ is determined on the bus acquisition control bus 3. As a result, each device 2 equipped with the above-mentioned arbitration circuit 20 is given the right to use the bus (common data bus 1) by the device 2 having the same arbitration number ■ as the arbitration number ■. A bit string number in which "0" is not inserted between "1"s is assigned as the arbitration number ■ of each device 2, and the arbitration circuit 20 assigns the arbitration number on the bus acquisition control bus 3. A means for comparing (2) and bit correspondence is a means necessary for carrying out the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The configuration and operation of the arbitration circuit of the present invention will be explained below with reference to FIGS. 1 and 2 while referring to FIGS. 3 to 7. First, in the present invention, as described above, the number of a bit string in which "0" is not inserted between "1" of each bit, for example, the string of the number is 4 bits. If it is composed of 0, 1, 2, 3, 4
, 6, 7, 8, 12, 14, and 15 are assigned as arbitration numbers ■ to each device 2.

In each device 2, when it is desired to use the common data bus 1 described above, the arbitration circuit 20 shown in FIG. 5(b) having the truth table shown in FIG. Input the number ■ and output it to bus acquisition control bus 3.

FIG. 1 shows that the arbitration number ■ is 5.
When configured with bits, the device (master module) that acquires control of the bus (1), (2)
2 arbitration numbers ■ are ``14'', respectively.
” (01110) and “3” (00110).

Generally, assuming that the master module with the higher number becomes the winner in the arbitration process, the master module with the number "14" (1) 2
should be the winner.

Considering the above arbitration logic, in the case of the present invention, phase 1: The logical sum of the arbitration numbers ■ of master module (1) 2 and master module (2) 2 is output to the bus acquisition control bus 3. Ru.

In the example of FIG. 1, the arbitration number ■ shown as "01110" appears on the bus acquisition control bus 3. Phase 2: Arbitration number ■ on this bus acquisition control bus 3 and each master module (1), (2)
2 is compared with arbitration number ■ in the arbitration circuit 20 .

In the case of the present invention, arbitration number ■
Since the configuration is such that "0" is not inserted between "1" and "1" of each bit, the arbitration number of the winner's master module (1) 2
The output of "01110" is output on the bus acquisition control bus 3 without any bit being stopped, and the arbitration number of the defeated master module (2) 2 "00110" means that all bits are output on the bus Arbitration number on acquisition control bus 3 ■“01110
``Since the level is lower than that, all bit outputs are stopped, and as a result, in this phase 2, the arbitration number ■ on the bus acquisition control bus 3 is determined, and the arbitration number equal to the arbitration number ■ is determined. Master module with ■ (1) 2
obtains the right to use the bus, i.e. becomes the winner.

In the present invention, as described above, a delay time of t' is required to enter the phase 1 state, a delay time of t' is required to enter the phase 2 state, and the winner That is, in this embodiment, the master module (1)
2 requires t' for its own arbitration circuit 20 to obtain a signal (WIN) indicating that the right to use the bus has been obtained, resulting in a total arbitration logic delay of 3t'.

[0048] The above-mentioned D. M. According to Tau's theory,
As arbitration time, bus acquisition control bus
If the propagation delay time tp is 3, the arbitration time is Tarb=4tp+logic delay of the arbitration circuit, so the arbitration circuit of the present invention 20
Then, Tarb=4tp+3t', which has the characteristic that it is not related to the number n of bits making up the arbitration number.

Therefore, in the arbitration circuit 20 of the present invention, the greater the number of participating master modules 2, the greater the effect of reducing the time required for arbitration compared to the conventional system.

Next, with reference to FIG. 2, the effects when the arbitration circuit 20 of the present invention is constructed of PLD elements (programmable logic devices) will be explained. Figure 2(a) shows the arbitration circuit 20 {
4(a) and 5(b)}, the logic when the arbitration number is composed of 4 bits is expressed as a logical formula for obtaining the least significant bit A0 (however, negative logic) on the bus acquisition control bus 3. This is shown in .

[0051] Here, A0 to A3 indicate the signals of arbitration number ■ on the bus acquisition control bus 3, and d0
~d3 indicates the arbitration number ■ on the master module 2 side.

When the arbitration circuit 20 shown in FIG. 5(b) is implemented using a PLD element, the PLD
Since the element is basically an and-or logic, it is necessary to develop the above logical formula into an and-or logic.

When the logical formula shown in FIG. 2(a) is developed into AND-OR logic, it becomes as shown in FIG. 2(b), and 8
However, in the case of the present invention, the bit string input to the arbitration circuit 20 is
Since the structure is such that "0" is not inserted between "1" and "1", the product term shown in FIG. 2(c) becomes logic "0", so the present invention The arbitration circuit 20 in Figure 2 (d
), it can be realized by the AND-OR logic of four product terms, and the effect of simplifying the circuit configuration can also be obtained.

[0054]

As described above in detail, the arbitration circuit of the present invention provides a bus system with different n-bit arbitration numbers for all devices (master modules) 2 connected to the bus. In the arbitration circuit 20 provided for each device (master module) 2 to acquire control of the bus, output the arbitration number ■ consisting of n bits to the bus acquisition control bus 3 consisting of the n bits, The level of the arbitration number ■ on the bus acquisition control bus 3 consisting of n lines is compared in bit correspondence, and the level of the signal line corresponding to bit i of a certain weight is the signal of the same bit i on the bus acquisition control bus 3. When the level is lower than the output of the bus acquisition control bus 3, the signal of the lower bit number (i-1) of the arbitration number ■ of the device 2 is inhibited from being output to the bus acquisition control bus 3, and the bus acquisition control is performed. Each of the above-mentioned arbitration circuits 20 is configured such that when the highest level arbitration number ■ is determined on the bus 3, the device 2 having the same arbitration number ■ as the arbitration number ■ gains the right to use the bus. In device 2, specify the number of the bit string in which no “0” is inserted between “1” of each bit.
It is assigned as the arbitration number ■ of each device 2, and compared in bit correspondence with the arbitration number ■ on the bus acquisition control bus 3 in the arbitration circuit 20, so the arbitration time constitutes the arbitration number ■. It is no longer related to the number of bits n, and has the effect of significantly shortening the arbitration time. Furthermore, when the arbitration circuit is implemented using AND-OR logic such as a PLD element, the circuit configuration can be simplified.

[Brief explanation of the drawing]

[Fig. 1] A diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of the arbitration circuit of the present invention using a PLD element.

[Figure 3] Diagram showing an example of the configuration of a normal bus system

[Figure 4
] Diagram explaining a conventional arbitration circuit (Part 1)
)

[Figure 5] Diagram explaining a conventional arbitration circuit (
Part 2)

[Fig. 6] Diagram explaining a conventional arbitration circuit (
Part 3)

[Figure 7] Diagram explaining a conventional arbitration circuit (
Part 4)

[Explanation of symbols]

1 Common data bus 2 Device or master module 20
Arbitration circuit 3
Bus acquisition control bus ■ Arbitration number assigned to each device (d0 to dn-1) ■ Arbitration number on the bus acquisition control bus (A0 to An-1)

Claims (1)

[Claims] Claim 1: In a bus system, an arbitration circuit (20) for a device (2) connected to the bus (1) to acquire control of the bus, the arbitration circuit (20) for all the devices (2) In order for each device (2) to obtain control of the bus, the arbitration circuit (20) of each device (2) allocates a different n-bit arbitration number (■) to itself. Arbitration number (■)
is output to the bus acquisition control bus (3) consisting of the n bits, and compared in level with the arbitration number (■) on the bus acquisition control bus (3) consisting of the n bits in a bit-wise manner. When the level of the signal line corresponding to i is lower than the output of the signal line of the same bit on the bus acquisition control bus (3), the device (2)
The lower bit number i-1 of the arbitration number of
an arbitration circuit (20) using a method in which the highest level arbitration number is determined on the bus acquisition control bus (3) by inhibiting output of the signal to the bus acquisition control bus (3); , each bit of the arbitration number (■) is “1”
1. A high-speed arbitration circuit characterized in that a number consisting of a bit string in which "0" is not inserted between "1" and "1" is assigned as an arbitration number (■) for each device (2).