GB2165726A - Arbitration system for data bus - Google Patents
Arbitration system for data bus Download PDFInfo
- Publication number
- GB2165726A GB2165726A GB08524539A GB8524539A GB2165726A GB 2165726 A GB2165726 A GB 2165726A GB 08524539 A GB08524539 A GB 08524539A GB 8524539 A GB8524539 A GB 8524539A GB 2165726 A GB2165726 A GB 2165726A
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- Prior art keywords
- bus
- unit
- arbitration
- module
- value
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
A bus arbitration system which arbitrates access to the bus in a case where plurality of modules request access to the bus at the same instant. Each module comprises a setting unit which sets an identification number representing the level of priority of the module, an arbitration unit which compares the identification number with those of other modules to decide whether of not the module has right to use the bus, and a subtracting unit which changes the identification number to an identification number of a lower level of priority, in a case where the module has acquired right to use the bus. <IMAGE>
Description
SPECIFICATION
Arbitration system for data bus
BACKGROUND OF THE INVENTION Field ofthe Invention
The present invention relates to an arbitration system for leveling the opportunities of a plurality of stations or modules connected to a common bus for datatransmissionthroughthebustogain access rights to the bus.
Description ofthe PriorArt
When an order of priority is established beforehand among a plurality of modules connected in parallel to a data bus, the opportunities to access the data bus of the modules are not equal, because when a module of higher priority occupies the bus for a long time, the opportunities to access the bus ofthe modules of lower priority are reduced. An arbitration system to arbitrate the rightto gain the control of the bus among the modules have been developed to relieve unequal opportunity to gain right to access the bus among the modules. For example, an arbitration system illustrated in Figs. 1 to 4 is disclosed in "Multibus II Bus
Architecture Specification Handbook", OEM Micro computer Systems, (1984), 2- 27.Referring to Fig. 1, a setting unit 1 sets identification numbers (referred to as "ID numbers" (hereinafter) to be given to the modules and sends the same to an arbitration unit 2.
Upon the reception of an arbitration command signal, the arbitration unit 2 implements arbitration cycle according to the order if ID numbers, and then the arbitration unit 2 provides a bus acquisition signal when bus ownership is obtained. Indicated at 5 is a terminal for connecting the arbitration unit 2 to the bus.
For conveniences' sake, suppose thatthree modules 6, 7 and 8 each having an arbitration unit as illustrated in Fig. 1 are connected to a bus 9 as illustrated in Fig. 2. Concretely, each module has a circuit illustrated in Fig. 3. This ciruit comprises five
NAND gates GOto G4, open-collector NAND gates G5 toG9,andanANDgateGl0.
The operation ofthis circuit will be described hereinafter. When the three modules 6, 7 and 8 request for access to the bus 9, an arbitration request signal 3 of each module becomes significant. In each ofthe modules 6, 7 and 8, the arbitration unit2 receives signals IDO to ID4 from the setting unit 1 and provides arbitration signals through the terminal 5.
These arbitration signals are the output signals of the open collectors indicated at G5 to G9 in Fig. 3, and wired OR is taken in the bus. Consequently, the bus acquisition signals of some among the modules 6, 7 and 8 become significant (= 1), while those of the rest become insiginficant 0). The bus acquisition signal 4 ofthe module (module 6, in this case), having the highest ID number, namely the highest priority, among the modules 6, 7 and 8 providing significant arbitration requestsignals3 becomes significant and the bus acquisition signals 4 of the rest of the modules become insignificant. Consequently,the module 6 having the significant bus acquisition bus signal 4 obtains control ofthe bus 9. At this time, the bus 9 and the terminal 5 have a value corresponding to the inversion of the value of the ID number of the module which has gained the control ofthe bus 9. Afterthe control ofthe bus 9 has been gained, the arbitration request signal 3 becomes insignificant until the bus 9 is needed nexttime.Thusthe arbitration cycle is performed on an assumption that modules having higher ID numbers have higher priority to gain the control ofthe bus 9.
The conventional bus arbitration system is constituted as described hereinbefore, in which the each functional module hasafixed ID number. Therefore, if a module having an ID number of higher priority continues using the bus, modules having ID numbers of lower priority are obliged to waitfor a long time before they gain the control ofthe bus, and hence opportunityto gain the control of the bus is liable to be biased to particular modules.
The present invention has been madeto solve the above-mentioned problems in the conventional bus arbitration system, and it is an object ofthe present invention to provide a bus arbitration system capable of leveling opportunityto gain the control ofthe bus among modules.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a bus arbitration system comprises: a setting unitfor setting an identification number; a latch unitfor latching the value of the identification number set by the setting unit; an arbitration unit which compares the priority of the module with those of other modules on the basis of the value of the identification number latched by the latch unit, and provides a signal indicating the acquisition of bus ownership when the own priority is higherthan those of the other modules; and means to change the value of the identification number latched by the latch unitwhen a bus acquisition is provided by the arbitration unit.
Change ofthevalue of an identification number is equivalentto the priority of the module which has gained bus ownership becoming lower, and hence in the next arbitration cycle, one ofthe rest ofthe modules gains bus ownership. Accordingly, the mod ules have the equal opportunity to accessthe bus.
In an exemplary application of the present invention, change of the value of an identification number given to the arbitration unit is achieved by subtracting a value corresponding to the inversion ofthe value of the identification numberfrom the latched value, or may be achieved by subtracting a predetermined value from the latched value.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram of a conventional bus arbitration system included in one ofthe modules connected to a common bus;
Figure 2 is a diagram illustrating connection of modules to a bus;
Figure 3 is a circuit diagram of an arbitration unit employed in a conventional bus arbitration system;
Figure 4 is a block diagram of a module provided with a bus arbitration system according to the present invention; and
Figures Sand 6 are block diagrams of modules provided with different bus arbitration systems, respectively, according to the present invention.
DETAILED DESCRIPTION OF THE
PREFERRED EMBODIMENTS
Fig. 4 is a block diagram of a preferred embodiment ofthe present invention In Fig.4, parts designated by reference numerals 1 to 5 are the same as those designated bythesame reference numerals in Fig. 1.
In Fig. 4, indicated at 10 is a selector unit, at 11 is a latch unitwhich stores signals given thereto by the selector unit 10 and at 12 is a subtraction unitwhich subtract a signal given through a terminal Sfrom the output signal ofthe latch unit 11 to obtain an ID number.
Modules6to 8 each consisting ofthose units are connected to a bus 9 in a well-known manner as illustrated in Fig. 2.
The function of the modules will be described hereinafter. In the initial state of each ofthe modules 6, 7 and 8, the selector unit 10 selects a signal among signals DO to I 1D4 given bythesetting unit 1 and stores the selected signal as the ID number ofthe module in the latch unit 11. In an arbitration cycle, the ID number stored in the latch unit 11 is given through the arbitration unit 2 to a bus 9. The arbitration unit 2 compares the ID numbers to each other and decides the priority ofthe module in the well-known procedure. Onlythe bus acquisition signal 4 of the module having the highest priority and gained control ofthe bus 9 becomes significant.The bus 9 and theterminal 5 have a value corresponding to the inversion of the value ofthe ID number ofthe module having bus ownership. Furthermore,thesubtraction unit l2of each ofthe modules 6, 7 and 8 subtracts a value corresponding to the inversion ofthevalueatthe terminal 5 from the value of the ID number, i.e., the value of the output of the latch unit 11. The result of the subtraction is stored in the latch unit 11. In a state otherthan the initial state, the selector unit 10 selects the output of the subtraction unit 12.At every arbitration cycle, the value of the ID numberofthe module obtained control of the bus 9 is subtracted from the values ofthe ID numbers stored in the modules 6, 7 and 8to change the ID numbers ofthe modules 6,7 and 8forthe next arbitration cycle.
For example, suppose thatthe values ofthe ID numbersofthe modules 6,7 and 8 are 10, 8and 5 respectively, and the modules 7 and 8 having ID numbers of values 8 and 5 implement arbitration cycle. Then, the module7 having the greatervalue of
ID number8 gains the bus 9, and thevalue 8 is subtracted from the values of ID numbers ofthe modules 6, 7 and 8 forthe next arbitration. Conse quently, the values 10, 8 afld 5 are reduced to values 2, 0 and -3 respectively. Sincethe results of subtraction ignore sign bit, -3 is regarded as 13 and 13 is stored as
ID numbersforthe next arbitration cycle.Accordingly, in the next arbitration cycle, sincethevalue of the ID numberofthe module which had 8 as the value ofthe ID number in the preceding arbitration cycle and gainedthe bus becomesO (zero), the priority ofthis module is the lowest in the next arbitration cycle, while the value ofthe ID number of the module which had 5 as the numberofthe ID numberin the preceding arbitration cycle becomes 13 in the next arbitration cycle, and hence this module hasthe highest priority in the next arbitration cycle.
In this embodiment, thirty-two values, namely, from Oto 31, corresponding to five bits can be set as the valuesoflDnumbers,however,thenumberofbits may be any optional number according to the number of modules.
As described hereinbefore, in this embodiment, the
ID numbers representingthe level of priority ofthe modules connected to the bus are updated at every arbitration cycle and the highest priority is given to a module having the greatest value of ID number.
Therefore, opportunity of gaining bus ownership will not be biased to particular modules and the same opportunity is given to all the modules.
Fig. 5 illustrates another embodiment ofthe present invention. In Figs. 4 and 5, like reference numerals designate like or corresponding parts. In a module illustrated in Fig. 5, the subtrating unit 12 employed in the module of Fig. 4 is substituted by a decrementer 31 The decrementer 31 #receives a signal from a latch unit 11 and gives an output signal to a selector unit 10.
The function of this embodimentwill be described hereinafter. In each of modules 6,7 and 8, when the module is in initial state, a selector unit 10 selects a signal among signals IDOto ID4given by a setting unit 1 and transfers the selected signal to a latch unit 11, which storesthe signal given thereto as the ID number ofthe module. When bus ownership need to be acquired,the ID number stored in the latch unit 11 is given through an arbitration unit2to a terminal 5 as the ID number. The arbitration unit decides the level of priority of the module on the basis ofthe ID number in a well-known manner. Only the bus acquisition signal 4 ofthe module having thebighest level of priority, for example, the module 6;and gained control of the bus 9 becomes significant.Upon the decision of the bus acquisition signal 4to be significant,the decrnmenter reducesthe value of the ID number by a value, for example, by 1 (one), to update the ID number. This updated number is stored in the latch unit 11 of the module 6 forthe next arbitration cycle. In a state other than the initial state, the selector unit 10 selects the output ofthe decrementer3l. Since the ID numbers of othermodules7 and 8which could not gain bus ownership are held unchanged, either the module 7 or the module 8 has the highest level of priorityforthe next arbitration cycle.
In Fig. 6 illustrating a further embodiment ofthe present invention, the outputterminal of a setting unit 1 is connected to both oneoftheinputterminalsofa subtracting unit 42 and a terminal 40 connected to a bus. Theterminal 40 is connected also to the input terminal of a latch unit41. The outputterminal ofthe latch 41 is connected tothe other input terminal ofthe su btractor 42. That is,the subtracting unit 42 is adapted to subtractthe value of an ID number stored in the latch unitfrom the value of an ID number set by the setting unit 1. The resultofthe subtraction is transferredto an arbitration unit2. The function ofthe arbitration unit 2 is the same as those ofthe embodiments of Figs. 4 and 5.
A setting unit 1 of a module which has gained control of bus 9 gives a significant signal to a terminal 40. A latch unit41 latchesthe value of the significant signal. A subtraction unit 42 subtracts the signal of the latch unit 41 from the signal of the setting unit 1 and provides the remainder as an output signal, which is used as ID number of modules 6to 8 in the next arbitration cycle. In an arbitration cycle, the ID number provided by the subtraction unit42 is given through the arbitration unit 2 to the bus 9. The arbitration unit 2 implements comparison and decision ofthe level of priority in a well-known manner. Onlythe bus acquisition signal 4 of the module having the highest priority and gained bus ownership becomes significant, and the ID number given bythe setting unit 1 to the terminal 40 is transmitted as it is.The latch unit41 is resetin the intitial state.
Thus, at every arbitration cycle, the ID number of a module which has gained control ofthe bus 9 is subtracted from the ID numbers ofthe modules 6,7 and 8 to give the modules different ID numbersforthe next arbitration cycle.
As an example, suppose that the values of the ID numbers ofthe modules 6, 7 and 8 are3, 5 and 10 respectively, modules 7 and 8 having 5 and 10 as the values ofthe ID numbers thereof respectively enter into arbitration, and the module 6 gained control of the bus 9 in the preceding arbitration cycle, namely, the value 3 of the ID number of the module 6 is latched by the latch unit 41. Then, the values of the subtraction units 42 of the modules 7 and 8 are 2 and 7, and hence the module 8 having a greater number gains control of the bus 9. The latch unit 41 of each module latches the value: 10 ofthe ID number set by the setting unit of the modu le 8. Conseq uently, the modules6,7 and 8 subtract 10 (ten) from the values oftheir ID numbers, and thereby the ID numbers ofthe modules 6, 7 and 8 become -7, -5 and 0. Since the results of operation ignore sign bits, -7 and -5 are regarded as 9 and 11 respectively, and the values: 9 and 11 are used in the next arbitration cycle. Thus the value of the ID number of the module 8 which gained control of the bus 9 in the preceding arbitration cycle becomes O (zero), and hence the level of priority of the module 8 in the next arbitration cycle is the lowest.
In this embodiment,thirty-two values, namely, from
Oto 31, corresponding to five bits can be set as the values of ID numbers, however, there is not any restriction on the number of bits.
Claims (5)
1. A bus arbitration system comprising a plurality of modules connected to a common bus and having identification numbers representing the levels of priority resepctively, and an arbitration unit included in each module and adapted to decide, on the basis of said identification numbers, whether or notthe module has rightto use said bus,whereineach of said modules comprises::
a setting unitforsetting said identification number;
a latch unit for latching the value of an identification number set by said setting unit;
an arbitration unit which compares the level of priority of the module with those of other modules on the basis of the values of the latched identification numbers, and provides a signal indicating the acquisition of right to use the bus when decision is made that the level ofpriorityoftheassociatedmoduleisthe highest; and
changing means to change the value ofthe identification number latched by said latch unit, when said arbitration unit provides a bus acquisition signal.
2. A system according to Claim 1, wherein said arbitration unit gives a value corresponding to the inversion ofthe value of an identification number given thereto from said latch unitto said bus, said changing means is subtracting means which subtracts said inverted value from the value ofthe identification number latched bysaid latch unit, and then makesthe latch unit latch the resultofthe subtraction.
3. A system according to Claim 1, wherein said changing means includes a decerementerwhich reduces the value of the identification number latched by said latch unit by a predetermined value at every acquisition of right to use the bus by said arbitration unit.
4. A bus arbitration system comprising a plurality of modules connected to a common bus and having identification numbers representing the levels of priority respectively, and an arbitration unit included in each module and adapted to decide, on the basis of said identification numbers, whether or notthe module has right to use said bus, wherein each of said modules comprises:
a setting unitforsetting said identification number;
a terminal for connecting the outputterminal of said setting unitto said bus;
a latch unit which latches a signal given to said terminal;
a subtracting unit which subtractsthevalue latched by said latch unitfrom the value of an identification number set by said setting unit; and
an arbitration unitwhich compares the level of priority of the module with those of other modules by using the value provided by said subtraction unit as the value of identification number, and provides a signal indicating the acquisition of rightto use the bus when decision is made that the level of priority of the associated module is the highest.
5. A bus arbitration system substantially as he reinbefore described with reference to Figure 4,5 or 6 ofthe accompanying drawings.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20796684A JPS6187448A (en) | 1984-10-05 | 1984-10-05 | Bus mediation system |
JP20796784A JPS6186858A (en) | 1984-10-05 | 1984-10-05 | Acquisition system for bus using right |
JP415285A JPS61163458A (en) | 1985-01-16 | 1985-01-16 | Bus mediating system |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8524539D0 GB8524539D0 (en) | 1985-11-06 |
GB2165726A true GB2165726A (en) | 1986-04-16 |
GB2165726B GB2165726B (en) | 1988-07-27 |
Family
ID=27276141
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08524539A Expired GB2165726B (en) | 1984-10-05 | 1985-10-04 | Arbitration system for data bus |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE3535436A1 (en) |
GB (1) | GB2165726B (en) |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2287621A (en) * | 1994-03-01 | 1995-09-20 | Intel Corp | High performance symmetric arbitration protocol with support for I/O requirements |
GB2293943A (en) * | 1994-10-04 | 1996-04-10 | Motorola Israel Ltd | Communications system with priority scheme for reduced access delay |
US5515516A (en) * | 1994-03-01 | 1996-05-07 | Intel Corporation | Initialization mechanism for symmetric arbitration agents |
US5754807A (en) * | 1995-11-20 | 1998-05-19 | Advanced Micro Devices, Inc. | Computer system including a multimedia bus which utilizes a separate local expansion bus for addressing and control cycles |
US5761452A (en) * | 1996-03-18 | 1998-06-02 | Advanced Micro Devices, Inc. | Bus arbiter method and system |
US5778200A (en) * | 1995-11-21 | 1998-07-07 | Advanced Micro Devices, Inc. | Bus arbiter including aging factor counters to dynamically vary arbitration priority |
US5802330A (en) * | 1996-05-01 | 1998-09-01 | Advanced Micro Devices, Inc. | Computer system including a plurality of real time peripheral devices having arbitration control feedback mechanisms |
US5805840A (en) * | 1996-03-26 | 1998-09-08 | Advanced Micro Devices, Inc. | Bus arbiter employing a transaction grading mechanism to dynamically vary arbitration priority |
US5935232A (en) * | 1995-11-20 | 1999-08-10 | Advanced Micro Devices, Inc. | Variable latency and bandwidth communication pathways |
US6061599A (en) * | 1994-03-01 | 2000-05-09 | Intel Corporation | Auto-configuration support for multiple processor-ready pair or FRC-master/checker pair |
US7995607B2 (en) * | 2004-04-28 | 2011-08-09 | Freescale Semiconductor, Inc. | Arbiter for a serial bus system |
US8254922B2 (en) | 2006-10-16 | 2012-08-28 | Stmicroelectronics, Inc. | Zero delay frequency switching with dynamic frequency hopping for cognitive radio based dynamic spectrum access network systems |
US8494546B2 (en) | 2006-10-16 | 2013-07-23 | Stmicroelectronics, Inc. | Method of inter-system communications dynamic spectrum access network systems-logical control connections |
US8503383B2 (en) | 2006-10-16 | 2013-08-06 | Stmicroelectronics, Inc. | Method of inter-system coexistence and spectrum sharing for dynamic spectrum access networks-on-demand spectrum contention |
US8780882B2 (en) * | 2008-01-16 | 2014-07-15 | Stmicroelectronics, Inc. | On-demand spectrum contention for inter-cell spectrum sharing in cognitive radio networks |
US8824432B2 (en) | 2008-01-16 | 2014-09-02 | Stmicroelectronics, Inc. | Beaconing period framing for efficient multi-channel inter-cell communications in cognitive radio networks |
Families Citing this family (5)
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JPH01180626A (en) * | 1988-01-12 | 1989-07-18 | Mitsubishi Electric Corp | Priority analyzer |
WO1993002421A1 (en) * | 1991-07-15 | 1993-02-04 | Fizichesky Institut Imeni P.N.Lebedeva Akademii Nauk Sssr | Method and device for forming a dynamic priority |
AT403629B (en) * | 1994-03-24 | 1998-04-27 | Keba Gmbh & Co | BUS SYSTEM, IN PARTICULAR PRIORITY-ORIENTED BUS SYSTEM |
DE19526378A1 (en) * | 1995-07-19 | 1997-01-23 | Telefunken Microelectron | Data bus system with several coupled integrated users |
DE19603442A1 (en) * | 1996-01-31 | 1997-08-07 | Siemens Ag | Method and arrangement for assigning access cycles to a bus of a microprocessor system |
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GB2114788A (en) * | 1982-01-07 | 1983-08-24 | Western Electric Co | Shared facility allocation system |
GB2117939A (en) * | 1982-03-29 | 1983-10-19 | Ncr Co | Data communication network and method of communication |
GB2125257A (en) * | 1982-08-04 | 1984-02-29 | Plessey Co Plc | Improved local area network systems |
EP0118731A1 (en) * | 1983-02-03 | 1984-09-19 | CSELT Centro Studi e Laboratori Telecomunicazioni S.p.A. | Distributed-structure circuit for arbitrating the access requests to the bus of a multiprocessor system |
EP0138676A2 (en) * | 1983-09-22 | 1985-04-24 | Digital Equipment Corporation | Retry mechanism for releasing control of a communications path in a digital computer system |
-
1985
- 1985-10-04 GB GB08524539A patent/GB2165726B/en not_active Expired
- 1985-10-04 DE DE19853535436 patent/DE3535436A1/en active Granted
Patent Citations (5)
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GB2114788A (en) * | 1982-01-07 | 1983-08-24 | Western Electric Co | Shared facility allocation system |
GB2117939A (en) * | 1982-03-29 | 1983-10-19 | Ncr Co | Data communication network and method of communication |
GB2125257A (en) * | 1982-08-04 | 1984-02-29 | Plessey Co Plc | Improved local area network systems |
EP0118731A1 (en) * | 1983-02-03 | 1984-09-19 | CSELT Centro Studi e Laboratori Telecomunicazioni S.p.A. | Distributed-structure circuit for arbitrating the access requests to the bus of a multiprocessor system |
EP0138676A2 (en) * | 1983-09-22 | 1985-04-24 | Digital Equipment Corporation | Retry mechanism for releasing control of a communications path in a digital computer system |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5901297A (en) * | 1994-03-01 | 1999-05-04 | Intel Corporation | Initialization mechanism for symmetric arbitration agents |
US5515516A (en) * | 1994-03-01 | 1996-05-07 | Intel Corporation | Initialization mechanism for symmetric arbitration agents |
US5581782A (en) * | 1994-03-01 | 1996-12-03 | Intel Corporation | Computer system with distributed bus arbitration scheme for symmetric and priority agents |
GB2287621A (en) * | 1994-03-01 | 1995-09-20 | Intel Corp | High performance symmetric arbitration protocol with support for I/O requirements |
US6061599A (en) * | 1994-03-01 | 2000-05-09 | Intel Corporation | Auto-configuration support for multiple processor-ready pair or FRC-master/checker pair |
GB2287621B (en) * | 1994-03-01 | 1998-12-16 | Intel Corp | High performance symmetric arbitration protocol with support for I/0 requirements |
GB2293943A (en) * | 1994-10-04 | 1996-04-10 | Motorola Israel Ltd | Communications system with priority scheme for reduced access delay |
GB2293943B (en) * | 1994-10-04 | 1998-06-17 | Motorola Israel Ltd | Communications system with priority scheme for reduced access delay |
US5754807A (en) * | 1995-11-20 | 1998-05-19 | Advanced Micro Devices, Inc. | Computer system including a multimedia bus which utilizes a separate local expansion bus for addressing and control cycles |
US5935232A (en) * | 1995-11-20 | 1999-08-10 | Advanced Micro Devices, Inc. | Variable latency and bandwidth communication pathways |
US5778200A (en) * | 1995-11-21 | 1998-07-07 | Advanced Micro Devices, Inc. | Bus arbiter including aging factor counters to dynamically vary arbitration priority |
US5761452A (en) * | 1996-03-18 | 1998-06-02 | Advanced Micro Devices, Inc. | Bus arbiter method and system |
US5805840A (en) * | 1996-03-26 | 1998-09-08 | Advanced Micro Devices, Inc. | Bus arbiter employing a transaction grading mechanism to dynamically vary arbitration priority |
US5802330A (en) * | 1996-05-01 | 1998-09-01 | Advanced Micro Devices, Inc. | Computer system including a plurality of real time peripheral devices having arbitration control feedback mechanisms |
US7995607B2 (en) * | 2004-04-28 | 2011-08-09 | Freescale Semiconductor, Inc. | Arbiter for a serial bus system |
US8254922B2 (en) | 2006-10-16 | 2012-08-28 | Stmicroelectronics, Inc. | Zero delay frequency switching with dynamic frequency hopping for cognitive radio based dynamic spectrum access network systems |
US8494546B2 (en) | 2006-10-16 | 2013-07-23 | Stmicroelectronics, Inc. | Method of inter-system communications dynamic spectrum access network systems-logical control connections |
US8503383B2 (en) | 2006-10-16 | 2013-08-06 | Stmicroelectronics, Inc. | Method of inter-system coexistence and spectrum sharing for dynamic spectrum access networks-on-demand spectrum contention |
US8780882B2 (en) * | 2008-01-16 | 2014-07-15 | Stmicroelectronics, Inc. | On-demand spectrum contention for inter-cell spectrum sharing in cognitive radio networks |
US8824432B2 (en) | 2008-01-16 | 2014-09-02 | Stmicroelectronics, Inc. | Beaconing period framing for efficient multi-channel inter-cell communications in cognitive radio networks |
Also Published As
Publication number | Publication date |
---|---|
GB2165726B (en) | 1988-07-27 |
DE3535436C2 (en) | 1991-12-05 |
DE3535436A1 (en) | 1986-04-10 |
GB8524539D0 (en) | 1985-11-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19931004 |