JPH04289587A - Multiport ram - Google Patents

Abstract

PURPOSE:When the same address is accessed from plural write port address and data are written in, any priority port data are arbitrarily set and only the priority port data become the object of write in against the same address designated from plural port addresses within a write cycle. CONSTITUTION:A, B, C write port address, a write port address data coincidence detecting circuit 12, which compares the output of these addresses, a priority write designating circuit 13, which selects priority port write data and a logic circuit, which controls the write enable signal from the outputs of the circuits 12 and 13, are provided. Thus, the contention among the write in data from the plural write ports is avoided and it prevents the data to be stored in the memory cell become unsettled.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiport RAM having a plurality of write ports.

0002

2. Description of the Related Art FIG. 2 is a circuit diagram showing an example of a write circuit for one bit in a conventional multi-port RAM having three sets of write ports. In the figure, 1 to 3 are write address decoders, 4 to 6 are N-channel field effect transistors, 7 to 9 are write drivers, and 10 and 11 are inverters.

In FIG. 2, an A port address input and a write enable input WEA are connected to the input terminal of a write decoder 1, and the output of the write decoder 1 is connected to an N channel field effect transistor 4 (hereinafter referred to as Ntr) via a write word line WWL1. ) is connected to the gate terminal G of the The B port address input and write enable input WEB are connected to the write decoder 2, and the output of the write decoder 2 is connected to the gate terminal G of Ntr5 via the write word line WWL2.

Similarly, the C port address input and write enable input WEC are connected to the write decoder 3, and the output of the write decoder 3 is connected to the write word line WWL3.
It is connected to the gate terminal G of Ntr6 via. A
The port data input DA1 is input to the write driver 7, and the output of the write driver 7 is connected to the source/drain terminal SD4A of the Ntr4.

Similarly, B port data input DB1 and C
Each port data input DC1 has a write driver 8.
, 9 to source/drain terminals SD5A and SD6A of Ntr5 and Ntr6, respectively. Source/drain terminals SD4B, S of Ntr4, 5, 6
D5B and SD6B are connected not only to each other but also to the input terminal of the inverter 10 and the output terminal of the inverter 11. The output terminal of inverter 10 is inverter 1
The inverter 10 and the inverter 11 constitute a memory cell.

Next, the write operation of this RAM will be explained. To write data to a memory cell using A port (B port, C port), set the address to A port address (B port address, C port address) and set write enable WEA (WEB, WEC) to "L". The write word line WWL1 (WWL2, WWL), which is the output of the write address decoder 1 (2, 3), is
3) becomes “H” and Ntr4 (Ntr5, Ntr6)
becomes conductive. By the light driver (8, 9),
Data is stored in the memory cell constituted by inverters 10 and 11, and the write operation is completed.

[0007]

[Problem to be Solved by the Invention] Since the conventional multi-port RAM having a plurality of write ports is configured as described above, when writing, write ports A, B
, C specify the same address, at least two of Ntrs 4, 5, and 6 become conductive. At this time, the write data is Nt
Source/drain terminals of r4, 5, 6 SD4B, SD5
B, SD6B data conflict with each other, and inverter 10
, 11 has a problem in that the data stored in them becomes undefined.

[0008] This invention was made to solve the above-mentioned problems, and a plurality of write port addresses specify the same address and data is written into a memory cell composed of inverters 10 and 11. In this case, only the arbitrarily designated port data is given priority, the priority port data is written to the designated address, and other port data designated to the same address is not written. It is an object of the present invention to provide a multi-port RAM that can avoid conflicts in write data between different ports by making it possible to specify priority port data in this manner.

[0009]

[Means for Solving the Problems] A multi-port RAM according to the present invention includes a write port address data coincidence detection circuit for comparing a plurality of write port addresses and their outputs, and a plurality of write port address data coincidence detection circuits for selecting port data to be prioritized. The present invention is characterized by comprising a priority write port designation circuit, and a logic circuit for controlling a write enable signal from this output and the output of the write port address data coincidence detection circuit.

0010

In the multi-port RAM of the present invention, when a plurality of write port addresses specify the same address during writing, the port address data coincidence detection circuit outputs a signal. This signal enables the priority write port designation circuit, enabling only the write enable signals corresponding to priority port data and port data that do not designate the same address, and prohibits writing from other port data.

[0011]

[Example] Example 1. Hereinafter, one embodiment of the present invention will be described based on the drawings. FIG. 1 shows a write circuit for 2 bits in a multiport RAM having three sets of write ports according to an embodiment of the present invention. In the figure, 1 to 3 are write address decoders, 4 to 6, 29 to 31 are N-channel field effect transistors, 7 to 9 are write drivers, 10, 11, 32,
33 is an inverter, 12 is a write port address data match detection circuit, 13 is a priority write port designation circuit, 14
~17 is a decoder, 18 is 3-input OR, 19 is 3-input N
21-22 are 5-input ANDs, 23-25 are 2-input XORs, and 26-28 are 2-input ORs.

In FIG. 1, the A, B, and C port address inputs are connected to a write address decoder coincidence detection circuit 12, and this output terminal AB is connected to a 3-input OR 18 and a 3-input NAND 19 of a priority write port designation circuit 13. Furthermore, it is connected to the enable terminal EN of the decoder 14 and the input terminal of the 5-input AND 22.

Output terminal AC is connected to 3-input OR 18 and 3-input NAND 19, as well as to the enable terminal EN of decoder 15 and the input terminal of 5-input AND 21.

The output terminal BC is connected to the 3-input OR 18 and the 3-input NAND 19, as well as to the enable terminal EN of the decoder 16 and the input terminal of the 5-input AND 20.

The input terminal AB of the decoder 14 is connected to the input terminal AB of the priority write port designation circuit 13, and the output terminals A and B are connected to the input terminals of the 5-input AND 20, 21. The input terminal AC of the decoder 15 is connected to the input terminal AC of the priority write port designation circuit 13, and the output terminals A and C
are connected to the input terminals of the 5-input AND20 and 22. The input terminal BC of the decoder 16 is the input terminal BC of the priority write port designation circuit 13, and the output terminals B and C are
It is connected to the input terminals of the 5-input AND21 and 22. Input terminals D1 and D2 of the decoder 17 are connected to input terminals D1 and D2 of the priority write port designation circuit 13,
The input terminal EN is connected to the output terminal of the 3-input OR18.

Output terminals A, B, and C of this decoder are connected to 5-input ANDs 20, 21, and 22, respectively. 3-input NAND19 is 5-input AND20, 2
1 and 22 are all connected.

The output of the 5-input AND 20 is connected together with the write enable input WEA to the input terminal of the 2-input XOR 23 and also to the input terminal of the 2-input OR 26. The output of 5 input AND21 is the write enable input WEB
It is also connected to the input terminal of the 2-input XOR 24, and also to the input terminal of the 2-input OR 27.

The output of the 5-input AND 22 is connected together with the write enable input WEC to the input terminal of the 2-input XOR 25, and also to the input terminal of the 2-input OR 28.

The outputs of the two-input XORs 23, 24, and 25 are:
Each is connected to the other input terminal of the two-input ORs 26, 27, and 28. A port address input and 2
The output of the input OR26 is connected to the input terminal of the write decoder 1, and the output of the write decoder 1 is connected to the gate terminal G of the Ntr4,29 via the write word lines WWL1 and WWL1'.

B port address input and 2 input OR2
7 is connected to write decoder 2, and the output of write decoder 2 is connected to write word lines WWL2 and WWL.
It is connected to the gate terminal G of Ntr5, 30 via 2'. Similarly, C port address input and 2 input OR
The output of 28 is connected to the write decoder 3, and the output of the write decoder 3 is connected to the write word lines WWL3 and W
It is connected to the gate terminal G of Ntr6, 31 via WL3'.

A port data input DA1 is input to the write driver 7, and the output of the write driver 7 is Ntr4,
29 source/drain terminals SD4A and SD29A. B port data input DB1 is connected to source/drain terminals SD5A, SD30A of Ntr5, 30 via write driver 8. Port data input DC1 is input to tight driver 9, and the output of write driver 9 is connected to source/drain terminals SD4A, SD31A of Ntr6, 31.

Source/drain terminals SD4B, SD5B, and SD6B of Ntrs 4, 5, and 6 are connected to each other, as well as to an input terminal of an inverter 10 and an output terminal of an inverter 11. The output terminal of inverter 10 is connected to the input terminal of inverter 11, and inverter 10 and inverter 11 constitute a memory cell.

Source/drain terminals SD29B, SD30B, and SD31B of the Ntrs 29, 30, and 31 are connected to each other, as well as to an input terminal of an inverter 32 and an output terminal of an inverter 33.

The output terminal of the inverter 32 is the inverter 3
The inverter 32 and the inverter 33 constitute a memory cell.

Next, the operation of the multiport RAM will be explained. A write operation when different addresses are specified for the A, B, and C write port address inputs will be described.

Since different addresses are set to the A, B, and C write port address inputs, the output terminals AB, AC of the write address decoder coincidence detection circuit 12
, BC all output "H". These three signals are the 3-input NAND 19 of the priority write port designation circuit 13.
This output becomes “L”, and the 5 input AND2
The outputs of 0, 21, and 22 also become "L". To write data to a memory cell, write enable input WEA (W
This is done by changing EB, WEC) from "H" to "L". This operation results in a 2-input XOR23 (24
, 25) and the output of the two-input OR 26 (27, 28) also change from "H" to "L". Write address decoder 1 (2, 3) causes write word line WWL1 (WW
L2, WWL3) changes from “L” to “H”, and Ntr4
(5, 6) are made conductive. Light driver 7 (8,
9), the A (B, C) port data is transferred to inverter 1.
Store data in memory cells composed of 0 and 11,
Finish the write operation.

2 of A, B, C light port address inputs
A write operation when the sets specify the same address will be described. The operation of the write port address data match detection circuit 13 is such that if the A port address and the B port address match, the output terminals AB, AC, and BC will be "L, H, H.
" is output. If the A port address and C port address match, "H, L, H" is output. If the B port address and C port address match, "H, H, L" is output. Next, A , B, and C port addresses all match, “L,”
If the A, B, and C port addresses all do not match, it outputs "H, H, H."

Two of the A and B light port address inputs
A case will be described in which, when the same address is designated by the same address, the contents of the A port data are preferentially written into the memory cell, and the write operation is performed at the address designated by the C port address without being constrained by the priority port data. The input terminal AB of the priority write port designation circuit 13 is set to "L" in advance. In addition, other input terminals AC, BC, D1, D
Any signal may be set to 2. When two sets of A and B write port address inputs specify the same address, the output terminal of the write port address data coincidence detection circuit 12 outputs "L" only for AB, and outputs "H" for AC and BC.

This signal is used by the priority write port designation circuit 13.
is input to the enable terminal EN of the decoder 14 of
Since the input terminal AB is set to "L" in advance, the output terminal A of the decoder 14 outputs "L". Therefore, the output of the 5-input AND20 becomes "L". Furthermore, since the AB output of the write port address data match detection circuit 13 is "L", the output of the 5-input AND22 is also "L".
”.However, all inputs of 5 input AND21 are “H”
Therefore, "L" is output.

[0030] Here, WEA, WEB, and WEC are all “H”.
” to “L” and when the write operation starts, the output of 2-input OR27 remains “H” and does not change.
The outputs of 6 and 28 change from "H" to "L". Write word lines WWL1 and WWL3' change from “L” to “H”
, Ntr4 and Ntr29 become conductive, A port data DA1 is written into the memory cell composed of inverters 10 and 11, and C port data DC1 is written into the memory cell composed of inverters 32 and 33. Therefore, when two sets of A and B write port address inputs specify the same address, the contents of the A port data are preferentially written to the memory cell, and the address specified by the C port address is not bound by the above priority port data. Contents of C port data can be written.

Similarly, when writing B port data to a memory cell preferentially over A port data, the input terminal AB of the priority write port designation circuit 13 is set to "H" and the above operation is performed.

Table 1 shows the input conditions of the priority write port designation circuit 13 when determining the priority port data for the case where each port address matches. In Table 1,
APA indicates A port address, BPA indicates B port address, CPA indicates C port address, and APD indicates A port address.
Port data, BPD indicates B port data, and CPD indicates C port data.

[0033]

[Table 1]

[0034]

As described above, according to the present invention, in a multi-port RAM having a plurality of write ports, when a plurality of write port addresses specify the same address at the time of writing, this is detected by the write port address data coincidence detection circuit. By making it possible to write port data arbitrarily set by the input of the priority write port designation circuit into the memory cell with priority over other port data, conflicts with write data from multiple write ports can be avoided. This has the effect of preventing data stored in memory cells from becoming unstable.

[Brief explanation of the drawing]

FIG. 1 is a write circuit diagram for one bit in a multi-port RAM having three sets of write ports according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a write circuit for 2 bits in a conventional RAM having three sets of write ports.

[Explanation of symbols]

1, 2, 3 Write address decoder 4, 5, 6
N-channel field effect transistors 7, 8, 9 Write drivers 10, 11 Inverter 12 Write port address data coincidence detection circuit 13
Priority light port designation circuit 14, 15, 16, 17 Decoder 18 3-input OR 19 3-input NAND 20, 21, 22 5-input AND 23, 24, 25 2-input XOR 26, 27, 28 2-input OR 29, 30, 31 N-channel field effect transistors 32, 33 Inverter

Claims (1)

[Claims] 1. In a multi-port RAM that has a plurality of write ports and can be accessed independently from each port, a write port address data matching circuit and a priority write port designation to which an output of the write port address data matching circuit is connected. 1. A multi-port RAM comprising a circuit, wherein the priority write port designation circuit is provided with an input that can arbitrarily set a priority write port when a plurality of write port address data match.