JPH04287567A - Picture element density conversion system - Google Patents

Abstract

PURPOSE:To obtain a magnification picture with excellent picture element density conservation with respect to a picture in mixture of a character picture and a pseudo intermediate tone picture, to prevent blurring of an edge part of the character picture possibly occurred at multi-value processing, to suppress production of moire stripes of pseudo contour and to realize the picture element density conversion picture with high quality. CONSTITUTION:A binary data inputted by a binary magnification circuit 2 is magnified respectively a multiple of (n) (n is an integer) in the main scanning direction and a multiple of (m) (m is an integer) in the subscanning direction. A multi-value processing circuit 3 stores a data to a memory once, extracts a picture data of an optional area, refers an area comprising a noted picture element and its surrounding picture elements to calculate the picture data of multi-value density based on a window outputted from a weight table. A magnification circuit 4 reduces/magnifies the picture data of multi-value density into an optional size by the interleave processing of a picture clock and a line synchronizing signal. A binarizing circuit 5 converts the picture data of the multi- value density into a binary data.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a pixel density conversion method, and more particularly to a pixel density conversion method for scaling binary image data to an arbitrary magnification and outputting binary image data with different pixel densities. be.

0002

[Prior Art] Conventionally, SPC (Sele
cted Pixel Coding) method, logical sum method,
Projection methods, 9-division methods, etc. are known. Each pixel density conversion method targets characters and line drawings, and S
Pixel density conversion processing is performed by simple thinning and duplication processing for each pixel, which is typified by the PC method.

[0003] Furthermore, as a pixel density conversion method for systematic dithered images, a method has been proposed in which a scaled image without moiré fringes is obtained by thinning out each dither matrix and scaling by duplication processing.

0004

However, in the conventional example described above, when simple pixel-by-pixel thinning and overlapping processing are used, relatively good images can be obtained for characters and line drawings. However, when the above processing is performed on a pseudo-halftone image whose density is expressed by the density of black pixels in a certain area, the black pixel pattern becomes blurred, and gradation blur and moire fringes occur. was there. For example, if simple pixel-by-pixel thinning and duplication processing is performed on a pseudo-halftone image obtained by the error diffusion method, the gradation becomes blurred and the image becomes noise-like. Similarly, when processing is performed on a dithered image, the period interferes with the period of the dither matrix due to thinning and duplication processing, resulting in moiré fringes.

On the other hand, in thinning and duplication processing using dither matrices as units, since the dither image expresses density in dither matrix units, it is difficult to obtain a relatively good scaled image with preserved gradation. can. However, there are drawbacks in that the conversion magnification is limited and the images that can be handled are limited to pseudo-halftone images created by dithering. The present invention was made to solve the above problems, and by converting a binarized image into density data and processing it, it is possible to perform the processing conventionally used for multivalued images. An object of the present invention is to provide a pixel density conversion method that can perform similar processing on an image containing a mixture of character images and pseudo-halftone images, and obtain a variable-magnification image with excellent density preservation.

[0006] Furthermore, by changing the window size and weighting when converting from binary to multi-value density,
A pixel density that prevents the blurring of the edges of character images that tends to occur during multilevel conversion, and at the same time suppresses the occurrence of moiré fringes and pseudo contours in pseudo-halftone images, resulting in high-quality pixel density converted images. The purpose is to provide a conversion method.

[0007]

Means and Effects for Solving the Problems In order to achieve the above object, the pixel density conversion system of the present invention has the following configuration. That is, a pixel that inputs binary image data consisting of x pixels in the main scanning direction x y pixels in the sub-scanning direction, converts it to an arbitrary size of X pixels in the main scanning direction x Y pixels in the sub-scanning direction, and outputs binary image data. In the density conversion method, an enlargement means for enlarging the image size of input binary image data as binary data to an arbitrary integer multiple of m times in main scanning and n times in sub-scanning; and during enlargement processing, the enlargement means A binary multi-value density conversion means for calculating a multi-value density from the density of a pixel of interest and its surrounding pixels for the obtained binary image data enlarged by an integer times, or for the input binary image data during reduction processing. , arbitrary scaling means for reducing the size of the multi-value density image data obtained by the binary multi-value density conversion means at an arbitrary magnification in each of the main scanning direction and the sub-scanning direction; 2) Binarize the multilevel density image data
It has a value converting means, and can scale any original image such as character images and pseudo-halftone images with high quality.For pseudo-halftone images, the original image input as binary data is converted into density data. By performing conversion processing and scaling processing, it is possible to obtain images with excellent density preservation.Furthermore, for character images, by changing the window size according to the scaling ratio, it is possible to obtain multilevel images. This prevents edge blurring that sometimes occurs, and obtains faithful pixel density converted images with preserved edges for characters and line drawings.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described in detail below with reference to the drawings. <Description of scaling processing (FIG. 2)> First, the flow of scaling processing in this embodiment will be explained in detail with reference to FIG. 2. FIG. 2 is a flowchart showing a process of scaling binary data of x pixels in the main scanning direction and y pixels in the sub-scanning direction to binary data of X pixels in the main scanning direction and Y pixels in the sub-scanning direction. First, in step S1, it is determined whether or not to perform enlargement processing in either the main scanning or sub-scanning, and if the enlargement processing is not performed,
That is, if both main scanning and sub-scanning are reduction processing, the process proceeds to step S3, but if enlargement processing is to be performed, the process proceeds to step S2.

(1) Enlargement processing When enlarging processing is performed, binary digital data of x pixels in the main scanning direction x y pixels in the sub-scanning direction is enlarged in the main scanning direction by duplication processing in the binary integer times enlargement processing in step S2. n times (
n = [X/x], where [a] represents an integer not smaller than a), magnification is changed by m times in the sub-scanning direction (m = [Y/y], where Y>y), and nx Convert to binary data of ×my pixels. Then, in step S3, the binary data obtained in step S2 is scanned pixel by pixel using a window corresponding to the magnification ratio, and multi-value density data is calculated from the pixel pattern of the binary image within the window. , nx×my
Convert to multi-level density image data of pixels. In the next step S4, the multi-level density image data of nx x my pixel size converted in step S3 is thinned out using the clock and line synchronization signal, and reduced and scaled to an arbitrary size and multi-valued of X x Y pixels. Convert to value density image data. Then, in step S5, by binarizing the multi-level density image data of X×Y pixels,
Get the value image.

(2) Reduction processing On the other hand, in the case of reduction processing, in step S3, the binary data of x×y pixels is scanned pixel by pixel using a window corresponding to the magnification ratio, and the Multi-value density data is calculated from the pixel pattern of the value image and converted into multi-value density image data of x×y pixels. Next, step S4
Now, the multilevel density image data of the x x y pixel size converted in step S3 is thinned out using the clock and line synchronization signal, and the image data is reduced and scaled to an arbitrary size.
Convert to multi-level density image data of pixels. Then, in step S5, the multi-level density image data of X×Y pixels is
By performing the value conversion process, a scaled binary image of X×Y pixels is obtained.

[0011] In the above process, when converting a binary image into multilevel density image data, window scanning is performed with different reference pixels and weighting depending on the magnification ratio, and during enlargement processing, the binary image is temporarily enlarged as it is. Thereafter, by converting the binary image into multi-value density image data, it becomes possible to obtain a variable-magnification image in which blurring of the edge portions of the image that occurs during multi-value conversion is suppressed to a minimum. Furthermore, by performing contour smoothing and enlarging processing at the time of enlarging, it is possible to interpolate the level difference in the diagonally shaded portion that occurs during overlapping enlarging, thereby obtaining a higher quality character image.

<Description of Configuration (FIG. 1)> Next, a specific device that performs the above-mentioned magnification processing will be described in detail. FIG. 1 is a block diagram showing the configuration of a pixel density conversion device in this embodiment. The constituent elements will be explained in order below. In FIG. 1, 100 is a data line that is input to this device, and binary digital data represented by 1 bit of white and black (here, black is ``1'' and white is ``0'') is transmitted. is input. When enlarging processing is performed, binary data input from the data line 100 is multiplied by n in the main scanning direction (n is an integer) in the main scanning direction and m times in the sub-scanning direction (m are integers) and output from a selector 6 (to be described later) to a multi-value converting circuit 3 via a signal line 200. Furthermore, when scaling down is performed, the binary data inputted from the data line 100 is inputted as is from the selector 6 to the multilevel conversion circuit 3. The selector 6 selects the binary data input from the signal line 200 during enlargement processing, and selects the binary data input from the signal line 100 during reduction processing, and inputs the binary data to the multi-value conversion circuit 3. do.

[0013] In the multi-value conversion circuit 3, data is temporarily stored in a memory (not shown), and image data of an arbitrary area is taken out. Then, by referring to the region consisting of the pixel of interest and its surrounding pixels, and based on the window output from the load table, multilevel density image data (for example, in the case of 6-bit output, "0
” to “63”, white is “0” and black is “63”), and this multi-valued data is output to the scaling circuit 4 via the signal line 300. Next, the scaling circuit 4 Then, the multi-level density image data outputted from the multi-level conversion circuit 3 described above is reduced and scaled to an arbitrary size by thinning processing of the image clock and line synchronization signal, and then sent to the binarization circuit via the signal line 500. 5
Output to. The binarization circuit 5 converts the multi-value data outputted from the above-mentioned scaling circuit 4 into binary data and outputs it to the data line 500.

The detailed structure of the pixel density conversion device having the above structure will be explained in detail below with reference to the related drawings. <Description of binary expansion circuit (FIGS. 3 to 5)> FIG. 3 is a block diagram showing a specific configuration of the binary expansion circuit 1 shown in FIG. 1. As shown in the figure, the binary enlarging circuit 1 includes a line buffer 210, a line buffer control section 220, a D flip-flop 230, and an image clock CL.
Simple duplication processing is performed by controlling K1, CLK2 and line synchronization signals DB1, DB2, and the binary image is enlarged. First, binary image data in which one pixel is represented by one bit is input to the line buffer 210 in synchronization with an image clock CLK1 and a line synchronization signal DB1 output from a timing control circuit 1, which will be described later. Here, when the image clock CLK1 and the line synchronization signal DB1 are enlarged by n times in the main scanning direction and m times in the sub-scanning direction, the image clock CLK2 after the overlap process is divided by n,
The line synchronization signal DB2 frequency-divided by m is selected by the timing control circuit and input to the binary expansion circuit.

Next, the binary image data input from the signal line 100 is written to the line buffer 210 by the line buffer control unit 220 in synchronization with the image clock CLK1 and line synchronization signal DB1, and is simultaneously written in synchronization with CLK1 and DB2. The data is read out and output to the signal line 240. Here, due to the relationship between DB2 and DB1, each time one line of image data is written, it is read out m times, and enlargement processing is performed by m times in the sub-scanning difference direction. As an example, FIG. 4 shows a case where the image is enlarged twice in the sub-scanning direction. As shown in the figure, image data input in synchronization with DB1 is
It is read out from the memory in synchronization with B2, and the data of the same line is output twice.

The image data read out from the line buffer 210 in synchronization with the image clock CLK1 is
The signal is input to the D flip-flop 230 via the signal line 240 and subsampled by the image clock CLK2. That is, 1-bit binary data input in synchronization with CLK1 is sampled n times by CLK2, thereby being expanded n times in the main scanning difference direction. FIG. 5 is a timing chart showing a case where the image is enlarged twice in the main scanning direction.

<Description of multivalue circuit (FIGS. 6 to 9)>
Next, a specific configuration of the multi-value quantization processing circuit 3 shown in FIG. 1 will be described below with reference to FIGS. 6 and 7. The multivalue circuit 3 in this embodiment includes line memories 31a to 31d, a shift register group 320, a load table 330, a data selector multiplexer 340, a gate group 350, an adder 360
, a data line 370 that outputs data from the load table;
Then, it is composed of a data line 380 that selects a data group of the load table 330 according to the scaling factor, and refers to an area consisting of the pixel of interest (i, j) and its surrounding pixels based on the input binary data. , calculates the average density weighted with the weight mask (here, matrix data output from the weight table 330) corresponding to each pixel in the reference area, and calculates the multilevel density data (in the case of 6 bits, the maximum value 63
).

Next, the operation of the multi-value converting circuit 3 will be explained in detail. First, when enlarging processing is performed in either the main scanning direction or the sub-scanning direction, binary image data is input from the input line 200 in synchronization with the image clock CLK2 and the line synchronization signal DB2. In addition, when performing reduction processing, binary image data is transmitted from the input line 100 to the image clock CLK2.
=CLK1, and line synchronization signal DB2 is input as is in synchronization with DB1. The input binary image data is first read into the line memory 31a of the line memory group 310, and is sequentially shifted in the sub-scanning difference direction from line memory 31b → 31c → 31d line by line in synchronization with the line synchronization signal DB2. To go.

Then, parallel data for four pixels in the sub-scanning difference direction is read out from each line memory 31a to 31d in synchronization with the image clock CLK2, and is read out from the shift register group 3.
20 is shifted and input. This shift register group 320
In , image data is sequentially shifted in synchronization with image clock CLK2, and image data having a matrix of 4 pixels x 4 lines is taken out and inputted to gate group 350 as 16 1-bit matrix data. Here, if the data latched in the shift register C3 is the pixel of interest (i, j), as shown in FIG. -1,
j-2), A3 is (i, j-2), A4 is (i+1, j
-2), similarly, B1 is (i-2, j-1) and B2 is (
i-1, j-1), B3 is (i, j-1), B4 is (i
+1,j-1), C1 is (i-2,j), C2 is (i-
1,j), C4 is (i+1,j), D1 is (i-2,j
+1), D2 is (i-1, j+1), D3 is (i, j+
1), D4 becomes the data of (i+1, j+1).

On the other hand, in the load table 330, several types of matrix data each having a size of 4×4 are stored in advance. Note that in the load table 330, the gate group 350
The total sum of matrix data output to is standardized to be the maximum value of the multi-level output (maximum 63 in the case of 6-bit output). An example of weighting for each pixel in this load table 330 is shown in FIG. For example, 90%
In the case of reduction ratio, as shown in FIG. 9(b), a 3×3 window (here, 3
The window size is set to 3×3 by setting the weights of pixels around the ×3 window to “0”. Further, if the reduction ratio is large, a flat window as shown in (c) is used, and if the reduction ratio is 50% or less, the window size is increased according to the reduction ratio.

Here, address data for selecting a window according to the magnification ratio is input to the data multiplexer 340 via the signal line 380, and one of the matrix data groups of the load table 330 is selected according to the address data. selected and input to gate group 350. Next, in the gate group 350, if the image data taken out from the latches A1 to D4 is a black pixel, the gate corresponding to each latch opens, and the numerical data output from the data selector multiplexer 340 is output to the adder 360. be done. When the image data is a white pixel, the gate corresponding to each latch is closed and "0" is output to the adder 360.

Next, in adder 360, gate group 3
The sum of the data outputted from 50 is calculated, and the result is outputted to the signal line 300 as multivalued data of the pixel of interest. In this embodiment, the signal line 380 inputs data according to the scaling factor, but for example, windows with appropriate weights for characters, line drawings, and pseudo halftone images are stored in advance in the load table 330. Then, input data including the judgment result from image area separation that identifies whether the pixel of interest is a pseudo-halftone area or a text/line drawing area, and select separate matrix data for each image area. This allows you to obtain a higher quality multivalued image.

In this embodiment, the reference pixel area for calculating multivalued data is 4 pixels x 4 lines, but it is not limited to this, and line memories, shift registers,
The reference pixel area can be easily increased or decreased by increasing or decreasing the gate or load table. <Description of variable magnification circuit (FIGS. 10 to 15)> Next, details of the variable magnification circuit 4 that performs reduction processing on multivalued image data will be described below.

First, the image reduction process by the scaling circuit 4 is performed by thinning out the image clock and the line synchronization signal. Here, since the configuration is simple, we use the SPC method (Selected
This will be explained using Pixel Coding as an example. In addition,
Prior to the description, details of the timing control circuit 1 that outputs the reduced image clock CLK3 and the line synchronization signal DB3 will be described with reference to FIG.

In the figure, 110 is a crystal oscillator that generates a basic clock, 120 is an image clock CLK1,
An image clock and line synchronization signal selection unit that outputs CLK2 and line synchronization signals DB1 and DB2; 130 is a main scanning image clock control circuit that performs arbitrary clock thinning according to the main scanning reduction rate of the scaling circuit; 140 is a scaling circuit; This sub-scanning line synchronization signal control circuit performs thinning processing of arbitrary line synchronization signals according to the sub-scanning reduction rate of the circuit.

In the above configuration, based on the reference clock CLK0 input from the outside, the image clock and line synchronization signal selection section 120 divides the basic clock according to the enlargement rate in the main scanning direction in the binary enlargement circuit 2. The selected image clocks CLK1 and CLK2 and the line synchronization signals DB1 and DB2, which are similarly determined by the magnification rate in the sub-scanning direction in the binary magnification circuit 2, are selected and output. The output image clock CLK2 is then input to the main scanning image clock control unit 130, where the input image clock CLK2 is thinned out according to the reduction ratio in the scaling circuit 4, and the image clock CLK2 of the reduced image data is CLK3 is output. Similarly, line synchronization signal DB2 thinning processing, which is reduction processing in the sub-scanning direction in scaling circuit 4, is performed in sub-scanning line synchronization signal control circuit 140, and line synchronization signal DB3 of the scaled image data is Output.

Next, the detailed operation of the main scanning image clock control section circuit 130 described above will be explained below with reference to FIG. For example, the main scanning direction is γx /Rx (γx, R
x is an arbitrary integer determined by the reduction rate) (γx <Rx), as shown in FIG. 11, if the original pixels are arranged at each distance γx, the converted pixels are arranged at each distance Rx. Here, if we set △X = Rx - γx and align the coordinates of the first original pixel and converted pixel to the origin, the difference in distance between the second original pixel and converted pixel is △x, and the third distance The difference is 2△X, and △X is added for each original pixel. Here, each time the added result becomes larger than the distance γx between the original images, the distance γx is subtracted from the added result, and at that time, one coordinate of the original image is sent. In this way, if you sequentially calculate the difference in distance between the original image and the converted image and send the coordinates of the original image according to the calculation results, the original image will be sent at a certain rate according to the reduction ratio, and the remaining pixels will be By using the pixel as a converted pixel, thinning processing is performed according to the reduction ratio. Here, if similar arithmetic processing is performed with the difference in distance between the original image and the converted image at the coordinate origin as 2/γx, the converted image will be the same as the original image so that the nearest pixel to the original image is selected. Thinning is performed using the SPC method (Select
d PixelCoding ).

Now, assuming that the pixel size in the main scanning direction of the original image is γx = 256, the operation of the main scanning image clock control circuit 130 will be described in detail with reference to FIGS. 12 and 13. In FIG. 12, 410 and 420 are D flip-flops, 430 is an 8-bit output adder having a carry signal line, and 440 is a gate circuit that applies a gate to clock CLK2. As shown, ΔX is input to adder 430 in synchronization with CLK2. Here, ΔX is a value determined according to the magnification ratio; for example, when reducing the image to 8/11, ΔX=256×11/8−256=96. Also, at the time of reset, the output of the adder 430 is γx /2=1
It becomes 28. The result of the addition process outputted to the output line 405 is inputted to the D flip-flop 420, and then inputted to the adder 430 in synchronization with CLK2. In the adder 430, D
The values output from the flip-flop 420 and the D flip-flop 420 are added in synchronization with the image clock CLK2, and ΔX is sequentially added to the previous addition result. Here, only 8 bits of data out of the output of adder 430 is returned to D flip-flop 420 via signal line 405.

Therefore, every time the addition result exceeds γx (256), γx is subtracted. Also, the image clock CLK2 input to the gate 440
Mask processing is performed by the carry signal of the adder 430 outputted from the output line 406, and an image clock CLK3 obtained by thinning out the clock of CLK2 is outputted. As shown in FIG. 13, thinning processing in the main scanning direction is performed by sampling image data input in synchronization with image clock CLK2 using CLK3. Further, the sub-scanning line synchronization signal control circuit 140 is configured similarly to the main-scanning image clock control circuit 130, performs thinning processing on the line synchronization signal DB2, and outputs DB3. Then, as in the main scanning direction, reduction in the sub-scanning direction is performed by thinning out the line synchronization signal.

In this embodiment, a case has been described in which the scaling circuit 4 thins out the original image by thinning out the image clock and the line synchronization signal. It is also possible to do this. The scaling process in this case will be described below. As described above, from the main scanning image clock control circuit 130 and the sub-scanning line synchronization signal control circuit 140 shown in FIG.
The difference in distance between the original image and the scaled image can be obtained as an output. Therefore, by weighting the original image data near the converted pixel based on the positional relationship between the original image and the scaled image, and calculating the converted pixel density, scaled multi-level density data with better density preservation than the SPC method can be obtained. be able to. As a weighting method, it is also possible to use the distance inverse proportionality method or, as shown in FIG. 15, the area occupation rate of the converted pixel relative to the original pixel. Here, the portion surrounded by a broken line in the figure is an original pixel, and the portion surrounded by a solid line is a converted pixel.

FIG. 14 is a block diagram showing the configuration of a concentration calculation circuit when area occupancy is used. In the same figure, 610 is each line memory 610a, 610b, 610
620 is a shift register group, 630 is a weighting coefficient calculation circuit that calculates the weight of each pixel from the positional relationship between the converted pixel and the original pixel, 640 is a plurality of multipliers 640a, 640b, 640c, 640d,
A multiplier group consisting of 640e, 640f, 640g, 640h, and 640i, and 650 is an adder. In such a configuration, the data of the original pixels (peripheral pixels) near the converted pixel (pixel of interest) can be obtained by the line memory group 610 and the shift register group 620 in the same way as in the case of the multilevel conversion circuit 3. . In this example, 5
When reducing by 0% or more, the converted pixel is up to 9% compared to the original pixel.
An example will be shown in which matrix data of 3 pixels x 3 lines is extracted by the above-mentioned circuit, taking into account the influence of pixels. Furthermore, as in the case of the multi-value conversion circuit 3 described above, reference pixels can be arbitrarily taken.

Next, a method for calculating the weighting coefficients output by the weighting coefficient calculation circuit 630 will be explained below. As shown in FIG. 15, the main scanning image clock control circuit 13 described above
0 and the addition result and carry signal (△xx, △yy) output from the sub-scanning line synchronization signal control circuit 140, the length of each side (Rx - △xx, γx , △xx - γx , RY - △
yy, γy, Δyy - γy). Here, Δxx and Δyy are the difference in distance between the original pixel containing the carry signal and the converted pixel. In addition, if the converted pixel does not span three original pixels, the length of each side is Rx
−Δxx, Δxx, RY −Δyy, Δyy. Next, the area occupied by the converted pixel in the original pixel is calculated from the length of each side described above. For example, the area a of the converted pixel in the original pixel A is (Rx - △xx) x (RY - △yy)
, the area b of the converted pixel occupied by the original pixel B is γx × (R
Y −△yy), and similarly, c, d, e, f, g, h
, i. Then, the individual areas a, b, c, d,
A value obtained by normalizing e, f, g, h, and i by the area of the converted pixel is used as a weighting coefficient for each corresponding pixel. Furthermore, since the weighting is uniquely determined by the distance difference △xx, △yy between the original image and the scaled image output from the main scanning image clock control circuit 130 and the sub-scanning line synchronization signal control circuit 130, △xx, The weighting data may be stored in a ROM table with Δyy as the address of the table, instead of the weighting coefficient calculation circuit 630. Further, the distance inverse proportionality method can also be constructed using a ROM.

Next, the original pixel density is weighted based on the weighting data obtained from the weighting coefficient calculation circuit 630 described above. This process is performed by the multipliers 640a to 640
In this process, the sum of the outputs from the individual multipliers is calculated by the adder 650, and is finally output as the density value of the converted image. <Description of Binarization Circuit (FIGS. 16 to 18)> FIG. 16 is a diagram showing a specific configuration example of the binarization circuit 5 shown in FIG. 1. The binarization circuit 5 converts the image data converted into multi-value data in the multi-value conversion circuit 4 into binary data again, and outputs binary scaled image data. As the binarization method, all binarization methods such as the dither method and the minimum average error method can be used. Here, an error diffusion method is used that can obtain a variable-magnification image with good density preservation by diffusing errors that occur during binarization to surrounding pixels and binarizing them.

The following describes the binarization circuit 5 using error diffusion processing.
The details will be explained with reference to the drawings. In Figure 16, 5
1a to 51d are D flip-flops for latching data, 52a to 52d are adders, 530 is a line memory for one line delay, 540 is a comparator, and 560 is an error distribution control circuit. In the above configuration, first, the multi-value (for example, 6 bits, 0 to 63) output from the scaling circuit 4
Density image data is input via the signal line 400 in synchronization with the image clock CLK3 and line synchronization signal DB3. The multilevel density data input here (target pixel position)
The original image multilevel density data corresponding to i, j) is added to the sum of errors allocated to the relevant pixel position by an adder 52d, and the value is sent from the signal line to the comparator 540 and the error allocation control circuit 560. Each is output. And comparator 540
Now, the data on the signal line is compared with a certain threshold TH (for example, 32 for 6-bit data), and if the data on the signal line is larger than the threshold TH, it is set to "1" (black), and if it is smaller, it is set to "0" ( white) to the signal line 500 in synchronization with the image clock CLK3 and line synchronization signal DB3.

Next, in the error distribution control circuit 560, according to the result of binarization, if the output is white, the data input from the signal line 550 is input, and if the output is black, the data input from the signal line 550 and the constant T( In the case of 6-bit data, error amounts 56a to 56d to be distributed to surrounding pixels are calculated using the difference from 63) as an error. As shown in FIG. 17, the error amount signals 56a to 56d correspond to the surrounding pixels (i-1, j+1), (i, j+1), (i+1, j+) when the pixel position of interest is (i, j).
1) and the error amounts already allocated to (i+1,j) are added by adders 52a to 52d, respectively. Further, here, the number of pixels to which errors are distributed is set to four pixels of interest, but the number is not limited to this and can be easily increased or decreased.

The detailed configuration of the above error distribution circuit 560 will be explained below with reference to FIG. In the figure, 561 is a subtracter, 562 is a selector, and 563a to 563d are multipliers that perform predetermined multiplication. First, the subtracter 561 calculates the difference (signal 5
50−constant T) is calculated and output to the selector 562. The selector 562 selects 2 input from the signal line 500.
Depending on the digitization result, if the binarization result is "0" (white), select the former (signal 550), and if the binarization result is "1" (black), select the latter (signal 550-T). , multiplier 563a~
Output to 563d. Here, multipliers 563a to 563
As shown in FIG. 18, d is the peripheral pixel (i-1,
j+1), (i, j+1), (i+1, j+1), (i
+1, j), and the signal lines 56a, 56b, 56c and 5 are multiplied according to the weights as shown below.
Output the result to 6d.

[0037]

[Equation 1] The binarization method described above makes it possible to obtain a variable-magnification binary image with excellent density preservation for pseudo-halftones.

[0038]

[Effects of the Invention] As explained above, according to the present invention,
Regardless of whether the input binary digital image is a pseudo-halftone image or a character image, it performs binary and multi-value conversion processing, converting each pixel to multi-value density, and then performs scaling processing, resulting in high quality images. A pseudo-halftone image can be obtained. Also, 2
When converting value data to multi-value data, during enlargement processing,
By enlarging the binary data as it is, the blurring of the edges of characters and line drawings during enlargement processing can be suppressed, and in the same way, by changing the window size and weighting when multi-valued according to the scaling ratio, high-quality binary scaling can be achieved. You can get the image.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a pixel density conversion device in this embodiment.

FIG. 2 is a flowchart showing scaling processing in this embodiment.

FIG. 3 is a block diagram showing the configuration of the binary expansion circuit shown in FIG. 1;

[Figure 4],

FIG. 5 is a timing diagram for explaining the operation of the binary expansion circuit.

[Figure 6],

FIG. 7 is a block diagram showing the configuration of the multi-value quantization circuit shown in FIG. 1;

FIG. 8 is a diagram illustrating the relationship between 4×4 image data and coordinates.

FIG. 9 is a diagram showing a weighting ratio of a window in multi-value processing.

10 is a block diagram showing the configuration of the timing control circuit shown in FIG. 1. FIG.

FIG. 11 is a diagram showing the positional relationship between an original image and a converted image in a scaling circuit.

FIG. 12 is a diagram illustrating clock thinning during reduction at an arbitrary magnification.

FIG. 13 is a timing chart illustrating reduction in the main scanning direction.

[Figure 14-1],

FIG. 14-2 is a block diagram showing the configuration of a circuit that calculates reduced pixel density through calculation.

FIG. 15 is a diagram for explaining weighting during scaling down.

16 is a block diagram showing the configuration of the binarization circuit shown in FIG. 1. FIG.

FIG. 17 is a diagram showing the relationship between a pixel of interest and pixels to which errors are allocated.

18 is a block diagram showing the configuration of the error distribution control circuit shown in FIG. 16. FIG.

[Explanation of symbols]

1 Timing control circuit 2 Binary expansion circuit 3 Multi-value circuit 4 Variable magnification circuit 5 Binarization circuit 6 Selector

Claims (3)

[Claims] Claim 1: Binary image data consisting of x pixels in the main scanning direction x y pixels in the sub-scanning direction is input, and
In a pixel density conversion method that converts to an arbitrary size of Y pixels in the sub-scanning direction and outputs binary image data, the image size of the input binary image data is multiplied by m in the main scanning direction and n times in the sub-scanning direction. an enlargement means for enlarging the binary image data by an arbitrary integral number of times, and for the binary image data enlarged by an integral number of times obtained by the enlargement means during the enlargement process, and for the input binary image data during the reduction process; Binary multi-value density conversion means that calculates multi-value density from the density of a pixel of interest and its surrounding pixels, and the size of the image data of the multi-value density obtained by the binary multi-value density conversion means in the main scanning direction and sub-scanning A pixel density conversion method characterized by having an arbitrary scaling means for reducing the size at an arbitrary magnification in each direction, and a binarization means for binarizing multi-level density image data obtained by the arbitrary scaling means. . 2. The binary multi-value density conversion means changes the window size and weighting of the binary data to be referred to during multi-value conversion according to the scaling factor of the image size. Pixel density conversion method. 3. The method further includes determining means for determining whether the pixel of interest is included in a character image area or in a pseudo halftone area, and the binary and multi-value density converting means converts the pixel into a multi-value density converter based on the determination result. Claim 1, characterized in that the window size and weighting of the binary data referred to during value conversion are changed.
pixel density conversion method.