JPH04287517A - Output buffer in semiconductor device - Google Patents

Abstract

PURPOSE:To reduce power consumption of the buffer by relatively decreasing a current flowing to the buffer. CONSTITUTION:A gate 16 provided especially is conductive every time when a high impedance state is detected in both P-channel and N-channel transistors(TRs) 2,3 of an inverter circuit 1. Then the charging of part of electric charges charged in an external additional capacitor 13 to an additional capacitor 17 provided newly and discharging of all or part of the electric charges charged in the capacitor 17 via a TR 3 of the circuit 1 are repeated alternately. Thus, the current consumption is decreased by transferring part of the charge charged in the external load capacitor once and storing it therein for a precharge period of an output buffer and discharging the charge charged up in the additional capacitor before a succeeding precharge period to an output of the inverter circuit in this way.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to an output buffer in a semiconductor device, and in particular, it relates to a low current consumption type output buffer that prevents the generation of through current when an input signal is inverted. .

0002

2. Description of the Related Art In recent years, with the miniaturization of chips equipped with various circuits made of semiconductor elements such as CMOS, there has been an increasing need to use batteries to supply power to the semiconductor devices. Therefore, it is necessary to reduce the power consumption as much as possible when each device made of semiconductor elements such as CMOS is in a predetermined driving state.

In particular, in the case of clock buffers, output buffer circuits, etc. located near the output stage of each device, the driving ability of the transistor used in the circuit varies depending on the additional capacitance driven by the circuit. However, in general, a transistor with a considerably large driving capacity is used. Therefore, for example, if a P-channel MOSFET transistor and an N-channel MOSFET transistor constituting the inverter circuit become active at the same time in an inverter circuit used for the output buffer, a through current flows through the inverter circuit. There is a problem in that it consumes unnecessary power.

However, as mentioned above, the closer the inverter circuit is to the output stage, the greater the drive capacity of the transistors used in the inverter circuit, so the through current itself also increases, resulting in a higher power consumption. There was a danger of consuming the Therefore, there is a demand for lower power consumption in the CMOS semiconductor device by reducing the through current as much as possible.

In other words, in recent years, in highly integrated semiconductor devices such as LSIs, in order to satisfy the contradictory demands of lower power consumption and higher speed, especially large drive buffers are required inside the chip. , input/output port (I/O
There is an increasing need to reduce the power consumption of input/output buffers such as ports). To deal with this problem, conventionally, a circuit as shown in FIG. 4, for example, has been used to prevent the generation of through current in the inverter circuit.

That is, in the buffer 1 constituted by an inverter circuit in which a P-channel type MOSFET transistor 2 and an N-channel type MOSFET transistor 3 are connected in series, an input signal IN from an input terminal 5 is transmitted to the inverters 20 and 21. The same input signal IN is inputted to the gate 10 of the P-channel transistor 2 via an appropriate delay circuit 6 consisting of an inverter 30, 31 and a NAND gate 9. The signal is input to the gate 11 of the N-channel transistor 3 via the delay circuit 7 and the NOR gate circuit 9.

On the other hand, the output section 12 of the buffer 1 is connected to an external load capacitor 13 consisting of a circuit group used in a subsequent stage. In other words, in such a conventional buffer,
As is clear from the timing chart shown in FIG.
A delay time d1 is given to the output waveform a of the delay circuit 6 inputted to the gate of the channel type transistor 2, and a delay time d1 is given to the output waveform a of the delay circuit 7 inputted to the gate of the N channel type transistor 3 in the inverter circuit 1. By adding a delay time d2 to the output waveform b, it is possible to avoid a situation where the P-channel transistor 2 and the N-channel transistor 3 become active at the same time, and prevent a through current from flowing through the buffer.

[0008]

[Problem to be Solved by the Invention] In other words, in the above conventional method, the time when the N-channel transistor is on does not overlap with the time when the P-channel transistor is on. However, in such a through-current generation prevention circuit, if either waveform becomes dull for some reason, the N-channel transistor and the P-channel transistor become active at the same time, preventing the through-current. There is still a risk that it will be leaked.

Furthermore, in the above-mentioned through-current generation prevention circuit, the more delay circuits are used, the less the risk that both transistors will turn on at the same time. Therefore, the manufacturing cost must increase significantly, and the layout area of the entire circuit also increases, which hinders the miniaturization and high integration of semiconductor devices.

Furthermore, in such a buffer, the output of the buffer is once precharged into the external capacitor 13, and then the charge is directly discharged through the N-channel type transistor 3 of the inverter circuit constituting the buffer. Therefore, this is the current consumption flowing through the buffer, and since the current consumption is determined by the operating cycle of the buffer x power supply voltage x load capacity, the problem is that the larger the load capacity, the more power consumption will occur. existed.

SUMMARY OF THE INVENTION An object of the present invention is to improve the drawbacks of the prior art and provide a buffer with low power consumption by distributing external load capacitance.

0012

[Means for Solving the Problems] In order to achieve the above object, the present invention employs the following technical configuration. That is, in an output buffer consisting of an input section, an output section connected to an appropriate external load capacitance, and an inverter circuit composed of a P-channel transistor and an N-channel transistor, the output buffer is connected to the input section. A high impedance circuit that detects when both transistors become high impedance based on the voltage at the gates of both transistors, a one-shot pulse generation circuit that outputs a pulse in accordance with the output of the high impedance detection circuit, and one end connected to the inverter. An output buffer of a semiconductor device, which is connected to an output part of the circuit, the other end of which is grounded via an additional capacitor, and is provided with a gate circuit which is made conductive by a pulse of the one-shot pulse generation circuit. .

[0013]

[Operation] Since the present invention employs the above-mentioned configuration, a part of the electric charge once charged to the external load capacitance during the precharge period of the buffer is transferred to the main source before the discharge period of the buffer. In the invention, since the charge in the external capacitor is reduced by transferring it to a newly added additional capacitor, the amount of current flowing through the buffer is relatively reduced when discharging the buffer, Therefore, it is possible to reduce power consumption in the buffer.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of the output buffer according to the present invention will be explained below in detail with reference to the drawings. FIG. 1 is a diagram explaining the principle of an output buffer according to the present invention, and also a diagram showing a specific example of the output buffer according to the present invention. The output buffer in FIG. 1 includes an input section 5 and an appropriate external load capacitor 1.
In the output buffer 1, which consists of an output section 12 connected to the input section 3, and an inverter circuit composed of a P-channel transistor 2 and an N-channel transistor 3, the gates of both transistors connected to the input section 5 10, 11
a high impedance circuit 14 that detects a time when both transistors become high impedance based on the voltage of the
A one-shot pulse generation circuit 15 outputs pulses in response to the output of the high-impedance detection circuit 14, one end of which is connected to the output section 12 of the inverter circuit, and the other end of which is grounded via an additional capacitor 17. , and a gate circuit 16 which is rendered conductive by a pulse from the one-shot pulse generating circuit.

That is, in the basic configuration of the buffer according to the present invention, the signal level of the input signal IN changes, for example, from "H" level to "L" level, or from "L" level to "H" level. This prevents the occurrence of a simultaneous active state in which the P-channel transistor 2 and the N-channel transistor 3 provided in the inverter circuit turn on at the same time when the level changes, thereby avoiding the generation of through current. It is configured to obtain a buffer that reduces the current flowing through the inverter circuit when discharging the inverter circuit to reduce power consumption.The principle is that the P-channel transistor 2 of the inverter circuit
and N-channel transistor 3 both detect a high impedance state, and each time the high impedance state occurs, a specially provided gate 17 is activated.
conducts and charges a part of the electric charge charged in the external load capacitor 13 to the newly provided additional capacitor 17, and a part or all of the electric charge charged in the additional capacitor 17 is transferred to the inverter. By alternately repeating the operation of discharging through the N-channel transistor 3 of the circuit, the amount of discharge current during discharging of the inverter circuit is attempted to be reduced.

Therefore, in the present invention, the gate 10 of the P-channel transistor 2 and the gate 11 of the N-channel transistor 3 are connected to each other, and the voltage at the gate of each transistor is detected. high impedance detection means 14 for detecting when the transistors are simultaneously in an off state, that is, in a high impedance state;
is provided.

The high impedance detection circuit 14 may be composed of an ENOR circuit 18 and an inverter 19 as shown in FIG. 2, for example. Further, in the buffer according to the present invention, as shown in FIG. 2, an appropriate delay circuit used in a conventional inverter circuit is provided between the gates 10 and 11 of each transistor of the inverter circuit and the input section 5. It is preferable to provide transistors 6 and 7 to prevent both transistors 2 and 3 from being turned on at the same time.

Next, in the present invention, in the high impedance detection circuit 14, the P-channel transistor 2
When the gate voltage of the P-channel transistor 2 becomes equal to or higher than the threshold voltage of the N-channel transistor 3, and the gate voltage of the N-channel transistor 3 becomes equal to or less than the threshold value of the N-channel transistor 3, an output signal is generated. is generated.

In the present invention, a one-shot pulse generation circuit 15 is provided which receives the output signal from the high-impedance detection circuit 14, and the one-shot pulse generation circuit 15 is connected to the high-impedance detection circuit. 14 and generates a one-shot pulse c. Although the configuration of the one-shot pulse generation circuit 15 is not particularly limited, it may be configured, for example, from a multi-stage inverter circuit group 22 and a NAND gate circuit 23 as shown in FIG. .

On the other hand, in the present invention, an additional capacitor 17 is newly arranged in parallel to the output section 12 of the inverter circuit in addition to the external load capacitor 13, and the additional capacitor 17 is the gate circuit 1 driven by the one-shot pulse c generated by the one-shot pulse generation circuit 15.
It is connected to the output section 12 via 6. That is, the additional capacitor 17 is connected to the external load capacitor 13 when the gate circuit 16 becomes conductive, and at least a part of the charge charged in the external load capacitor flows into the additional capacitor 17 and is charged. The inverter circuit is configured so that the charged charges are discharged via the inverter circuit when the gate circuit 16 is next turned on.

The gate circuit 16 in the present invention may be any gate circuit as long as it is driven and controlled by the one-shot pulse c of the one-shot pulse generating circuit 15 as described above. As an example, a transfer gate as shown in FIG. 2 can be used. The transfer gate is a P-channel transistor 24
and an N-channel type transistor 25 are connected facing each other, the common terminal part 26 of which is connected to the output part 12 of the inverter circuit, and the other terminal part 27 is connected to the additional capacitor 17. has been done.

In the transfer gate, the gate 28 of the P-channel transistor 24 is connected to the one-shot pulse generation circuit 15 via an inverter circuit 32, and the gate 29 of the N-channel transistor 25 is directly connected to the one-shot pulse generation circuit 15. It is connected to 15. Therefore, the transfer gate is turned on when the one-shot pulse c is generated.

The operation of the output buffer shown in FIG. 2 according to the present invention will now be explained with reference to FIG. 3. At current time t1, the signal level of the input signal IN input to the input section of the output buffer 1 changes from "L" level to "H" level.
However, the gate voltage a of the P-channel transistor 2 is not affected by the delay circuit 6. At time t2 delayed by delay time d1, the level changes from "H" to "L".

Therefore, the N-channel transistor 3 is turned off at some point after time t1 when the gate voltage b becomes equal to or lower than the threshold voltage of the N-channel transistor 3. At some point after time t2, the gate voltage a of the P-channel transistor 2 becomes
It turns on when the voltage becomes equal to or lower than the threshold voltage of the P-channel transistor 2.

Therefore, between time t1 and t2,
A high impedance state occurs in which P-channel transistor 2 and N-channel transistor 3 are simultaneously turned off. In the present invention, the high impedance detection circuit 14 is configured to operate when the gate voltage a is equal to or higher than the threshold voltage of the P-channel transistor 2 and the gate voltage b is equal to or higher than the threshold voltage of the N-channel transistor 3. The occurrence of the following state, ie, a high impedance state, is detected and output to the one-shot pulse generation circuit 15.

When the one-shot pulse generation circuit 15 generates the one-shot pulse c1 in response to the output of the high-impedance detection circuit 14, the transfer gate circuit 16 becomes conductive, and the additional capacitance 17 connects to the output section 12.
At this time, the generation timing of the one-shot pulse is adjusted so that the one-shot pulse c1 is generated before the N-channel transistor 3 is completely cut off. A part or all of the charge charged in the additional capacitor 17 can be discharged through the N-channel transistor 3 together with the charge charged in the external load capacitor.

It should be noted that the pulse generation time d3 of the one-shot pulse generation circuit in the present invention can be set as appropriate;
Needless to say, after the one-shot pulse disappears, the transfer gate circuit 16 is cut off. Next, from time t2, the signal level of the input signal IN becomes “
Until time t3 when the level changes from "H" level to "L" level,
Since the P-channel transistor 2 is turned on and the N-channel transistor 3 is turned off, there is a precharge period in which the external load capacitor 13 is charged with electric charge from the power supply.

Therefore, the level of the output signal from the output section of the buffer is at the "H" level. Next, if the signal level of the input signal IN changes from the "H" level to the "L" level at time t3, the signal level of the gate voltage a immediately changes from the "L" level to the "H" level. , on the other hand, the gate voltage b is affected by the delay circuit 7 and has a delay time d
At time t4 delayed by 2, the level changes from “L” to “H”
Change in level.

Therefore, the P-channel transistor 2 is turned off at some point after time t3 when the gate voltage a becomes equal to or higher than the threshold voltage of the P-channel transistor 2. At some point after time t4, the gate voltage b of the N-channel transistor 3 becomes
It turns on when the voltage exceeds the threshold voltage of the N-channel transistor 3.

Therefore, between time t3 and t4,
A high impedance state occurs in which P-channel transistor 2 and N-channel transistor 3 are simultaneously turned off. When the high-impedance detection circuit 14 detects such a state in the same manner as above and outputs the result to the one-shot pulse generation circuit 15, and the one-shot pulse generation circuit 15 generates the one-shot pulse c2 in response, The transfer gate circuit 16 becomes conductive again and the additional capacitor 17 is connected to the output 12 again.

At this time, since the N-channel transistor 3 is completely cut off, the external load capacitance 13
A part or all of the charge charged in the external load capacitor 13 is temporarily charged in the additional capacitor 17, and as a result, the amount of charge charged in the external load capacitor 13 is reduced. In the present invention, the amount of charge remaining in the external load capacitor 13 can be adjusted by appropriately adjusting the capacitance Ca of the external load capacitor 13, the additional capacitor 17, and the capacitor Cb. be.

Next, from time t4 until time t5 when the signal level of the input signal IN changes from the "L" level to the "H" level again, the P-channel type transistor 2 is turned off, and the N-channel type transistor 3 is turned off. is on, so
This becomes a precharge period in which the charge charged in the external load capacitor 13 during the precharge period is discharged via the N-channel transistor 3.

Therefore, the level of the output signal at the output section of the buffer is at the "L" level. Hereinafter, the waveform after time t5 is a repetition of the waveform after time t1.

[0034]

[Effects of the Invention] Since the present invention employs the above-described configuration, a part of the electric charge once charged to the external load capacitor during the precharge period of the output buffer is transferred during the discharge period of the output buffer. The current consumption can be reduced by transferring the charge to an additional capacitor added before the precharge period and accumulating it, and then releasing the charge that has been charged up to the additional capacitor to the output side of the inverter circuit before the next precharge period. It is possible.

In the present invention, by adopting such a configuration, the power supply voltage is V, the external load capacitance is Ca, the additional capacitance is Cb, and the "L" level of the output of the output buffer and " If the number of repetitions (i.e., operating frequency) with the H" level is f, the current consumption is theoretically calculated from the above equation.

[0036]

[Math 1] It is thought that this will decrease.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of an output buffer according to the present invention, and is a diagram showing a specific example of the output buffer according to the present invention.

FIG. 2 is a diagram showing another specific example of the output buffer according to the present invention.

FIG. 3 is a timing chart of the output buffer according to the present invention shown in FIG. 2;

FIG. 4 is a diagram showing an example of a conventional output buffer.

FIG. 5 is a timing chart in the output buffer shown in FIG. 4;

[Explanation of symbols]

1... Output buffer, inverter circuit 2... P-channel transistor 3... N-channel transistor 5... Input terminal 6, 7... Delay circuit 10, 11... Gate terminal 12... Output terminal 13... External load capacitor 14... High impedance Detection circuit 15...One-shot pulse generation circuit 16...Gate circuit, transfer gate circuit 17...Additional capacitance

Claims (3)

[Claims] Claim 1: In an output buffer consisting of an input section, an output section connected to an appropriate external load capacitor, and an inverter circuit composed of a P-channel transistor and an N-channel transistor, the input section and a high-impedance circuit that detects a time when both connected transistors become high-impedance based on voltages at the gates of both transistors; a one-shot pulse generation circuit that outputs a pulse in accordance with the output of the high-impedance detection circuit;
A gate circuit is provided, one end of which is connected to the output of the inverter circuit, the other end of which is grounded via an additional capacitor, and which is rendered conductive by the pulse of the one-shot pulse generation circuit. An output buffer in a featured semiconductor device. 2. Each time both a P-channel transistor and an N-channel transistor of the inverter circuit are in a high impedance state, the gate circuit is activated in response to a one-shot pulse from the one-shot pulse generating circuit. conductive, and the additional capacitor alternately repeats an operation of charging a part of the electric charge stored in the external load capacitor and an operation of discharging a part of the charged electric charge. The output buffer according to claim 1. 3. The output buffer according to claim 1, wherein a suitable delay circuit is added to each gate portion of the P-channel transistor and the N-channel transistor constituting the inverter circuit.