JPH04287514A - Pulse width modulation circuit - Google Patents

Abstract

PURPOSE:To minimize logics on an integrated circuit and to widen the scope of general-purpose application without need of an exclusive logic circuit. CONSTITUTION:The circuit employs a programmable timer counter 10 and a 1-bit output register 20 whose content is inverted by an overflow signal 111 of the said timer counter 10 and a pulse width modulation output 200 is realized as an output of the timer counter 10. Moreover, when no pulse width modulation output is required in the circuit configuration above, the timer counter acts like a usual timer counter and number of logic circuits on the integrated circuit is minimized and general-purpose applications are expanded. Furthermore, the load exerted to the software is relieved by having only to add one register able to load a count data to the said circuit constitution.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuits, and more particularly to pulse width modulation circuits built into microcomputers and microcontrollers.

0002

2. Description of the Related Art Conventional pulse width modulation circuits are comprised of dedicated logic circuits on integrated circuits. below,
An example thereof will be explained using FIG. 3.

This circuit is composed of an n-bit counter 1, an n-bit register 2, and a comparison circuit 3. A clock 100 is input to the counter 1, and n-bit counter data 101, which becomes one input of the comparator circuit 3, is output. The register 2 outputs n-bit register data 102, which becomes one input to the comparator circuit 3. The output of the comparator circuit 3 becomes a pulse width modulated output 103.

In the pulse width modulation circuit having such a configuration, the register 2 is set to any programmable value. A counter 1 counted by a clock 100 outputs n-bit counter data 101. The comparison circuit compares n-bit counter data 101 and n-bit register data 102, and when the n-bit counter data 101 is smaller than the n-bit register data 102, the low level is set, and when it is larger, the high level is pulse width modulated. Output as output 103.

[0005]

However, the conventional configuration described above requires a dedicated logic circuit as a pulse width modulation circuit, and the logic of the comparison circuit increases as the number of bits increases.

The above means that when constructed on an integrated circuit, the logic becomes large and versatility is lost.

[0007] The present invention solves the above-mentioned problems of the prior art and enables pulse width modulated output using logic circuits already constructed on an integrated circuit.

[0008]

The pulse width modulation circuit of the present invention uses a programmable timer counter and a 1-bit output register whose value is inverted by an overflow signal of the timer counter, and provides an application output of the timer counter. This enables pulse width modulation output. Furthermore, by adding one register to the timer counter into which count data can be loaded, the burden on the software is reduced.

[0009]

[Operation] With this configuration, when pulse width modulation output is not required, it can be used as a normal timer counter, the logic on the integrated circuit is also minimized, and versatility is increased.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. This circuit consists of a programmable n-bit timer counter 10 and a 1-bit output register 20 whose value is inverted by an overflow signal 111 of the timer counter 10. The timer counter 10 includes an n-bit counter 11, an n-bit register 12 for setting count data, and an overflow detection circuit 14.
Consisting of The output of the output register 20 becomes the pulse width modulated output 200.

In the pulse width modulation circuit having this configuration, in the initial state, the register 12 is programmed with a value that determines the low level time, and the output register 20 outputs the low level. From this state, the counter 11 starts counting the low level time. counter 11
While counting high level, the register 12 is prepared with a value that determines the low level time. counter 11
When overflows, an overflow signal 111 is generated and the value of the output register 20 is updated to a high level. The counter 11 is loaded with a value that determines the high level time of the register 12, and the counter 11 starts counting the high level time. While the counter 11 is counting high level, a value determining the low level time is prepared in the register 12. When the counter 11 overflows again, the value of the output register 20 is updated to low level. The counter 11 is loaded with a value determining the low level time of the register 12, and the counter 11 starts counting the low level time. By repeating the above steps, a pulse width modulated output 200 is obtained.

[0013] Also, the configuration as is can be used as a normal timer counter. As described above, according to this embodiment, a pulse width modulation circuit is realized using a programmable timer counter and a 1-bit output register that is inverted by the overflow signal of the timer counter.

A second embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing a second embodiment of the invention.

This circuit consists of a programmable n-bit timer counter 10 and a 1-bit output register 20 whose value is inverted by an overflow signal 111 of the timer counter 10. The timer counter 10 includes an n-bit counter 11, an n-bit register 12 and register 13 for setting count data, and an overflow detection circuit 14. The output of the output register 20 becomes the pulse width modulated output 200.

In the pulse width modulation circuit having this configuration, as an initial state, the count data register 12 is programmed with a value that determines the high level time, and the register 13 is programmed with a value that determines the low level time. The output register 20 outputs a low level. From this state, the counter 11 starts counting the low level time. When the counter 11 overflows, an overflow signal 111 is generated and the value of the output register 20 is updated to a high level. The counter 11 is loaded with a value that determines the high level time of the register 12, and the counter 11 starts counting the high level. When counter 11 overflows again, output register 20
The value of is updated to low level. A value determining the low level time of the register 13 is loaded into the counter 11, and the counter 11 starts counting the low level. By repeating the above operations, a pulse width modulated output 200 is obtained.

Furthermore, by setting the values of register 12 and register 13 to the same value, it can also be used as a normal timer counter.

As described above, according to this embodiment, the burden on software can be reduced by simply adding one more register in which count data can be set to the programmable timer counter.

[0019]

[Effects of the Invention] The present invention enables pulse width modulation output by simply adding a 1-bit register whose value is inverted by the overflow signal of the timer counter to a timer counter already configured on an integrated circuit. It is said that Moreover, by simply adding one more register that can set count data to the above configuration, pulse width modulation output that can reduce the burden on software is made possible.

Furthermore, it can be used as a programmable timer counter for users who do not require pulse width modulation output, so it has great versatility.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a pulse width modulation circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a pulse width modulation circuit according to a second embodiment of the present invention.

[Figure 3] Block diagram showing a conventional pulse width modulation circuit

[Description of symbols] 10 Timer counter 11 Counter 12 Register 14 Overflow detection circuit 20 Output register 100 Input clock 110 Counter output 111 Overflow signal 200 Pulse width modulation output

Claims (2)

[Claims] 1. A programmable timer counter, and a value inverted by an overflow signal of the timer counter.
A pulse width modulation circuit that uses a bit output register to enable pulse width modulation output as an applied output of the timer counter. 2. The pulse width modulation circuit according to claim 1, wherein the timer counter is provided with two registers for alternately loading count data.