JPH04287311A - Formation of polycrystalline semiconductor thin film - Google Patents
Formation of polycrystalline semiconductor thin filmInfo
- Publication number
- JPH04287311A JPH04287311A JP5193791A JP5193791A JPH04287311A JP H04287311 A JPH04287311 A JP H04287311A JP 5193791 A JP5193791 A JP 5193791A JP 5193791 A JP5193791 A JP 5193791A JP H04287311 A JPH04287311 A JP H04287311A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline semiconductor
- film
- thin film
- semiconductor thin
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000010409 thin film Substances 0.000 title claims abstract description 29
- 230000015572 biosynthetic process Effects 0.000 title claims description 6
- 239000010408 film Substances 0.000 claims abstract description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 238000001947 vapour-phase growth Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 abstract description 7
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000002441 X-ray diffraction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は、多結晶半導体薄膜を
堆積するための工程に関するものである。FIELD OF THE INVENTION This invention relates to a process for depositing polycrystalline semiconductor thin films.
【０００２】0002
【従来の技術】ガラス、石英等の絶縁基板上に多結晶シ
リコン（以下、ポリＳｉ（ｐｏｌｙ−Ｓｉ）と称する場
合がある。）薄膜を形成する技術は、液晶ディスプレイ
、センサー等の大面積入出力デバイスのスイッチング素
子駆動回路を作製する目的で現在盛んに研究されている
。[Prior Art] A technique for forming a thin film of polycrystalline silicon (hereinafter sometimes referred to as poly-Si) on an insulating substrate such as glass or quartz is used for large-area devices such as liquid crystal displays and sensors. It is currently being actively researched for the purpose of creating switching element drive circuits for output devices.
【０００３】ポリＳｉで薄膜トランジスタ（ＴＦＴ）を
作製する場合、成膜したポリＳｉ薄膜を構成するポリＳ
ｉの粒径はなるべく大きく、配向性が良いことが望まし
い。また、製造上の観点からは、膜厚は５００ｎｍ程度
以下の厚さであることが望ましい。When manufacturing a thin film transistor (TFT) using poly-Si, the poly-S constituting the formed poly-Si thin film is
It is desirable that the particle size of i is as large as possible and that the orientation is good. Further, from a manufacturing standpoint, the film thickness is preferably about 500 nm or less.
【０００４】しかし、気相成長による薄膜成長の初期の
状態をＸ線回折により観測すると、粒径は非常に小さく
、かつ結晶粒は種々の方向に向いており配向性は良くな
い。これは、気相成長による薄膜成長の一般的傾向であ
る。However, when the initial state of thin film growth by vapor phase growth is observed by X-ray diffraction, the grain size is very small and the crystal grains are oriented in various directions, with poor orientation. This is a general trend in thin film growth by vapor phase growth.
【０００５】成膜が進み、膜厚が厚くなるに従って選択
的な成長が起こる結果、粒径は大きくなり、配向性も良
い方に改善される。As the film formation progresses and the film thickness increases, selective growth occurs, resulting in a larger grain size and improved orientation.
【０００６】そこで、成膜の初期から粒径が大きく、配
向性を良くする方法には、例えばグラフォエピタキシャ
ル成長で行われているように、フォトリソグラフィーに
より基板上に微細な凹凸を予め形成する方法がある。し
かし、フォトリソグラフィーによる方法では凹凸の周期
を１００ｎｍ以下とすることは難しく、かつ工程が複雑
であるという欠点があった。[0006] Therefore, as a method for increasing the grain size and improving the orientation from the initial stage of film formation, there is a method of forming fine irregularities on the substrate in advance by photolithography, as is done, for example, in graphoepitaxial growth. There is. However, the method using photolithography has the disadvantage that it is difficult to reduce the period of the unevenness to 100 nm or less, and the process is complicated.
【０００７】[0007]
【発明が解決しようとする課題】解決しようとする問題
点は、粒径が大きく、配向性の良い多結晶半導体薄膜を
堆積する工程が複雑である点である。The problem to be solved is that the process of depositing a polycrystalline semiconductor thin film with large grain size and good orientation is complicated.
【０００８】この発明の目的は、簡単な工程で、膜厚が
薄くても、粒径が大きく、配向性の良い多結晶半導体薄
膜を形成する方法を提供することにある。An object of the present invention is to provide a method for forming a polycrystalline semiconductor thin film with a large grain size and good orientation even if the film thickness is small, using simple steps.
【０００９】[0009]
【課題を解決するための手段】この目的の達成を図るた
め、この発明によれば、絶縁基板上に多結晶半導体を成
長させた後、この層の表面側の部分のみをエッチング除
去する。そして、このエッチング後に残存した多結晶半
導体表面に、再び多結晶半導体を成長させる。In order to achieve this object, according to the present invention, after a polycrystalline semiconductor is grown on an insulating substrate, only the surface side portion of this layer is removed by etching. Then, polycrystalline semiconductor is grown again on the surface of the polycrystalline semiconductor that remains after this etching.
【００１０】この発明の実施に当たり、好ましくは、始
めに堆積する多結晶半導体物質とエッチング後に堆積す
る多結晶半導体物質とを同一とするのが良い。In practicing the invention, it is preferred that the polycrystalline semiconductor material deposited initially and the polycrystalline semiconductor material deposited after etching are the same.
【００１１】この発明の実施に当たり、好ましくは、始
めに堆積する多結晶半導体膜の厚さの半分以下の厚さの
表面側の部分のみをエッチングにより除去するのが良い
。[0011] In carrying out the present invention, it is preferable to remove by etching only a portion on the surface side that is less than half the thickness of the initially deposited polycrystalline semiconductor film.
【００１２】この発明の実施に当たり、好ましくは、多
結晶半導体として、多結晶Ｓｉを堆積するのが良い。In carrying out the present invention, it is preferable to deposit polycrystalline Si as the polycrystalline semiconductor.
【００１３】[0013]
【作用】このような作成方法によれば、多結晶半導体膜
の成膜と、エッチングという比較的簡単な工程によって
、粒径が大きく、配向性の良い多結晶半導体薄膜が形成
できるので、高品質の多結晶半導体薄膜が得られる。[Operation] According to this production method, a polycrystalline semiconductor thin film with large grain size and good orientation can be formed through a relatively simple process of forming a polycrystalline semiconductor film and etching, resulting in high quality. A polycrystalline semiconductor thin film is obtained.
【００１４】[0014]
【実施例】以下、図面を参照しながらこの発明の実施例
につき説明する。尚、図はこの発明の構成を理解できる
程度に各構成の寸法、形状および配置関係を概略的に示
したものである。また、この発明は以下に説明する実施
例に限定されるものではない。Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the drawings schematically show the dimensions, shapes, and arrangement relationships of each component to the extent that the configuration of the present invention can be understood. Further, the present invention is not limited to the embodiments described below.
【００１５】図１の（Ａ）〜（Ｃ）はこの発明を説明す
るための形成工程図であり、各図は主要工程段階での薄
膜を断面で示してある。多結晶半導体としてはＳｉ、Ｓ
ｉＣおよびＳｉＧｅがあるが、ここではＳｉを例にとっ
て説明する。FIGS. 1A to 1C are forming process diagrams for explaining the present invention, and each figure shows a cross section of a thin film at a main process stage. Si, S as polycrystalline semiconductors
Although there are iC and SiGe, Si will be explained here as an example.
【００１６】まず、絶縁基板として例えばガラス基板１
１（コーニング７０５９）を用い、これを洗浄した後プ
ラズマＣＶＤ装置内に設置する。次に、ガラス基板１１
上に多結晶Ｓｉ膜（ポリＳｉ膜ともいう。）１２を数１
０ｎｍ例えば約５０ｎｍ程度の膜厚に成膜する（図１の
（Ａ））。成膜条件は、四フッ化シラン（ＳｉＦ４）：
３００ＳＣＣＭ、モノシラン（ＳｉＨ４）：１５ＳＣＣ
Ｍ、Ｈ２：５００ＳＣＣＭ、ＲＦパワー：６０Ｗ、反応
気圧３００Ｐａ、基板温度：３００℃で行う。First, for example, a glass substrate 1 is used as an insulating substrate.
1 (Corning 7059), and after cleaning it, it is installed in a plasma CVD apparatus. Next, the glass substrate 11
A polycrystalline Si film (also referred to as poly-Si film) 12 is formed on the top by the number 1.
The film is formed to a thickness of about 0 nm, for example about 50 nm ((A) in FIG. 1). The film forming conditions were silane tetrafluoride (SiF4):
300SCCM, monosilane (SiH4): 15SCC
M, H2: 500SCCM, RF power: 60W, reaction pressure 300Pa, substrate temperature: 300°C.
【００１７】次に、ポリＳｉ膜１２を成膜したガラス基
板１１を反応性イオンエッチング装置内に設置しこの多
結晶半導体膜１２の表面側の部分のみをエッチングする
。この場合のエッチング条件は、ＣＦ４／Ｏ２（１０モ
ル％）：１００ＳＣＣＭ、ＲＦパワー：２００Ｗである
。このエッチング処理時間は、４０〜６０秒とし成膜さ
れたポリＳｉ１２が半分程度の厚さ以上残るように選択
する。尚、図１の（Ｂ）においてエッチング後に残存し
ているポリＳｉ膜を１２ａで示す。尚このエッチングを
行う目的は、次にポリＳｉ膜を再び成膜する際に、この
ポリＳｉの成膜に不都合な部分を選択的に除去すること
にある。Next, the glass substrate 11 with the poly-Si film 12 formed thereon is placed in a reactive ion etching apparatus, and only the surface side portion of the polycrystalline semiconductor film 12 is etched. The etching conditions in this case are CF4/O2 (10 mol%): 100SCCM, RF power: 200W. The etching time is selected to be 40 to 60 seconds so that more than half the thickness of the poly-Si film formed remains. In FIG. 1B, the poly-Si film remaining after etching is indicated by 12a. The purpose of this etching is to selectively remove portions that are inconvenient for poly-Si film formation when the poly-Si film is formed again next time.
【００１８】次に、これを５重量％ＨＦ水溶液に数秒間
浸水して自然酸化膜を完全に除去する。自然酸化膜が完
全に除去されると、表面が水をはじくようになるので容
易に判断出来る。Next, this is immersed in a 5% by weight HF aqueous solution for several seconds to completely remove the natural oxide film. Once the natural oxide film has been completely removed, the surface will begin to repel water, making it easy to tell.
【００１９】この後に、自然酸化膜が除去されたポリＳ
ｉ膜を１２ａが成膜された基板を再びプラズマＣＶＤ装
置内に設置し、ポリＳｉ膜１２の成膜条件と同じ条件で
、自然酸化膜を除去した表面上にポリＳｉ膜１４を所定
の膜厚に成長させる。図１の（Ｃ）に上述したようなこ
の発明による処理工程で作成した残存ポリＳｉ膜１２ａ
とポリＳｉ膜１４とから成るポリＳｉ薄膜１６を断面図
で示してある。After this, the polyS from which the natural oxide film has been removed is
The substrate on which the i film 12a has been formed is again placed in the plasma CVD apparatus, and a predetermined poly-Si film 14 is deposited on the surface from which the natural oxide film has been removed under the same conditions as the film-forming conditions for the poly-Si film 12. Let it grow thickly. FIG. 1C shows a residual poly-Si film 12a produced by the process according to the present invention as described above.
A poly-Si thin film 16 consisting of a poly-Si film 14 and a poly-Si film 14 is shown in a cross-sectional view.
【００２０】このようにして形成したポリＳｉ薄膜１６
と、途中のエッチングの処理を行わないで形成したポリ
Ｓｉ薄膜の配向性をＸ線回折により実験的に調べた。そ
の結果、（２２０）面の回折のみが観測されたのでその
強度を比較したところ、この発明の形成方法で形成した
ポリＳｉ薄膜１６では、途中の処理を行わないで形成し
たポリＳｉ薄膜に比べて約１．３倍の強度を示した。こ
れはエッチング処理におけるエッチング速度が面方向に
より異なるので、（２２０）面以外の方向の面のエッチ
ングが選択的に進むために、（２２０）方向のポリＳｉ
の結晶成長が促進するものと解釈される。The poly-Si thin film 16 thus formed
The orientation of a poly-Si thin film formed without any intermediate etching process was experimentally investigated using X-ray diffraction. As a result, only the diffraction of the (220) plane was observed, and when comparing the intensities, it was found that the poly-Si thin film 16 formed by the formation method of the present invention was compared to the poly-Si thin film formed without any intermediate treatment. It showed about 1.3 times the strength. This is because the etching rate in the etching process differs depending on the plane direction, so etching of planes in directions other than the (220) plane progresses selectively.
This is interpreted as promoting crystal growth.
【００２１】また、上述した実施例では、絶縁基板とし
てガラス基板を用いたが、これら限定されるものではな
く石英基板あるいは設計に応じた任意適当な基板を用い
ることができる。Furthermore, in the above-described embodiments, a glass substrate is used as the insulating substrate, but the present invention is not limited to this, and a quartz substrate or any suitable substrate according to the design can be used.
【００２２】また、上述した実施例で説明した各工程段
階における処理条件は単なる好適例であり、これらの処
理条件も設計に応じて適当に変更し得ることは明らかで
ある。Furthermore, the processing conditions at each process step explained in the above-mentioned embodiments are merely preferred examples, and it is clear that these processing conditions can be changed as appropriate depending on the design.
【００２３】[0023]
【発明の効果】上述した説明からも明らかなように、こ
の発明の多結晶半導体薄膜の形成方法によれば、多結晶
半導体の結晶の粒径を大きく、配向性を良くできるので
、膜厚が薄くても高品質の多結晶半導体薄膜が得られる
。Effects of the Invention As is clear from the above explanation, according to the method for forming a polycrystalline semiconductor thin film of the present invention, the grain size of the polycrystalline semiconductor crystals can be increased and the orientation can be improved, so that the film thickness can be increased. Even if it is thin, a high quality polycrystalline semiconductor thin film can be obtained.
【図１】この発明の多結晶半導体薄膜の形成方法の説明
に供する工程図である。FIG. 1 is a process diagram illustrating a method for forming a polycrystalline semiconductor thin film according to the present invention.
【符号の説明】 １１：ガラス基板 １２、１４：多結晶シリコン膜 １２ａ：残存多結晶シリコン膜 １６：多結晶シリコン薄膜[Explanation of symbols] 11: Glass substrate 12, 14: Polycrystalline silicon film 12a: Residual polycrystalline silicon film 16: Polycrystalline silicon thin film
Claims (4)
成長により堆積する工程において、絶縁基板上への多結
晶半導体薄膜の堆積を行った後、この膜の表面側の部分
のみをエッチングにより除去する工程と、エッチング後
の残存多結晶半導体薄膜上に再び多結晶半導体膜を堆積
する工程とを順に行うことを特徴とする多結晶半導体薄
膜の形成方法。Claim 1: In the step of depositing a polycrystalline semiconductor thin film on an insulating substrate by vapor phase growth, after depositing the polycrystalline semiconductor thin film on the insulating substrate, only the surface side of the film is etched. A method for forming a polycrystalline semiconductor thin film, comprising sequentially performing a step of removing the polycrystalline semiconductor film and a step of depositing the polycrystalline semiconductor film again on the polycrystalline semiconductor thin film remaining after etching.
導体膜の材料とエッチング後に堆積する多結晶半導体膜
の材料とが同一であることを特徴とする請求項１の多結
晶半導体薄膜の形成方法。2. Formation of a polycrystalline semiconductor thin film according to claim 1, wherein the material of the polycrystalline semiconductor film initially deposited on the insulating substrate and the material of the polycrystalline semiconductor film deposited after etching are the same. Method.
導体膜の厚さの半分以下の厚さの表面側の部分のみをエ
ッチングにより除去することを特徴とする請求項１の多
結晶半導体薄膜の形成方法。3. The polycrystalline semiconductor thin film according to claim 1, wherein only a surface side portion having a thickness less than half of the thickness of the polycrystalline semiconductor film initially deposited on the insulating substrate is removed by etching. How to form.
積することを特徴とする請求項１の多結晶半導体薄膜の
形成方法。4. The method for forming a polycrystalline semiconductor thin film according to claim 1, wherein polycrystalline Si is deposited as the polycrystalline semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5193791A JPH04287311A (en) | 1991-03-18 | 1991-03-18 | Formation of polycrystalline semiconductor thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5193791A JPH04287311A (en) | 1991-03-18 | 1991-03-18 | Formation of polycrystalline semiconductor thin film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04287311A true JPH04287311A (en) | 1992-10-12 |
Family
ID=12900782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5193791A Withdrawn JPH04287311A (en) | 1991-03-18 | 1991-03-18 | Formation of polycrystalline semiconductor thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04287311A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012087043A (en) * | 2010-09-21 | 2012-05-10 | Semiconductor Energy Lab Co Ltd | Needle-like microstructure and device having needle-like microstructure |
-
1991
- 1991-03-18 JP JP5193791A patent/JPH04287311A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012087043A (en) * | 2010-09-21 | 2012-05-10 | Semiconductor Energy Lab Co Ltd | Needle-like microstructure and device having needle-like microstructure |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980514 |