JPH04286797A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To write plural words of data in the lump. CONSTITUTION:At least one data setting line 12 transmitting a data setting signal is provided in the memory cell array of the semiconductor storage device, and N type MOS transistors 9a and 9b is added to the inside of memory cells 14a and 14b as a data writing circuit controlled with a data setting signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to memory cells and data setting lines thereof.

0002

2. Description of the Related Art FIG. 8 shows a static random access memory (hereinafter referred to as "static random access memory") which is one of conventional semiconductor memory devices.
1 schematically shows a general configuration of a semiconductor memory device including an SRAM (SRAM). In FIG. 8, 21 is an address buffer, 22 is an address decoder, 23 is a memory cell array, 24 is a control circuit, and 25 is a data input/output circuit. The control circuit 24 controls address input/output and data input/output through control lines 31 and 32, respectively. In the memory cell array 23, memory cells 34 that store one bit of data are arranged in a matrix consisting of rows and columns. bit line 1a,
1b, word lines 2 are passing on the left and right.

In the case of an SRAM, memory cells 34 constituting the memory cell array 23 generally have a configuration as shown in FIG. In FIG. 7, bit lines 1a and 1b are connected to storage nodes 6a and 6b through N-type MOS transistors 7, respectively. N
The gate of the N type MOS transistor 7 is connected to the word line 2, and the ON/OFF state of the N type MOS transistor 7 is controlled by the word line 2. Inside the memory cell 34,
3 represents a power supply potential, 4 represents a reference potential, 5a and 5b represent high resistance load elements, and 8a and 8b represent N-type MOS transistors.

Next, the operation will be explained. Writing and reading of data is performed through bit lines 1a and 1b by turning on N-type MOS transistor 7 when the potential of word line 2 becomes "H". Note that data is input/output to the bit line 1a, and an inverted value of the data is input/output to the bit line 1b. When the potential of the word line 2 is "L", data is held within the memory cell 34.

[0005]

[Problems to be Solved by the Invention] Since the conventional SRAM is configured as described above, it is necessary to write data one word at a time. There was a problem that multiple write operations were required and data could not be written all at once.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device that allows multiple words of specific data to be written at once. .

[0007]

[Means for Solving the Problems] A semiconductor memory device according to the present invention newly provides a data set line for transmitting at least one data setting signal within a memory cell array, and provides a data set line for transmitting at least one data setting signal to the inside or outside of the memory cell. A data write circuit controlled by a setting signal is added, and by activating the data setting signal, preset data is written into each memory cell through which the data set line passes.

[0008]

[Operation] In the semiconductor memory device according to the present invention, by activating the data setting signal, the data writing circuits provided inside or outside the memory cells corresponding to a plurality of words operate simultaneously, and the data writing circuits provided inside or outside the memory cells corresponding to a plurality of words operate simultaneously. Preset data is written into each of the plurality of memory cells.

[0009]

[Embodiment] FIGS. 1(a) and 1(b) show SRA in a semiconductor memory device according to a first embodiment of the present invention.
FIG. 3 is a diagram showing a circuit configuration of memory cells forming an M memory cell array. In both figures, 1a and 1b are bit lines for transmitting data, and are connected to storage nodes 6a and 6b, respectively, via an N-type MOS transistor 7. The gate of the N-type MOS transistor 7 is connected to the word line 2 to which the row selection signal is transmitted.
ON/OFF of the OS transistor 7 is controlled by a signal passing on the word line 2. Inside the memory cell, 3 is a power supply potential, 4 is a reference potential, 5a and 5b are high resistance load elements, and 8a and 8b are N-type MOS transistors. The configuration up to this point is the same as that of a conventional SRAM memory cell.

The structure of the memory cell of this embodiment differs from the conventional SRAM memory cell in that the structure of the memory cell is
N-type MOS transistors 9a and 9b are added, and further connected to the gate of the N-type MOS transistor 9a or the N-type MOS transistor 9b outside the memory cell.
This is the addition of a data set line 12 for transmitting data setting signals. N-type MOS transistors 9a, 9b
are connected to storage nodes 6a and 6b, respectively, and sources of N-type MOS transistors 9a and 9b are both connected to reference potential 4.

Furthermore, in FIG. 1(a), the gates of N-type MOS transistors 9a and 9b are connected to the reference potential 4 and the data set line 12, respectively, while in FIG. 1(b), on the contrary, the gates of N-type MOS transistors 9a and 9b are The gates of MOS transistors 9a and 9b are connected to data set line 12 and reference potential 4, respectively. A portion surrounded by a dotted line in FIG. 1(a) is a memory cell 14a, and a portion surrounded by a dotted line in FIG. 1(b) is a memory cell 14b.

FIG. 2 schematically shows the structure of a semiconductor memory device including the memory cells shown in FIGS. 1(a) and 1(b). The configuration of FIG. 2 is different from the configuration of a conventional device in that a data set line 12 is added within the memory cell array, and a data setting signal is further transmitted from the control circuit 24 to the data set line 12 of the memory cell array 23. This is because a data setting control line 33 has been added for this purpose.

The operation of the semiconductor memory device configured as described above will be explained below. word line 2 and bit line 1
The normal data writing operation by a and 1b is exactly the same as that of a conventional SRAM, so its explanation will be omitted here.

The data setting operation of the memory cells shown in FIGS. 1(a) and 1(b) using the data set line 12 will be explained below. First, the memory cell 14a in FIG. 1(a)
The data setting operation will be explained below. Data set line 1
The signal on word line 2 becomes “H” and the signal on word line 2 becomes “L”
When , the N-type MOS transistor 9b is in a conductive state and the N-type MOS transistors 7 and 9a are in a non-conductive state, so that the reference potential "L" is transmitted to the storage node 6b.
The potential of storage node 6a becomes "H". Therefore, data "1" is written into the memory cell 14a. Thereafter, even if the signal on the data set line 12 becomes "L", the data "1" stored in the memory cell 14 is held.

Next, the data setting operation of the memory cell 14b in FIG. 1(b) will be explained. Data set line 12
When the upper signal becomes "H" and the signal on the word line 2 is "L", the N-type MOS transistor 9a becomes conductive and the N-type MOS transistors 7 and 9b are non-conductive, so that the storage node 6a The reference potential "L" is transmitted to the storage node 6b, and the potential of the storage node 6b becomes "H". Therefore, data "0" is written into the memory cell 14b. after that,
Even if the signal on the data set line 12 becomes "L", the data "0" stored in the memory cell 14b is held.

As described above, according to this embodiment, by setting the data set line signal to "H", "1" or "0" is written to the memory cell without the normal writing operation of the SRAM. data can be written. In this case, as shown in Figures 1(a) and 1(b), N-type MO
By selecting which of the gates of S transistors 9a and 9b is connected to the reference potential and the other to the data set line, it is possible to determine whether the data to be written is "1" or "0". can be determined.

FIG. 3 also shows the memory cells 14a, 1
4b is a diagram illustrating a part of a memory cell array configured by 4b. In the figure, four memory cells in the upper, middle, and lower rows are memory cells for a first word, a second word, and a third word, respectively, and each shares one word line 2. Each word is configured to be able to store 4 bits of data. Also, 12 in the figure
The memory cells share one data set line 12.

Bit line 1a is connected to 12 memory cells in FIG.
, 1b, it is necessary to activate each word line 2 in order and write data one word at a time, but if the data set line 12 is activated, the preset data is written to all memory cells. can be written at once. For example, in the memory cell array having the configuration shown in FIG. 3, it is possible to write data "1111" into the first word, "0000" into the second word, and "1010" into the third word all at once.

As described above, according to this embodiment, memory cells for a plurality of words share the same data set line 12, and in each memory cell, which of the gates of the N-type MOS transistors 9a and 9b is set to the reference potential. connect to
If you choose to connect the other side to the data set line, by setting the data set line signal to "H", you can write any data at once to all memory cells that share these data set lines. become able to.

Furthermore, the number of data set lines 12 is increased,
In each memory cell, N corresponding to 9a and 9b in FIG.
By adding two type MOS transistors for each added data set line, it becomes possible to write two or more types of data.

An example is shown in FIG. That is, FIG. 4 shows a circuit configuration of a memory cell of a semiconductor memory device according to an application example of the first embodiment of the present invention.
The same reference numerals as in a) and (b) indicate the same parts. The configuration of FIG. 4 is characterized by the addition of N-type MOS transistors 10a, 10b and a data set line 13 to the configurations of FIGS. 1(a) and 1(b). Therefore, in the configuration of FIG. 4, it is possible to write two types of data, and by setting the signal on the data set line 12 to "H", data "1" can be written to the memory cell. The signal on the data set line 13 is set to “H”
By doing so, it is possible to write "0" data into the memory cell.

FIG. 5 shows a memory cell and its peripheral circuit configuration in a semiconductor memory device according to a second embodiment of the present invention. In the figure, Figure 1(a), (
b) The same reference numerals indicate the same or equivalent parts,
The structure of the memory cell of this embodiment differs from the conventional SRAM memory cell in that a data writing circuit 17 is provided outside the memory cell 34, and this is connected to the memory nodes 6a and 6.
b. The data write circuit 17 is an N-type MOS transistor 1
The gate of the N-type MOS transistor 16 is connected to the data set line 12, the source is connected to the reference potential 4, and the drain is connected to either one of the storage nodes 6a and 6b. When this data writing circuit 17 is connected to the storage node 6a, when the signal on the data set line 12 is "H", data "0" is stored in the memory cell.
” is written and the data writing circuit 17 is connected to the storage node 6b, data “1” is written when the signal on the data set line 12 is “H”.

Therefore, in this embodiment as well, similarly to the first embodiment, the memory cells for a plurality of words share the same data set line, and the data writing circuit 17 is configured in each memory cell. Storage nodes 6a, 6
By arbitrarily selecting which node of b to connect to, by setting the signal of the data set line 12 to "H", it is possible to write any data at once to all memory cells that share the data set line. can.

Furthermore, by adding a data set line and a circuit for writing data, it becomes possible to write two or more types of data to all memory cells that share the data set line. An example is shown in FIG. That is, FIG. 6 shows a memory cell and its peripheral circuit configuration of a semiconductor integrated circuit as an application example of the second embodiment of the invention. In the figure, the same reference numerals as in FIG. 5 indicate the same or corresponding parts, Two data set lines 12, 13 and two write circuits 1
It is characterized by having 7a and 17b. Therefore, in the configuration of FIG. 6, it is possible to write two types of data, and by setting the signal on the data set line 12 to "H", the data is transferred to the memory cell 34 via the data write circuit 17b.
By setting the signal on the data set line 13 to "H", data of "0" can be written to the memory cell via the data writing circuit 17a. can.

[0025]

As described above, according to the present invention, a data set line for transmitting at least one data setting signal is provided in a memory cell of a semiconductor memory device, and a data set line is provided inside or outside the memory cell. Since a data write circuit controlled by a data setting signal is provided, by activating the data setting signal, multiple words of data set in advance can be written to multiple memory cells at once. There is.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a circuit configuration of a memory cell of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a memory cell of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 3 is a diagram showing the configuration of a memory cell array of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a memory cell of a semiconductor memory device according to an applied example of the first embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a memory cell of a semiconductor memory device according to a second embodiment of the invention.

FIG. 6 is a diagram showing a circuit configuration of a memory cell of a semiconductor memory device according to an applied example of the second embodiment of the present invention.

FIG. 7 is a diagram showing a general circuit configuration of a memory cell of an SRAM, which is one of conventional semiconductor memory devices.

FIG. 8 is a diagram showing a general configuration of an SRAM, which is one of conventional semiconductor memory devices.

[Explanation of symbols]

1a Bit line 1b Bit line 2 Word line 3 Power supply potential 4 Reference potential 5 High resistance load element 7 N-type MOS transistor 8a N
type MOS transistor 8b N type MOS transistor 9a N type MOS transistor 9b N type MOS transistor 10a N type MOS transistor 10b N type MOS transistor 16 N type MOS transistor 12 Data set line 13 Data set lines 17a, 17b Data writing circuit 21
Address buffer 22 Address decoder 23 Memory cell array 24 Control circuit 25 Input/output circuit 31 Control line 32 Control line 33 Data setting control line 34 Memory cell

Claims (1)

[Claims] 1. A semiconductor memory device comprising a memory cell array, an address input/output line, an address decoder, and a data input/output circuit, wherein the memory cell array includes a bit line for transmitting data and a row selection signal. A plurality of word lines for transmitting a data setting signal and at least one or more data set line for transmitting a data setting signal are provided, and the data setting signal is transmitted to the inside or outside of the memory cells constituting the memory cell array. The data set line is controlled by a circuit that writes specific data to the memory cells, and by activating the data setting signal, preset data is written to each of the memory cells that share the data set line. semiconductor storage device.