JPH04286145A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve fluidity of solder, to improve manufacturing yield of a chip carrier and to shorten a manufacturing time by partly continuing a metallized layer provided on a lower surface of a leg of a cap to a metallized layer provided at a position opposed to a back surface of a chip on a lower surface of the cap. CONSTITUTION:A chip carrier 1 is hermetically sealed at a semiconductor chip 5 with a cap 6 through a solder bump 4 on an electrode 3 of a main surface of a package board 2, and a leg of the cap 6 is soldered to a peripheral edge of the main surface of the board 2 by sealing solder 7. A first metallized layer 8a provided on the lower surface of the leg of the cap 6 is connected to a second metallized layer 8b provided at a position opposed to the back surface of the chip 5 on the lower surface of the cap 6 through a third metallized layer 8c. Thus, part of melted heat transfer solder 9 rapidly flows to a gap between the board 2 and the leg of the cap 6.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuit devices, and particularly to chip carriers.
) type semiconductor integrated circuit device.

0002

2. Description of the Related Art Japanese Patent Laid-Open Nos. 62-249429 and 63-310139 disclose a chip carrier in which a semiconductor chip mounted on a package substrate is hermetically sealed with a cap.

The chip carrier described in the above-mentioned document is shown in FIG. The chip carrier 20 carries a semiconductor chip 24 via solder bumps 23 on an electrode 22 provided on the main surface of a package substrate 21 made of a ceramic material such as mullite.
This semiconductor chip 2 is bonded face down.
4 is hermetically sealed with a cap 25. The cap 25 is made of aluminum nitride (AlN)
It is made of highly thermally conductive ceramic such as solder 26 for sealing.
It is bonded to the main surface of the package substrate 21 by. Periphery of main surface of package substrate 21 and cap 25
A metallized layer 27 for improving the wettability of the sealing solder 26 is provided on each of the lower surfaces of the legs. The back surface (upper surface) of the chip 24 sealed in the cavity surrounded by the package substrate 21 and the cap 25 is bonded to the lower surface of the cap 25 with heat transfer solder 28 . This is a structure for transmitting heat generated from the chip 24 to the cap 25 through the heat transfer solder 28. In order to improve the wettability of the heat transfer solder 28, a metallized layer 27 is provided on the lower surface of the cap 25 and the back surface of the chip 24.

The inner layer of the package substrate 21 contains, for example, W.
An internal wiring 29 made of (tungsten) is formed, and the electrode 22 on the main surface side of the package substrate 21 and the electrode 22 on the lower surface side are electrically connected through this internal wiring 29. A chip carrier 20 is attached to the electrode 22 on the lower surface side.
Solder bumps 30 are bonded to serve as external terminals when the is mounted on a module board or the like.

To assemble the chip carrier, first, the solder bumps bonded to the main surface of the chip are accurately positioned on the electrodes on the main surface of the package substrate using a chip mount device. Subsequently, the package substrate on which the chip is mounted is transferred to a reflow oven in an inert gas atmosphere, and the solder bumps are heated and remelted in the reflow oven, thereby face-down bonding the chip to the main surface of the package substrate.

Next, a cap is bonded to the main surface of the package substrate using sealing solder.

[0007] Also, the back surface of the chip is bonded to the bottom surface of the cap using heat transfer solder. The operation of soldering the cap to the main surface of the package substrate and the operation of soldering the back surface of the chip to the lower surface of the cap are performed in the same process. That is, after placing preform solder on the back of the chip and then placing a cap on top of it, the preform solder is heated in a reflow oven while a weight or the like is placed on top of the cap and an appropriate load is applied. , melt. At this time, due to the load applied to the cap, a portion of the molten solder travels along the inner wall of the cap and flows into the gap between the periphery of the main surface of the package board and the legs of the cap, causing the back surface of the chip to At the same time as being bonded to the lower surface of the cap, the package substrate and the cap are bonded.

[0008]

[Problems to be Solved by the Invention] However, in the above-described chip carrier assembly method, when the preform solder sandwiched between the chip and the cap is heated and melted in a reflow oven, the lower surface of the chip is damaged due to the load applied to the cap. There was a problem in that the solder bumps were easily deformed or crushed. Furthermore, since it takes a certain amount of time for the molten solder to flow along the inner wall of the cap and into the gap between the package substrate and the cap, there is a problem in that the assembly time becomes long.

An object of the present invention is to provide a technique that can improve the manufacturing yield of chip carriers having the above-mentioned structure.

Another object of the present invention is to provide a technique that can shorten the manufacturing time of a chip carrier having the above structure.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

0012

[Means for Solving the Problems] By soldering a cap using sealing solder to the main surface of a package substrate on which a chip is mounted via solder bumps, the chip is hermetically sealed, and the cap is sealed. In a chip carrier in which the back surface of the chip is soldered to the lower surface using heat transfer solder, the sealing solder is wetted on the peripheral edge of the main surface of the package substrate and the lower surface of the leg of the cap, respectively. a first metallized layer for improving the wettability of the heat transfer solder, and a second metallized layer for improving the wettability of the heat transfer solder on a lower surface of the cap facing the back surface of the chip; The first metallized layer and the second metallized layer provided on the lower surface of the leg portion of the cap are partially continuous.

[0013]

[Operation] According to the above-described means, the first metallized layer provided on the lower surface of the leg of the cap and the second metalized layer provided on the lower surface of the cap at a location facing the back surface of the chip are partially formed. By making the solder continuous, when the preform solder sandwiched between the chip and the cap is heated and melted, a portion of the molten solder travels along the surfaces of the first and second metallized layers and reaches the main surface of the package substrate. can quickly flow into the gap between the peripheral edge of the cap and the leg of the cap.

The present invention will be explained below with reference to Examples. In addition, in all the figures for explaining the embodiment, parts having the same functions are denoted by the same reference numerals, and repeated explanation thereof will be omitted.

[0015]

[Embodiment] As shown in FIG. 1, the chip carrier 1 of this embodiment is a semiconductor chip face-down bonded via solder bumps 4 onto an electrode 3 on the main surface of a package substrate 2 made of a ceramic material such as mullite. 5 is hermetically sealed with a cap 6. The chip carrier 1 has external dimensions of length x width = 10~
It is a small device of about 14 mm x 10 to 14 mm, and it is a micro carrier for LSI chip (M
icro Carrier for LSI Chip
) is also called.

[0016] The solder bump 4 has a content of, for example, 3 to 4% by weight.
Pb/Sn alloy containing Sn (melting temperature = 32
(about 0 to 330°C). The cap 6 is made of a highly thermally conductive ceramic such as aluminum nitride (AlN), and its legs are soldered to the peripheral edge of the main surface of the package substrate 2 with sealing solder 7.

A first metallized layer 8a is provided on each of the peripheral edge of the main surface of the package substrate 2 and the lower surface of the legs of the cap 6 to improve the wettability of the sealing solder 7. The metallized layer 8a is made of, for example, Ti,
It consists of a composite metal film in which thin films of Ni and Au are deposited by a vapor deposition method.

The main surface of the package substrate 2 and the cap 6
The back surface (top surface) of the chip 5 sealed in a cavity surrounded by the bottom surface of the cap 6 is soldered to the bottom surface of the cap 6 with heat transfer solder 9. This transfers the heat generated from the chip 5 to the cap 6 through the heat transfer solder 9.
This is to convey the information to the In order to improve the wettability of the heat transfer solder 9, a second metallized layer 8b is provided on the lower surface of the cap 6 at a location facing the back surface of the chip 5. The sealing solder 7 and the heat transfer solder 9 are made of, for example, a Pb/Sn alloy (melting temperature: about 275 to 300° C.) containing about 10% by weight of Sn.

An internal wiring 10 made of W, for example, is formed in the inner layer of the package substrate 2.
0, the electrode 3 on the main surface side of the package substrate 2 and the electrode 3 on the lower surface side are electrically connected. Although not shown in the drawings, solder bumps that serve as external terminals when the chip carrier 1 is mounted on a module substrate or the like are bonded to the electrode 3 on the lower surface side. The solder bumps are made of solder having a lower melting point than the sealing solder 7, for example, about 3.0% by weight of A.
Sn/Ag alloy containing g (melting temperature = 221-22
(approximately 2℃).

FIG. 2 is a perspective view showing the inside of the cap 6. As shown in FIG. As shown in the figure, a first metallized layer 8a is provided on the lower surface (upper surface in the figure) of the legs of the cap 6, and a second metallized layer 8a is provided on the lower surface of the cap 6 at a location facing the back surface of the chip 5. The third metallized layer 8b is connected to the third metallized layer 8c provided at four locations on the inner wall of the cap 6, for example. That is, the first metallized layer 8a and the second metallized layer 8b are partially continuous through the metallized layer 8c. The metallized layers 8a, 8b, and 8c are made of, for example, the same composite metal film formed in the same process.

Next, a method of assembling the chip carrier 1 having the above structure will be explained with reference to FIGS. 3 to 5.

First, as shown in FIG. 3, the solder bumps 4 formed on the main surface of the chip 5 are accurately positioned on the electrodes 3 on the main surface of the package substrate 2. As shown in FIG. This positioning is performed using a machine such as a chip mount device. Next, the package substrate 2 is transported to a reflow oven. The inside of the reflow oven is filled with an atmosphere filled with an inert gas such as nitrogen or argon, or a reducing gas made by mixing the inert gas with hydrogen, in order to prevent the surface of the solder bumps 4 from oxidizing. . Then, by setting the temperature in the furnace to be somewhat higher than the melting temperature of the solder bumps 4 (approximately 340 to 350°C) and heating and melting the solder bumps 4, the chip 5 is attached to the main surface of the package substrate 2. Perform face-down bonding (Figure 4).

Next, as shown in FIG. 5, a heat transfer solder 9 (preform solder) having a predetermined volume is placed on the back surface of the chip 5, and a cap 6 is placed on top of it. Subsequently, in this state, the package substrate 2 is transported to a reflow oven while being held horizontally. The inside of the reflow oven is filled with an atmosphere filled with the inert gas or reducing gas in order to prevent the surface of the heat transfer solder 9 from being oxidized. Then, the temperature in the furnace is set to be somewhat higher (approximately 310° C.) than the melting temperature of the heat transfer solder 9, and the heat transfer solder 9 is heated and melted. As a result, the molten solder wets and spreads along the surface of the second metallized layer 8c, and a portion of it spreads along the surface of the third metallized layer 8c to the periphery of the main surface of the package substrate 2 and the cap 6. The solder quickly flows into the gap between the legs and becomes the sealing solder 7, and the assembly of the chip carrier 1 shown in FIG. 1 is almost completed.

In this way, the first metallized layer 8a is passed through the third metallized layer 8c provided on the inner wall of the cap 6.
According to the chip carrier 1 of this embodiment in which the and second metallized layer 8b are partially continuous, a part of the melted heat transfer solder 9 flows along the surface of the third metallized layer 8c to the package substrate. Since it quickly flows into the gap between the peripheral edge of the main surface of the cap 2 and the leg of the cap 6, the chip 5 can be sealed in a short time.

Furthermore, since the load applied to the cap is unnecessary or can be significantly reduced, deformation or crushing of the chip 5 when melting the heat transfer solder 9 can be prevented, and the assembly yield of the chip carrier 1 can be improved. will improve.

[0026] Above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say.

For example, as shown in FIG. 6, the arrangement and shape of the third metallized layer can be changed as appropriate, such as by providing the third metallized layer 8c at the four corners of the inner wall of the cap 6.

In either case, if the area of the third metallized layer is too large, excess solder will flow into the gap between the periphery of the main surface of the package substrate and the legs of the cap, resulting in the solder remaining on the back side of the chip. Due to the insufficient amount of heat solder, voids occur in the gap between the back of the chip and the bottom of the cap, reducing the heat dissipation of the chip. On the other hand, if the area of the third metallized layer is too small, it will take a long time for the solder to flow into the gap between the peripheral edge of the main surface of the package substrate and the leg of the cap. Therefore, the area of the third metallized layer needs to be optimally designed depending on the area and shape of the solder cap.

[0029]

[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions will be briefly explained as follows.
It is as follows.

A cap is soldered to the main surface of the package substrate on which the chip is mounted via solder bumps using sealing solder to hermetically seal the chip, and heat transfer solder is applied to the bottom surface of the cap. In the chip carrier in which the back surface of the chip is soldered using a method of soldering, a method for improving the wettability of the sealing solder is applied to each of the peripheral edge of the main surface of the package substrate and the lower surface of the leg of the cap. In addition to providing a first metallized layer, a second metallized layer for improving the wettability of the heat transfer solder is provided on the lower surface of the cap opposite to the back surface of the chip, and By making the first metallized layer and the second metallized layer provided on the lower surface partially continuous, it is possible to improve the manufacturing yield of the chip carrier. Moreover, the manufacturing time of the chip carrier can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a chip carrier type semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a perspective view showing a cap of this chip carrier type semiconductor integrated circuit device.

FIG. 3 is a cross-sectional view showing a method of manufacturing this chip carrier type semiconductor integrated circuit device.

FIG. 4 is a cross-sectional view showing a method of manufacturing this chip carrier type semiconductor integrated circuit device.

FIG. 5 is a cross-sectional view showing a method of manufacturing this chip carrier type semiconductor integrated circuit device.

FIG. 6 is a perspective view showing a cap of a chip carrier type semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 7 is a sectional view of a main part of a conventional chip carrier type semiconductor integrated circuit device.

[Explanation of symbols]

1 Chip carrier 2 Package board 3 Electrode 4 Solder bump 5 Semiconductor chip 6 Cap 7　Solder for sealing 8a Metallized layer 8b Metallized layer 8c Metallized layer 9 Solder for heat transfer 10 Internal wiring 20 Chip carrier 21 Package board 22 Electrode 23 Solder bump 24 Semiconductor chip 25 Cap 26　Solder for sealing 27 Metallized layer 28 Solder for heat transfer 29 Internal wiring 30 Solder bump

Claims (3)

[Claims] 1. The semiconductor chip is hermetically sealed by soldering a cap to the main surface of the package substrate on which the semiconductor chip is mounted via solder bumps using sealing solder, and the semiconductor chip is hermetically sealed to the bottom surface of the cap. A semiconductor integrated circuit device having a chip carrier formed by soldering the back side of the semiconductor chip using heat transfer solder, the semiconductor integrated circuit device having a chip carrier formed by soldering the back side of the semiconductor chip using heat transfer solder, wherein A first metallized layer for improving the wettability of the sealing solder is provided, and a first metallized layer for improving the wettability of the heat transfer solder is provided on a lower surface of the cap facing the back surface of the semiconductor chip. A semiconductor integrated circuit device, characterized in that a second metallized layer is provided, and a portion of the first metallized layer and the second metallized layer provided on the lower surface of the leg of the cap are continuous. 2. The first metallized layer and the second metallized layer provided on the lower surface of the leg portion of the cap include:
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is made of the same conductive film formed in the same process. 3. The semiconductor chip is hermetically sealed by soldering a cap using sealing solder to the main surface of the package substrate on which the semiconductor chip is mounted via solder bumps, and the semiconductor chip is hermetically sealed on the bottom surface of the cap. A semiconductor integrated circuit device having a chip carrier formed by soldering the back side of the semiconductor chip using heat transfer solder, the semiconductor integrated circuit device having a chip carrier formed by soldering the back side of the semiconductor chip using a heat transfer solder, the semiconductor integrated circuit device comprising: A first metallized layer is provided for improving the wettability of the sealing solder, and a second metallized layer is provided on the back surface of the semiconductor chip for improving the wettability of the heat transfer solder, and the A semiconductor integrated circuit device, characterized in that a portion of the first metallized layer provided on the lower surface of the leg portion of the cap extends to the back surface of the semiconductor chip.