JPH04283849A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To realize scheduling wherein threads which belong to the same task are performed with the same mini cluster. CONSTITUTION:Plural mini clusters are constituted by combining plural multi- processors and caches in plural layers, a process table 23 where the relation between threads and execution processors is recorded and a cache constitution table 24 which indicates the relation between the respective processors and mini clusters are prepared, and a job queue is prepared for each processor; and the process table is used to decide whether or not a thread which is dequeued from a processor in an idle state and a thread which is executed by the same task can be executed by an execution processor, the mini cluster that the execution processor belongs to is decided by the cache constitution table, and in this state, the processor having the shortest job queue is selected among the processors of the belonging mini clusters.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to multiprocessor systems with hierarchical caches.

0002

2. Description of the Related Art The recent development of electronic computers has been remarkable. In particular, with the advancement of microprocessors and the increase in memory capacity, computers having a configuration of a microprocessor, a cache, and a common memory have become common.

By the way, in such computers that employ a multiprocessor system having a large number of microprocessors, each processor that operates autonomously communicates closely with each other and operates in parallel while cooperating with each other. .

However, if all of these microprocessors are connected to a bus, the system may become inoperable if, for example, a large amount of traffic occurs on the bus at once.

Conventionally, as shown in FIG. 4, a mini-cluster 4 is configured by combining a plurality of microprocessors (P) 1 with a hierarchical cache having a first cache (Fc) 2 and a second cache (Sc) 3. However, there is a device in which a plurality of such mini-clusters 4 are connected to a bus 6 together with a main memory (MM) 5.

[0006] In devices having such a hierarchical cache, data consistency is guaranteed by hardware in order to facilitate programming. In other words, when the same program is executed simultaneously, even though different processors 1 access the same address A,
By making the value of A the same, data consistency is guaranteed.

[0007] This is true, for example, as shown in FIG. 4 above.
In the case of hierarchical cache, when processors (α, β) 1 of different mini-clusters 4 access the same address A,
First, address A is updated on the α side, the value of A in the first cache 2 on the α side is updated, and then the value of each second cache 3 on the α and β sides is changed, and then β
Since the value of A in the first cache 2 on the side has to be updated, it takes a lot of effort and has the disadvantage of being expensive.

On the other hand, in the configuration of such a multiprocessor type OS (operating system), there is only one ready queue for jobs, and the processors that are in an idle state after completing a job process jobs from the ready queue in order. The program is executed while extracting the .

[0009] In this case, which processor each program is executed on is determined by the state of the system.
If the switch is woken up and the system returns,
A process may be executed by a different processor than before. When a process moves from one processor to another in this way, so-called process migration occurs,
Since the contents of the cache of the processor before being moved are wasted and are not used effectively, there is also the drawback that the execution speed of the entire system is slowed down.

[0010] Conventionally, as a means to prevent such process migration, the name of the executing processor is recorded in correspondence with the process name in a process table, and a process queue is prepared for each processor. There is something. In this way, even if a process causes a task switch due to a system call, the name of the executing processor is recorded in the process table, so when a return is received from a system call, the process is executed using that processor name. All you have to do is re-execute the program, and by preventing process migration, the contents of the cache are retained without being wasted, making it possible to execute the program at high speed.

However, in a multi-threaded server, etc., where different threads access and manipulate shared global data in parallel as a programming style, when multiple threads are executed on a multiprocessor, the data space is shared. Therefore, even if the execution processor of a thread is fixed, the situation described in Figure 4 will occur frequently, and the hardware overhead (dead time) associated with communication between each processor to maintain data consistency will occur.
The disadvantage was that it became larger. This is write through,
It does not matter what protocol is used to ensure data consistency, such as copying back.

0012

[Problem to be solved by the invention] In this way, conventionally,
When attempting to run a multi-threaded server on a multiprocessor, there is a drawback that the hardware overhead associated with communication between each processor to maintain data consistency becomes large.

The present invention has been made in view of the above circumstances, and realizes scheduling that can maintain data consistency and reduce hardware overhead associated with communication between processors. The purpose is to provide a multiprocessor system with

[0014]

[Means for Solving the Problems] The present invention is a multiprocessor system that configures a plurality of mini-clusters by combining a plurality of multiprocessors and a cache consisting of a plurality of layers, and records the relationship between threads and executing processors. In addition to preparing a process table and a cache configuration table that expresses the relationship between each of the above processors and the above mini-cluster in terms of the relationship between the above hierarchical caches, a job queue is prepared for each processor, and the thread is the same as the thread dequeued from the idle processor. The availability of the execution processor for the thread executed in the task is determined from the above process table, and the mini-cluster to which the execution processor belongs is determined from the above cache configuration table, and the processor obtained according to the scheduling algorithm determined from this determination result. I try to choose. For example, the processor with the shortest jub queue among the processors in the affiliated mini-cluster is selected based on the determination result based on the cache configuration table.

[0015]

As a result, according to the present invention, it is possible to implement scheduling in which threads belonging to the same task are executed in the same mini-cluster.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. in this case,

FIG. 1 shows a schematic configuration of a multiprocessor system to which this embodiment is applied. In this case, 11 is a processor, and this processor 11 has a first cache (Fc) 12 and a second cache (Sc).
A mini-cluster 10 is configured by combining with a hierarchical cache consisting of 13, and such a mini-cluster 10
is connected to the bus 15 together with the main memory (MM) 14. Scheduling for a multiprocessor system equipped with such a hierarchical cache is performed as follows. Next, Figure 2 shows
FIG. 2 is a diagram for explaining scheduling of such a multiprocessor system.

In this case, in the symmetric multiprocessor OS, the ready queue of a processor in an idle state is indicated by reference numeral 21, and executable threads are dequeued from this ready queue 21. Then, this dequeued thread is sent to scheduler 2.
Send to 2.

The scheduler 22 has a process table 23 that records the relationship between thread numbers and execution processor names, and the above-mentioned first cache (
It has a cache configuration table 24 that records the relationship between the Fc) 12, the second cache (Sc) 13, and the mini cluster (Xc) 10, and uses threads dequeued from the ready queue 21 to update each table 23 and 24. By referring to it, threads that belong to the same task and are being executed within the same cluster are determined.

On the other hand, in each mini-cluster 10, each processor 11 has a job queue 111, 112,
113, ... are prepared, and when the mini-cluster 10 is specified, the job queue 111, 1 of each processor 11 is
A desired processor 11 is selected from the states 12, 113, 114, . FIG. 3 is a flowchart for explaining such a scheduling algorithm.

In this case, when the processor 11 in the idle state takes out the thread at the head of the ready queue 21 (step A1), this taken out thread is
It is sent to the scheduler 22. Then, the contents are compared with the contents of the process table 23, and it is determined whether there is a thread running on the same task (step A2).

[0022] Here, if it is determined that there is a thread being executed, the cache configuration table 24 is referred to and the mini-cluster (Xc) 10 is searched (step A3).
. Next, among the processors 11 belonging to the same mini-cluster (Xc) 10, job queues 111, 112,
113, . . . is selected (step A4), the job queue of this processor 11 is entered (step A5), and the subsequent execution is performed.

On the other hand, if it is determined in step A2 that there is no thread being executed, the cache effect will not be obtained no matter which processor 11 executes the job, so the job queue allocated to each processor 11 will be The processor 11 that has the shortest queue and is likely to be executed most quickly is selected (step A6), and the job queue of this processor 11 is entered (step A7) to proceed to subsequent execution.

[0024] Therefore, in this way, regarding the leading thread of the processor 11 which is in the idle state,
By comparison with the process table 23, it is determined whether there is a thread running in the same task. If it is determined that there is a thread running, the cache configuration table 24 is referred to, the mini-cluster 10 is searched, and furthermore, this The shortest processor 1 of the job queues 111, 112, 113, ... of each processor 11 belonging to the mini-cluster 10
1 is selected, it is possible to implement scheduling such that threads belonging to the same task are always executed in the same mini-cluster. This makes it possible to maintain data consistency even when a multi-thread server is executed on a multi-processor, and it also becomes possible to reduce the hardware overhead associated with communication between each processor.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be implemented with appropriate modifications without changing the gist. For example, in the above-described embodiment, a job queue and a cache configuration table are used for each process, but effects equivalent to these can be obtained by adjusting the execution priorities of threads. In addition, in this embodiment, the execution unit of the program is a thread, but the effect of the invention is remarkable in the case of a thread that shares text space and data space, but the effect of the invention is not impaired even if it becomes a process execution unit. . In addition, in the above, the processor with the shortest jub queue among the processors in the mini-cluster to which it belongs is selected based on the determination result based on the cache configuration table, but the mini-cluster to which the executing processor belongs is determined based on the cache configuration table, The processor may be selected according to a schedule algorithm determined from the above.

[0026]

[Effects of the Invention] According to the multiprocessor system of the present invention, it is possible to implement scheduling such that threads belonging to the same task are executed in the same mini-cluster, so data consistency can be maintained. This makes it possible to implement scheduling that reduces hardware overhead associated with communication between processors. Furthermore, since process migration is suppressed, hierarchical caches can be used efficiently, and computing power can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of an embodiment of a multiprocessor system of the present invention.

FIG. 2 is a diagram for explaining scheduling in the same embodiment.

FIG. 3 is a flowchart for explaining the scheduling algorithm of the embodiment.

FIG. 4 is a diagram for explaining an example of a conventional multiprocessor system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10... Mini cluster, 11... Processor, 12... First cache, 13... Second cache, 14... Main memory, 15... Bus, 21... Ready queue, 22... Scheduler, 23... Process table, 24... Cache configuration table.

Claims (1)

[Claims] 1. In a multiprocessor system in which a plurality of mini-clusters are configured by combining a plurality of multiprocessors and a cache consisting of a plurality of hierarchies, a process table for recording the relationship between threads and executing processors, and a process table for recording the relationship between each of the processors and the mini-cluster. In addition to preparing a cache configuration table representing the relationship of the hierarchical caches in terms of the hierarchical cache relationship described above, a job queue is prepared for each of the above processors, and the execution processor of the thread that is executed in the same task as the thread dequeued from the idle processor is prepared. The process table is used to determine whether or not the executing processor is available, the mini-cluster to which the execution processor belongs is determined from the cache configuration table, and the processor is selected based on the results of these determinations according to a predetermined scheduling algorithm. Features a multiprocessor system.