JPH04282893A - Manufacture of thin-film multilayer substrate - Google Patents

Abstract

PURPOSE:To increase the performance and reliability of a via and a conductor inside the layer, in a method of manufacturing a thin-film multilayer substrate which is required to be fine and multilayered. CONSTITUTION:On the base material 51 of a substrate, lower conductor interconnections 52a, 52b are formed and then a via 55 is formed. After that, an insulated layer 60 is formed in such a depth that the surface 60a may be flat without being affected by the shape of the via 55, etc. Then, the insulated layer 60 is dry-etched to form a flat surface 60a with the end of the via 55 being exposed. On the flat surface 60b, an upper conductor interconnection is formed in such a condition that it may be brought into contact with the via 55. By this method, the via is formed independently and thereby the structure is strong and the upper conductor interconnection has no unevenness. Therefore, the electric performance and reliability can be increased.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film multilayer substrate, and more particularly to a method for manufacturing a thin film multilayer substrate that requires finer patterns and multilayering.

[0002] In recent years, as computer systems have become faster, the printed circuit boards used have become finer and finer.
There are demands for larger substrate sizes and multilayer substrates, and thin film multilayer substrates are being provided to meet these demands. And even in this thin film multilayer substrate, the pattern becomes finer,
Multi-layering is being promoted, and as a result, interconnection VIA (hereinafter simply referred to as "buyer") between layers is being miniaturized and multi-layered.
It is desired to improve the reliability of conductor wiring, etc. on a substrate.

0003

8 to 10 are diagrams showing each step of an example of a conventional method for manufacturing a thin film multilayer substrate.
A series of manufacturing steps are shown sequentially from (A) through FIG. 9 to FIG. 10(D).

First, as shown in FIG. 8(A), a lower conductor wiring 2 is formed on a base material 1 of a substrate, and subsequently, an insulating layer 3 is formed on its upper surface as shown in FIG. 8(B).

Next, a metal film 4 for a metal mask, which will be a mask when forming a via hole 3a to be described later, is shown in FIG.
As shown in C), it is formed on the insulating layer 3 by sputtering. Then, as shown in FIG. 8(D), a resist pattern 5 having a via hole pattern 5a is further formed on the upper surface by exposure and development.

Next, using the resist pattern 5 as a mask, the metal film 4 for the metal mask is wet-etched.
As shown in FIG. 8E, a via hole pattern 6a is formed in the metal film 4 for metal mask. The metal film 4 for metal mask on which the via hole pattern 6a is formed becomes the metal mask 6 at this point.

Next, using this metal mask 6 as a mask, the insulating layer 3 is dry-etched to form a via hole 3a in the insulating layer 3 as shown in FIG. 9(A). Then, the unnecessary metal mask 6 is removed by wet etching to complete a series of steps of forming the via hole 3a in the insulating layer 3 (FIG. 9(B)).

Next, vias and upper layer conductor wiring are formed. First, as shown in FIG. 9C, a base metal film 7 is formed by sputtering on the entire upper surface of the insulating layer 3 and on the inner surface of the via hole 3a.

Next, a resist pattern 8 for forming vias and upper layer conductor wiring is formed. This is first shown in Figure 9.
As shown in (D), a resist 9 is applied on the base metal film 7, and a mask 10 having vias and patterns 10a and 10b of upper layer conductor wiring is placed on the upper surface thereof. Then, by exposing and developing the substrate in this state, as shown in FIG.
As shown in (E), a resist pattern 8 having vias and upper layer conductor wiring patterns 8a and 8b is formed.

Next, using this resist pattern 8 as a mask, electrolytic plating is performed on the underlying metal film 7, as shown in FIG. 10(A).
As shown in FIG. 2, vias 11 and upper layer conductor wirings 12 and 13 are formed. Then, the unnecessary resist pattern 8 is removed (FIG. 10(B)), and subsequently the unnecessary base metal film 7 is also removed.

Through the above steps, as shown in FIG. 10C, upper layer conductor wires 12 and 13 are formed on the upper surface of the insulating layer 3, and the upper layer conductor wire 12 and the lower layer conductor wire 2 are formed as upper layer conductor wires. The via 11 formed integrally with the layer 12 electrically connects the layers.

Furthermore, by repeating the above-mentioned steps shown in FIGS. 8(B) to 10(C), FIG.
), the insulating layer 14, upper layer conductor wiring 15, 16,
and vias 17 are formed further above the upper layer conductor wirings 12 and 13, and a two-layer thin film substrate is formed on the base material 1. Furthermore, a thin film multilayer substrate has been formed by stacking a large number of such layers.

[0013]

[Problem to be Solved by the Invention] In the process shown in FIG. 10A in which vias 11 and upper layer conductor wirings 12 and 13 are formed on base metal layer 7 by electrolytic plating, along the inner surface of via hole 3a, The formed via 11 has poor growth of electrolytic plating, and the upper layer conductor wiring 12 is exposed on the upper surface.
The amount of conductor deposited due to plating is small compared to . This is the corner 3b at the entrance of the via hole 3a as shown in the same figure.
This is particularly noticeable at the corner 3b, and the conductor attached to the corner 3b becomes extremely thin compared to the surrounding area. Therefore, there is a high possibility that the via 11 will break at this thin portion due to various stresses, reducing the reliability of the interlayer connection in the thin film multilayer substrate.

Furthermore, as shown in FIG. 8(B), the insulating layer 3
is formed on the upper part of the lower layer conductor wiring 2 and its surface becomes uneven, so the upper layer conductor wiring 12 becomes uneven as shown in FIG. 10(C), and the other upper layer conductor wiring 13
There will be a difference between the two. As shown in FIG. 10(D), the uneven shape of the upper layer conductor wiring and the level difference between multiple upper layer conductor wirings become larger as the number of layers increases, and as a result, the following three Challenges arise.

■As shown in FIG. 9(D), since the mask 10 used to form the resist pattern 8 is in the form of a flat plate with a flat surface, it is coated along the uneven surface of the insulating layer 3 and similarly coated. A gap 18 is generated between the uneven surface 9a of the resist 9 and this mask 10. If exposure is performed in this state, light wraparound and light diffusion will occur between the gaps 18, and the shape of the pattern will be distorted as seen in the pattern 8b in FIG. 9(E). accuracy will decrease.

■As shown in FIG. 10(C), the distance T1 between the upper layer conductor wiring 12, 13 and the lower layer conductor wiring 2 is
, T2 have different dimensions, which affects the impedance characteristics between the conductor wirings, which is unfavorable in terms of the electrical characteristics of the thin film multilayer substrate.

■As shown in FIG. 10(D), when a plurality of layers are laminated and the uneven shape becomes severe as in the upper layer conductor wiring 15,
Stress is concentrated on the strongly sloped portion 15a, etc., increasing the possibility of wire breakage at this portion, and reducing the reliability of the intralayer conductor wiring.

The various problems mentioned above have hindered the miniaturization and multilayering of thin film multilayer substrates.

The present invention has been made in view of the above problems, and provides a method for manufacturing a thin film multilayer board that improves the reliability of interlayer connections using vias and intralayer conductor wiring, and allows for finer patterns and multilayering. The purpose is to

[0020]

[Means for Solving the Problems] FIG. 1 is a flowchart showing the principle configuration of the present invention.

In order to achieve the above object, the present invention provides a method for manufacturing a thin film multilayer board in which upper layer conductor wiring and lower layer conductor wiring disposed above and below with an insulating layer interposed therebetween are interlayer connected by vias. First, a via forming step (step 22) is performed in which only the vias are formed on the lower layer conductor wiring formed on the substrate base material, and then an upper layer in which the upper layer conductor wiring is formed on the insulating layer. Conductor wiring formation process (
This is a configuration for performing step 25).

[0022] As a specific manufacturing method, in a method for manufacturing a thin film multilayer board in which upper layer conductor wiring and lower layer conductor wiring disposed on the upper and lower sides with an insulating layer interposed therebetween are interlayer connected by vias, the substrate base material is a lower layer conductor wiring forming step (step 21) of forming the lower layer conductor wiring thereon; and a via forming step (step 21) of forming the vias on the lower layer conductor wiring before forming the insulating layer on the lower layer conductor wiring. Step 22) and
an insulating layer forming step of forming the insulating layer on the substrate base material to a thickness that can form a flat first surface without being affected by the shapes of the lower conductor wiring and the vias; step 23), etching the insulating layer uniformly from the first surface until the tip of the via is exposed, and etching the insulating layer flattened at a height where the tip of the via is exposed. an insulating layer etching step (step 24) for forming a second surface; and an upper layer conductor wiring forming step (step 25) for forming the upper layer conductor wiring on the second surface in contact with the via. , as shown in Figure 1,
This is a configuration in which the process proceeds sequentially from step 21 to step 25.

[0023]

[Operation] By forming the vias and the upper layer conductor wiring separately, the vias and the upper layer conductor wiring can be formed individually under optimal conditions. In other words, compared to the conventional method of forming vias by plating, it is possible to form vias into shapes and configurations that suit the purpose, and the vias do not have weak parts like conventional methods. can do. As a result, disconnection of the vias is prevented.

In addition, in the specific manufacturing method, since a flat first surface is formed on the insulating layer formed on the lower conductor wiring in the insulating layer forming step, the insulating layer is formed in the insulating layer etching step. When the layer is etched more uniformly than the surface, the etching progresses while the surface of the insulating layer remains flat. When the etching is completed, the tip of the via is exposed on the second surface of the flat insulating layer. Therefore, the upper layer conductor wiring formed on the second surface of the insulating layer in the upper layer conductor wiring forming step contacts the tip of the via and has a flat plate shape with no unevenness. There is also no difference in level between the conductive layer and the upper layer conductor wiring.

[0025]

[Example] FIG. 2 is a flowchart of an embodiment of the method for manufacturing a thin film multilayer substrate according to the present invention, and FIG. 3 shows the states in each step from the lower layer conductor wiring forming step 31 to the second sputtering step 35 in FIG. FIG. 4 is a diagram showing the states in each process from the first resist pattern stripping step 36 to the dry etching step 39 in FIG. 2, and FIG. A diagram showing the state in each step up to the (Cu) plating step 43, FIG. 6 shows the second resist pattern peeling step 44 and the second ion milling etching step 4 in FIG.
7 is a diagram showing an example of a thin film multilayer substrate in which a plurality of layers of conductor wiring are formed by the thin film multilayer substrate manufacturing method of this embodiment.

Each step shown in FIG. 2 will be explained with reference to FIGS. 3 to 7.

First, a lower conductor wiring forming step 31 is performed. As shown in FIG. 3(A), lower conductor wiring 52a, 5 made of copper (Cu) is placed on the upper surface 51a of the base material 51 of the board.
2b is formed.

Next, a first sputtering step 32 is performed. As a result, a metal film 53 having a thickness of about 1 μm is uniformly formed on the base material 51 and the lower conductor wirings 52a and 52b, as shown in FIG. 3(B). This metal film 53 is the lower conductor wiring 52a.
, 52b to a thickness of about 0.2 μm, and copper (Cu) 53a sputtered above it to a thickness of about 1 μm to form a two-layer structure. Copper (Cu) 53a is the main material of the metal film 53, and chromium (Cr) 53b is the main material of the metal film 53.
3a has the effect of preventing peeling off from the lower layer conductor wirings 52a, 52b.

Next, a first resist pattern forming step 33 is performed to form a resist pattern on this metal film 53. A normal resist technique is used for this, and first, a resist is applied to the metal film 53 to a thickness of about 10 μm, and a mask with a pattern is placed on the upper surface of the resist and exposed and developed, as shown in FIG. As shown in (C), a resist pattern 54 having a via pattern 54a is formed.

Next, a first electrolytic copper (Cu) plating step 34 is performed. Here, electrolytic plating is performed using the resist pattern 54 as a mask and the metal film 53 as an electrode. As a result, plating is sequentially grown within the via pattern 54a from the top surface of the metal film 53, and as shown in FIG. 3(D), a conductor that will become the via 55 is formed within the pattern 54a.

Next, a second sputtering step 35 is performed. This is done in order to form a dry etching resistant metal such as platinum (Pt) on the surface of the via 55 so that the via 55 will not be eroded by the dry etching that will be performed later. Through this process, as shown in FIG.
and is uniformly formed on the surface of the via 55.

Next, the first resist pattern stripping step 36
I do. Here, by passing the substrate in the state shown in FIG. 3E through a stripping solution, the resist pattern 54 that is no longer needed after the formation of the vias 55 is completed is stripped and removed. Further, as described above, since the metal film 56 is required only on the surface of the via 55, the metal film 56 on the resist pattern 54 is removed by using the peeling and removal of the resist pattern 54 (lift-off method). FIG. 4A shows a state in which the resist pattern 54 and unnecessary portions of the metal film 56 have been removed.

Next, a first ion milling etching step 37 is performed. Metal film 53 by first sputtering process 32
is formed for the purpose of forming the via 55, and is unnecessary at this point. Therefore, as shown in FIG. 4B, ion milling etching is performed using argon (Ar) gas 57 to remove the metal film 53 except for the via 55 portion. Here, since the dry etching resistant metal film 56 is formed on the upper surface of the via 55 as described above, this ion milling etching is also effective and corrosion of the via 55 is prevented.

From the first sputtering step 32 to this first
A series of steps up to the ion milling etching step 37 constitute a via forming step in which the via 55 is formed on the lower conductor wiring 52a.

Next, an insulating layer is formed by a polyimide coating/thermal curing step 38. This is thermosetting polyimide 61
As shown in FIG. 4(C), this is applied uniformly to the entire surface of the base material 51 on which the lower conductor wirings 52a, 52b, etc. are formed, and then placed in a nitrogen (N2) baking oven (not shown). The insulating layer 60 is formed by heat curing.

Thermosetting polyimide 61 coated here
Consider the film thickness. Vias 55, lower layer conductor wirings 52a, 52b, etc. are formed on the base material 51 to form an uneven shape. For this reason, the applied thermosetting polyimide 61
If the film thickness is small, the surface 60a' of the insulating layer 60' becomes uneven due to the shape of the lower part, as shown by the dashed line in FIG. 4(C), and the conventional problem occurs here as well. I end up. Therefore, as shown by the solid line in FIG. 4(C), when the insulating layer 60 is formed with a film thickness that is approximately twice the height of the tip of the via 55, the surface 60a of the insulating layer 60 will overlap the via 55 and the lower layer. It is no longer affected by the shape of the conductor wirings 52a, 52b, and a flat surface without any unevenness is obtained.

Next, a dry etching step 39 is performed. This is RIE (Reactive Ion Etchi)
ng = reactive ion etching) equipment, oxygen gas (
The insulating layer 60, which is an organic material, is etched using O2) or (O2+CF4) gas. At this time, as shown in FIG. 4(D), the substrate is installed in the apparatus so that the irradiation direction of the reactive ions 58 directly faces the flat surface 60a of the insulating layer 60. In this way, the erosion of the insulating layer 60 by etching progresses uniformly from the original surface 60a, and the new surface formed by etching the insulating layer 60 is parallel to the original surface 60a and is a flat surface. is always maintained.

Then, as shown by the solid line in FIG. 4(D), the via 5 is opened from the new etched surface 60b.
This dry etching step 39 is completed when the metal film 56 provided at the tip of the metal film 5 is exposed. During this dry etching, the via 55 is protected by the metal film 56 to prevent erosion.

Here, since the insulating layer 60 is uniformly applied on the base material 51, the initial surface 60a is parallel to the upper surface 51a of the base material 51. Therefore, the new surface 60b of the insulating layer 60 etched by the dry etching step 39 as described above becomes a flat surface parallel to the upper surface 51a of the base material 51, and a part of the via 55 is exposed. ing.

Then, the substrate in the state shown in FIG. 4(D) is subjected to heat treatment at 200° C. for 1 hour in a vacuum of about 10 −1 Pa. Through this heat treatment, moisture adsorbed by the insulating layer 60 is removed, and organic matter adhering to the insulating layer 60 is decomposed and fixed, thereby reducing partial loss of the metal film 62 that will be formed later on the insulating layer 60. However, the adhesion between the insulating layer 60 and the metal film 62 is improved.

As described above, the base material 5 is formed by the polyimide coating/thermal curing process 38 and the dry etching process 39.
The insulating layer 6 has a flat surface parallel to the top surface 51a of the first insulating layer 6, and has a surface 60b that exposes a part of the via 55.
Formation of 0 takes place.

Next, a third sputtering step 40 is performed. As shown in FIG. 5(A), a metal film 62 serving as a base for forming the upper layer conductor wiring is formed in a planar shape on the surface 60b and the via 55 by sputtering. Similar to the metal film 53, this metal film 62 also has a thickness of about 0.2μ.
Chromium (Cr) 62b sputtered with a thickness of m
and copper (Cu) 62a sputtered above it to a thickness of approximately 1 μm, forming a two-layer structure.
r) 62b functions to prevent the copper (Cu) 62a from peeling off from the insulating layer 60.

Next, a resist coating/mask mounting step 41 is performed to form a resist pattern on this metal film 62.
I do. This is achieved by resist 63 as shown in FIG. 5(B).
is applied onto the metal film 62 to a film thickness of about 10 μm, and a mask 64 having an upper layer conductor wiring pattern 64a is placed on the top surface. After that, by exposing and developing the resist 63, the resist exposure and development process step 4
Do step 2. Through this exposure and development process, a pattern 65a of upper layer conductor wiring is formed on the resist 63 as shown in FIG. 5(C).

As described above, the second resist pattern forming step is constituted by the resist coating/mask mounting step 41 and the resist exposure and development step 42, and the resist pattern 65 having the pattern 65a of the upper layer conductor wiring is formed on the metal film 62. formed on top.

Next, a second electrolytic copper (Cu) plating step 43
I do. This is done using the resist pattern 65 as a mask and the metal film 62 as an electrode, and as shown in FIG. 5(D), copper (Cu) plating grows on the metal film 62 in the pattern 65a, and 66 is formed.

Next, the second resist pattern stripping step 44
I do. In this step, the resist pattern 65 is chemically stripped and removed from the metal film 62 by passing the substrate through a stripping solution as in the first resist pattern stripping step 36. FIG. 6A shows a state in which the resist pattern 65 has been removed.

Next, a second ion milling etching step 45 is performed. This is because, in the state shown in FIG. 6A, for example, the upper layer conductor wiring 66 and the other upper layer conductor wiring 66A are electrically connected by the metal film 62, so unnecessary portions of the metal film 62 are removed. It is an object. By placing the substrate again in the apparatus used in the first ion milling etching process 37 and performing ion milling etching, the upper layer conductor wirings 66, 66 are formed as shown in FIG. 6(B).
The metal film 62 in parts other than A is removed.

A series of steps from the third sputtering step 40 to the second ion milling etching step 45 are as follows:
The upper layer conductor wiring 66 is connected to the via 55 and the insulating layer 60 is formed.
This constitutes an upper layer conductor wiring formation step formed above.

In this way, from the first lower layer conductor wiring forming step 31 to the second ion milling etching step 45,
Through the series of steps up to this point, as shown in FIG. 6(B), the upper layer conductor wiring 66 is formed on the lower layer conductor wiring 52a, 52b on the base material 51 of the substrate with the insulating layer 60 in between, and the lower layer conductor wiring A two-layer thin film multilayer substrate is formed in which the upper layer conductor wiring 52a and the upper layer conductor wiring 66 are electrically connected by the via 55. Then, by repeating this series of steps again, a three-layer thin film multilayer substrate 70 as shown in FIG. 7 can be formed, for example, and by repeating this many times, a multilayer thin film multilayer substrate can be formed. be done.

As described above, according to the method for manufacturing a thin film multilayer board of this embodiment, the vias 55 and the upper layer conductor wiring 66 are formed in separate steps, so that the shape, structure, etc. of the via 55 are different from that of the upper layer conductor wiring 66. can be selected regardless of the formation of. That is, the via 55 can be formed into a columnar shape that is strong in terms of strength as in this embodiment, and thereby the possibility of the via 55 breaking is significantly reduced compared to the conventional case.

[0051] Furthermore, as mentioned above, polyimide coating/
Because the surface 60b of the insulating layer 60 becomes a flat surface parallel to the upper surface 51a of the base material 51 through the thermosetting step 38 and the dry etching step 39, problems caused by the uneven shape and step difference of the upper layer conductor wiring in the past are solved. is solved and has the following effects.

■As shown in FIG. 5(B), the surface 63a of the resist 63 formed along the surface 60b of the insulating layer 60
Since the surface is flat, no gap is formed between the mask 64 and the flat mask 64, and the accuracy of pattern transfer by exposure and development is improved compared to the conventional method. As a result, the upper layer conductor wiring can be formed with high precision.

■As shown in FIG. 7, the upper layer conductor wirings 66 and 67 of the second layer and the upper layer conductor wirings 68 and 69 of the third layer are as follows.
Since they are formed parallel to the upper surface 51a of the base material 51 and on the flat surfaces 60b and 71a, the distance between each conductor wiring in the interlayer becomes uniform. As a result, the non-uniform spacing dimensions do not affect the impedance characteristics of the thin film multilayer substrate as in the past, and the electrical characteristics of the thin film multilayer substrate become better than in the past.

■As shown in the upper layer conductor wirings 66 to 69 shown in FIG. 7, even if the upper layer conductor wirings are formed in multiple layers, they are always formed in a flat plate shape, so there is a possibility of disconnection of the upper layer conductor wirings due to stress concentration. descend.

As described above, the method of manufacturing the thin film multilayer board of this embodiment is expected to improve the reliability of the interlayer connections by the vias 55 and improve the performance and reliability due to the improved accuracy of the upper layer conductor wirings 66 to 69. This makes it possible to further advance miniaturization and multilayering of thin film multilayer substrates. Furthermore, although the manufacturing method of this embodiment is complicated with a large number of steps, the upper layer conductor wiring forming steps from the third sputtering step 40 to the second ion milling etching step 45 are as follows:
The via formation process from the first sputtering process 32 to the first ion milling etching process 37 is simply repeated again. Therefore, the method for manufacturing the thin film multilayer substrate of this embodiment is virtually the same as the conventional manufacturing method in terms of work steps and manufacturing equipment.

Note that the present invention is not limited to the above embodiments, and the metal films 53, 56, and 62 may be formed by electroless plating, vapor deposition, or the like instead of sputtering. In addition, the metal structure includes metal films 53 and 6.
Regarding 2, as long as the surface is copper (Cu), a metal structure other than this embodiment may be used, and regarding the metal film 56, an inert metal such as gold (Au) may be used. Also,
The material of the insulating layer 60 is not limited to the thermosetting polyimide of this embodiment, but may also be epoxy, fluorine-based synthetic resin, or the like.

[0057]

[Effect of the invention] As described above, according to the invention of claim 1,
By forming the vias and the upper layer conductor wiring in separate processes, the vias can be formed in an optimal shape and configuration regardless of the formation of the upper layer conductor wiring, eliminating weak parts as in the conventional method. Can be done. As a result, the possibility of wire breakage in the vias can be significantly reduced compared to the prior art.

Furthermore, according to the invention of claim 2, the surface of the insulating layer is parallel to the substrate base material and is a flat surface, so that the conventional problems caused by uneven shapes and steps of the upper layer conductor wiring are solved. As a result, effects such as (1) improvement in the accuracy of the upper layer conductor wiring, (2) improvement in the electrical characteristics of the thin film multilayer substrate, and (2) a reduction in the possibility of disconnection of the upper layer conductor wiring can be expected.

[0059] As a result of the above effects, it is expected that the reliability of interlayer connections by the vias will be improved and the performance and reliability of the upper layer conductor wiring will be improved, making it possible to further advance the miniaturization and multilayering of thin film multilayer substrates. .

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing the principle configuration of the present invention.

FIG. 2 is a flowchart of an embodiment of a method for manufacturing a thin film multilayer substrate according to the present invention.

3 is a diagram showing states in each step from the lower layer conductor wiring forming step to the second sputtering step in FIG. 2. FIG.

4 is a diagram showing the state in each step from the first resist pattern peeling step to the dry etching step in FIG. 2. FIG.

5 is a diagram showing states in each step from a third sputtering step to a second electrolytic copper (Cu) plating step in FIG. 2. FIG.

6 is a diagram showing a state in a second resist pattern peeling step and a second ion milling etching step in FIG. 2. FIG.

FIG. 7 is a diagram of an example of a thin film multilayer substrate in which a plurality of layers of conductor wiring are formed by the thin film multilayer substrate manufacturing method of the present embodiment.

FIG. 8 is a diagram showing each step of an example of a conventional thin film multilayer substrate manufacturing method.

FIG. 9 is a diagram showing each step of an example of a conventional method for manufacturing a thin film multilayer substrate.

FIG. 10 is a diagram showing each step of an example of a conventional method for manufacturing a thin film multilayer substrate.

[Explanation of symbols]

21-25, 31-45 Process 51 Base material 52a, 52b Lower layer conductor wiring 53, 56, 62 Metal film 54, 65 resist pattern 55 Buyer 58 Reactive ions 60 Insulating layer 60a, 60b surface 64 Mask 66-69 Upper layer conductor wiring 70 Thin film multilayer substrate

Claims (3)

[Claims] [Claim 1] Upper layer conductor wiring (66) and lower layer conductor wiring (52a) disposed above and below with an insulating layer (60) in between.
In the method for manufacturing a thin film multilayer board in which layers are connected by vias (55), first, only the vias (55) are placed on the lower conductor wiring (52a) formed on the substrate base material (51). A thin film multilayer characterized in that a via forming step (22) is performed to form a via, followed by an upper layer conductor wiring forming step (25) in which the upper layer conductor wiring (66) is formed on the insulating layer (60). Substrate manufacturing method. [Claim 2] Upper layer conductor wiring (66) and lower layer conductor wiring (52a) disposed above and below with an insulating layer (60) in between.
In the method of manufacturing a thin film multilayer board in which layers are connected by vias (55), a lower conductor wiring forming step (52a) is formed on the substrate base material (51).
21) and a via forming step (2) of forming the via (55) on the lower layer conductor wiring (52a) before forming the insulating layer (60) on the lower layer conductor wiring (52a).
2), and the insulating layer (60) is connected to the lower conductor wiring (5).
2a) and forming an insulating layer on the substrate base material (51) with a thickness that can form a flat first surface (60a) without being affected by the shape of the via (55). step (23), uniformly etching the insulating layer (60) from the first surface (60a) until the tip of the via (55) is exposed; an insulating layer etching step (24) forming a second surface (60b) of said insulating layer which is planar at a height of said second surface (60b) and bringing said second surface (60b) into contact with said via (55); A method for manufacturing a thin film multilayer substrate, comprising an upper layer conductor wiring forming step (25) of forming the upper layer conductor wiring (66). 3. In the via forming step (22), a resist pattern (54) having a pattern (54a) corresponding to the via (55) is formed on the lower layer conductor wiring (52).
a) A resist pattern forming step (33) formed on the top, and a plating step (3) in which the via (55) is formed by plating using the resist pattern (54) as a mask.
3. The method of manufacturing a thin film multilayer substrate according to claim 1, comprising: step 4) and a resist pattern stripping step (36) for removing the resist pattern (54).