JPH04282891A - Manufacture of hybrid integrated circuit device - Google Patents
Manufacture of hybrid integrated circuit deviceInfo
- Publication number
- JPH04282891A JPH04282891A JP4522091A JP4522091A JPH04282891A JP H04282891 A JPH04282891 A JP H04282891A JP 4522091 A JP4522091 A JP 4522091A JP 4522091 A JP4522091 A JP 4522091A JP H04282891 A JPH04282891 A JP H04282891A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- flux
- circuit board
- printed circuit
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910000679 solder Inorganic materials 0.000 claims abstract description 86
- 230000004907 flux Effects 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000004140 cleaning Methods 0.000 claims description 10
- 239000011810 insulating material Substances 0.000 claims description 3
- 239000006071 cream Substances 0.000 abstract description 24
- 238000007650 screen-printing Methods 0.000 abstract description 3
- 239000002904 solvent Substances 0.000 abstract 1
- 238000005476 soldering Methods 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 5
- 239000003960 organic solvent Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 208000032368 Device malfunction Diseases 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3489—Composition of fluxes; Methods of application thereof; Other methods of activating the contact surfaces
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明はハンダ付けによってプリ
ント基板上に電気的な接続を行うチップ部品や半導体素
子を実装してなる混成集積回路装置の製造方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a hybrid integrated circuit device in which chip parts and semiconductor elements for electrical connection are mounted on a printed circuit board by soldering.
【０００２】0002
【従来の技術】従来、チップ抵抗や放熱効果のあるヒー
トシンクを設けた半導体素子等をプリントの配線上に接
続する場合には、まず、第１工程としてはプリント基板
上の各素子が搭載される所定位置にフラックスが含有さ
れた練り状のクリームハンダを印刷をする。次に、第２
工程ではそのクリームハンダにて印刷された所定位置に
各素子を載置する。次いで、第３工程では前記第２工程
にて素子を載置したプリント基板を赤外線ヒータ等によ
って加熱し、前記クリームハンダをリフローさせる。ク
リームハンダがリフローされたことによってフラックス
が煮沸し、クリームハンダの表面に出る。従って、クリ
ームハンダはフラックスとハンダとに分離することとな
る。[Prior Art] Conventionally, when connecting a chip resistor or a semiconductor element equipped with a heat sink with heat dissipation effect to printed wiring, the first step is to mount each element on a printed circuit board. A paste-like cream solder containing flux is printed in a predetermined position. Next, the second
In the process, each element is placed at a predetermined position printed with the cream solder. Next, in a third step, the printed circuit board on which the element was mounted in the second step is heated by an infrared heater or the like to reflow the cream solder. As the cream solder is reflowed, the flux boils and appears on the surface of the cream solder. Therefore, cream solder is separated into flux and solder.
【０００３】そして、前記所定位置に載置された各素子
は、同素子の自重によって溶融しているハンダ内に沈み
込み、同ハンダを冷却することによって前記プリント基
板上の所定位置に素子が載置固定される。次の第４工程
では、前記第３工程にてクリームハンダをリフローした
際に表面に出たフラックスを有機溶剤等にて洗浄する。Each element mounted at the predetermined position sinks into the melted solder due to its own weight, and by cooling the solder, the element is mounted at the predetermined position on the printed circuit board. Fixed in position. In the next fourth step, the flux that appeared on the surface when the cream solder was reflowed in the third step is cleaned with an organic solvent or the like.
【０００４】以上詳述したように、上記の各工程を終え
て混成集積回路装置が製造される。As detailed above, a hybrid integrated circuit device is manufactured after completing each of the above steps.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記の
製造方法によって形成された混成集積回路装置において
は、プリント基板に素子を接続するために両間にクリー
ムハンダを介在したが、第３工程のリフロー時に、クリ
ームハンダ内に含有されたフラックスが煮沸する際、ハ
ンダ内に多量のボイド（気泡）が発生する。[Problems to be Solved by the Invention] However, in the hybrid integrated circuit device formed by the above manufacturing method, cream solder is interposed between the two to connect the elements to the printed circuit board. Sometimes, when the flux contained in cream solder is boiled, a large amount of voids (bubbles) are generated within the solder.
【０００６】ハンダ内にボイドが存在すると、プリント
基板と素子のシェア強度、即ち接続強度が低下するため
プリント基板から素子が剥離しやすくなる。又、プリン
ト基板と素子の接続部の断面積、即ちハンダの断面積は
ボイドが存在することによって小さくなり、混成集積回
路装置を作動させた際に素子から発生する熱の放熱性を
悪化させる。さらに、素子が剥き出し状態でクリームハ
ンダがリフローされるため、フラックスが外部に飛び散
り、そのフラックスが素子に付着する。そして、第４工
程で洗浄するが、十分に素子からフラックスが除去され
ない。従って、素子が汚染され、回路装置の誤動作等を
招くことがあり、同混成集積回路装置の信頼性が損なわ
れるという問題があった。[0006] If voids exist in the solder, the shear strength, ie, the connection strength, between the printed circuit board and the element decreases, making it easier for the element to separate from the printed circuit board. Further, the cross-sectional area of the connection between the printed circuit board and the element, that is, the cross-sectional area of the solder, is reduced by the presence of voids, which deteriorates the heat dissipation of heat generated from the element when the hybrid integrated circuit device is operated. Furthermore, since the cream solder is reflowed with the element exposed, the flux scatters to the outside and adheres to the element. Although cleaning is performed in the fourth step, the flux is not sufficiently removed from the element. Therefore, there is a problem in that the elements are contaminated and the circuit device malfunctions, and the reliability of the hybrid integrated circuit device is impaired.
【０００７】本発明は上記問題点を解消するためになさ
れたものであって、その目的はハンダ層内に溜まる気泡
を減少させ、プリント基板と素子との接続強度の向上及
び素子の放熱性の向上を図ることができ、さらに、プリ
ント基板を洗浄した際にフラックスを除去でき、素子を
汚染しないで混成集積回路装置の信頼性の向上を図るこ
とができる混成集積回路装置の製造方法を提供すること
にある。The present invention has been made to solve the above problems, and its purpose is to reduce air bubbles accumulated in the solder layer, improve the connection strength between the printed circuit board and the element, and improve the heat dissipation of the element. To provide a method for manufacturing a hybrid integrated circuit device, which can improve reliability of the hybrid integrated circuit device by removing flux when cleaning a printed circuit board and not contaminating elements. There is a particular thing.
【０００８】[0008]
【課題を解決するための手段】本発明は上記問題を達成
するために、絶縁材よりなるプリント基板上に形成され
た配線パターンの所定の位置にハンダによって素子を接
続した混成集積回路装置の製造方法において、前記プリ
ント基板における所定の配線パターン位置にフラックス
の存在下で配線パターン上にハンダ層を形成するハンダ
層形成工程と、その後プリント基板を洗浄して前記ハン
ダ層のフラックスを除去する洗浄工程と、前記ハンダ層
の表面に素子を配置させる素子実装工程と、その状態で
ハンダをリフローするリフロー工程とにより、ハンダと
素子とを接続する混成集積回路装置の製造方法をその要
旨とする。[Means for Solving the Problems] In order to achieve the above-mentioned problems, the present invention manufactures a hybrid integrated circuit device in which elements are connected by solder to predetermined positions of a wiring pattern formed on a printed circuit board made of an insulating material. In the method, a solder layer forming step of forming a solder layer on the wiring pattern in the presence of flux at a predetermined wiring pattern position on the printed circuit board, and a cleaning step of cleaning the printed circuit board to remove the flux from the solder layer. The gist of the present invention is to provide a method for manufacturing a hybrid integrated circuit device in which solder and an element are connected by an element mounting process in which the element is placed on the surface of the solder layer, and a reflow process in which the solder is reflowed in this state.
【０００９】[0009]
【作用】まず、ハンダ層形成工程にて、配線パターンの
所定の位置にフラックス及びハンダからなるハンダ層を
形成する。次の洗浄工程にてプリント基板の洗浄を行っ
い、前記ハンダ層の表面に付着したフラックスを除去す
る。続いて、素子実装工程にて治具によってハンダ上に
素子を支持載置する。そして、リフロー工程にて前記ハ
ンダがリフローされ、そのリフローされたハンダへ素子
が接続される。[Operation] First, in the solder layer forming step, a solder layer made of flux and solder is formed at a predetermined position of the wiring pattern. In the next cleaning step, the printed circuit board is cleaned to remove the flux attached to the surface of the solder layer. Subsequently, in the element mounting process, the element is supported and mounted on the solder using a jig. Then, in a reflow process, the solder is reflowed, and the element is connected to the reflowed solder.
【００１０】以上、上記の各工程を行うことによって、
混成集積回路装置が製造される。[0010] By performing the above steps,
A hybrid integrated circuit device is manufactured.
【００１１】[0011]
【実施例】以下、本発明を具体化した一実施例を図１〜
７に基づいて説明する。まず、図１に示すように、絶縁
材よりなるプリント基板１上に形成された配線パターン
２の所定位置へスクリーン印刷によってハンダの粒を含
有したフラックス、即ちクリームハンダ３を塗布する。
そして、次に前記クリームハンダ３をリフローしてフラ
ックス３ａを煮沸させ、図２に示すように、同フラック
ス３ａをハンダ３ｂの表面に吐出させる。このとき、ク
リームハンダ３には素子が載置されていないためフラッ
クス３ａはハンダ３ｂの表面に吐出しやすくなり、同ハ
ンダ３ｂ内にボイドがほとんど溜まらず外部に吐出され
る（ハンダ層形成工程）。[Example] Hereinafter, an example embodying the present invention is shown in Figs.
The explanation will be based on 7. First, as shown in FIG. 1, flux containing solder grains, that is, cream solder 3, is applied by screen printing to a predetermined position of a wiring pattern 2 formed on a printed circuit board 1 made of an insulating material. Then, the cream solder 3 is reflowed to boil the flux 3a, and as shown in FIG. 2, the flux 3a is discharged onto the surface of the solder 3b. At this time, since no element is placed on the cream solder 3, the flux 3a is easily discharged onto the surface of the solder 3b, and almost no voids are accumulated in the solder 3b, and the flux 3a is discharged to the outside (solder layer forming process). .
【００１２】そして、次に図３に示すように、前記ハン
ダ付け工程においてハンダ３ｂの表面に吐出したフラッ
クス３ａを有機溶剤等によって洗浄し、ハンダ３ｂの表
面からフラックス３ａを除去する（洗浄工程）。続いて
、配線パターン２上に素子を載置する素子実装工程に移
る。このとき、前記ハンダ付け工程においてクリームハ
ンダ３をリフローさせたことから、ハンダ３ｂは半球面
状に固化し、同ハンダ３ｂ上には素子を容易に載置させ
ることができなくなっている。Next, as shown in FIG. 3, the flux 3a discharged onto the surface of the solder 3b in the soldering process is cleaned with an organic solvent or the like to remove the flux 3a from the surface of the solder 3b (cleaning process). . Next, the process moves to an element mounting step in which an element is placed on the wiring pattern 2. At this time, since the cream solder 3 was reflowed in the soldering process, the solder 3b solidified into a hemispherical shape, making it impossible to easily place an element on the solder 3b.
【００１３】そこで、図４，５に示すような治具４を使
用して素子５を配線パターン２上に載置させる。前記治
具４は熱膨張率が低く、かつ軽量なカーボンからなり、
各素子５に対応する四角枡目状に区画されて形成されて
いる。そして、同図に示すように、前記治具４をプリン
ト基板１上の所定位置に配置する。次に各素子５をその
素子５に対応する治具４の枡目の中にセットし、素子５
を治具４の内壁で囲む。素子５は治具４の内壁によって
支持されるため、同素子５を半球面状に固化したハンダ
３ｂ上の所定位置に容易に載置することができる。Therefore, the element 5 is placed on the wiring pattern 2 using a jig 4 as shown in FIGS. 4 and 5. The jig 4 is made of carbon that has a low coefficient of thermal expansion and is lightweight,
It is divided and formed into a square grid shape corresponding to each element 5. Then, as shown in the figure, the jig 4 is placed at a predetermined position on the printed circuit board 1. Next, each element 5 is set in the grid of the jig 4 corresponding to the element 5, and
is surrounded by the inner wall of jig 4. Since the element 5 is supported by the inner wall of the jig 4, the element 5 can be easily placed at a predetermined position on the hemispherically solidified solder 3b.
【００１４】続いて、ハンダ３ｂ上に載置された素子５
を実装したプリント基板１を水素還元雰囲気中でリフロ
ーする（リフロー工程）。この水素還元雰囲気中でリフ
ローされることによって図６に示すように、クリームハ
ンダ３内にフラックス３ａが含有されていなくてもハン
ダ３ｂへ素子５が自重により沈み込み、前記配線パター
ン２と素子５が確実に接続される。Next, the element 5 placed on the solder 3b
The printed circuit board 1 mounted with is reflowed in a hydrogen reducing atmosphere (reflow process). By being reflowed in this hydrogen reducing atmosphere, as shown in FIG. 6, even if the cream solder 3 does not contain flux 3a, the element 5 sinks into the solder 3b due to its own weight, and the wiring pattern 2 and the element 5 sink into the solder 3b. are connected securely.
【００１５】そして、図７に示すように、リフロー工程
を完了した後、プリント基板１上から治具４を取り除い
て混成集積回路装置Ｃが製造される。なお、混成集積回
路装置Ｃにヒートシンク６を設けた素子５が使用されて
いる場合には、同素子５は前記配線パターン２に対して
絶縁状態にあるため、前記リフロー工程を完了した後、
治具４を取り除いて前記素子５と配線パターン２との配
線を行うワイヤボンディングを施す工程が加えられる（
図示せず）。As shown in FIG. 7, after the reflow process is completed, the jig 4 is removed from the printed circuit board 1, and the hybrid integrated circuit device C is manufactured. Note that when the hybrid integrated circuit device C uses an element 5 provided with a heat sink 6, since the element 5 is insulated from the wiring pattern 2, after the reflow process is completed,
A step of removing the jig 4 and performing wire bonding for wiring the element 5 and the wiring pattern 2 is added (
(not shown).
【００１６】以上詳述したように、本実施例の混成集積
回路装置の製造方法によって得られた混成集積回路装置
Ｃによれば、ハンダ３ｂ内にはほとんどボイドが発生し
ないため、同ハンダ３ｂの断面積が従来のボイドが発生
したハンダの断面積と比較して広くなる。従って、混成
集積回路装置Ｃを作動させた際に素子５から発生する熱
の放熱性の向上が図られるとともにプリント基板１と素
子５とのシェア強度の向上を図ることができる。As described in detail above, according to the hybrid integrated circuit device C obtained by the method of manufacturing a hybrid integrated circuit device of this embodiment, since almost no voids are generated in the solder 3b, The cross-sectional area is wider than that of conventional solder with voids. Therefore, it is possible to improve the heat dissipation of heat generated from the element 5 when the hybrid integrated circuit device C is operated, and to improve the shear strength between the printed circuit board 1 and the element 5.
【００１７】さらに、ハンダ付け工程において素子５を
載置する前にフラックス３ａを除去するため、フラック
ス３ａによる素子５の汚染がなくなり、同混成集積回路
装置Ｃの誤作動等が大幅に減少されて混成集積回路装置
Ｃの信頼性の向上を図ることができる。なお、本発明は
上記実施例に限定されるものではなく、発明の趣旨を逸
脱しない範囲で例えば次のような製造方法で製造しても
よい。Furthermore, since the flux 3a is removed before placing the element 5 in the soldering process, the element 5 is not contaminated by the flux 3a, and malfunctions of the hybrid integrated circuit device C are greatly reduced. The reliability of the hybrid integrated circuit device C can be improved. Note that the present invention is not limited to the above embodiments, and may be manufactured by the following manufacturing method, for example, without departing from the spirit of the invention.
【００１８】（１）まず、プリント基板１の配線パター
ン２の所定位置にフラックス３ａのみを塗布する。そし
て、フラックス３ａが塗布されたプリント基板１をハン
ダ３ｂが溶融されているハンダ槽に浸漬させる。ハンダ
槽に浸漬させたことによって、前記配線パターン２のフ
ラックス３ａが塗布された所定位置にのみハンダ３ｂが
付着される（ハンダ層形成工程）。そして、それ以後の
工程は上記実施例と同じ洗浄工程、素子実装工程、リフ
ロー工程、必要に応じてワイヤボンディング工程を行う
。(1) First, only the flux 3a is applied to a predetermined position of the wiring pattern 2 of the printed circuit board 1. Then, the printed circuit board 1 coated with the flux 3a is immersed in a solder bath in which the solder 3b is melted. By immersing it in the solder bath, the solder 3b is attached only to the predetermined positions of the wiring pattern 2 to which the flux 3a has been applied (solder layer forming step). The subsequent steps are the same as in the above embodiments, including a cleaning step, an element mounting step, a reflow step, and a wire bonding step if necessary.
【００１９】前記実施例でのハンダ層形成工程では、ス
クリーン印刷によってプリント基板１へクリームハンダ
３を塗布したために、クリームハンダ３を塗布するため
のマスクを必要としたが、本別例のハンダ層形成工程で
は、マスクを用いなくてもフラックス３ａをプリント基
板１に塗布させることができ、種々の配線パターン２の
混成集積回路装置にも対応できるので、そのときどきの
マスク交換等の煩わしさがなくなる。又、本別例の製造
方法によって得られた混成集積回路装置は前記実施例の
製造方法で得られた混成集積回路装置Ｃと同様の効果を
得ることができる。In the solder layer forming step in the above embodiment, since the cream solder 3 was applied to the printed circuit board 1 by screen printing, a mask was required for applying the cream solder 3, but the solder layer of this other example In the forming process, the flux 3a can be applied to the printed circuit board 1 without using a mask, and it can be applied to hybrid integrated circuit devices with various wiring patterns 2, so there is no need to worry about changing the mask from time to time. . Further, the hybrid integrated circuit device obtained by the manufacturing method of this alternative example can obtain the same effects as the hybrid integrated circuit device C obtained by the manufacturing method of the above embodiment.
【００２０】（２）前記実施例では、洗浄工程において
フラックス３ａを除去するために有機溶剤を使用したが
、この有機溶剤に代えてフロンガスや超音波等を使用し
てフラックス３ａを除去してもよい。
（３）前記実施例では、治具４は四角枡目状に形成され
ていたが、この治具４の枡目形状をハニカム形状等、種
々の形状に変更して実施してもよい。(2) In the above embodiment, an organic solvent was used to remove the flux 3a in the cleaning process, but the flux 3a may also be removed using fluorocarbon gas, ultrasonic waves, etc. instead of the organic solvent. good. (3) In the above embodiment, the jig 4 was formed in the shape of a square grid, but the grid shape of the jig 4 may be changed to various shapes such as a honeycomb shape.
【００２１】[0021]
【発明の効果】以上詳述したように本発明によれば、ハ
ンダ層内に溜まる気泡を減少させ、プリント基板と素子
との接続強度の向上及び素子の放熱性の向上を図ること
ができ、さらに、プリント基板を洗浄した際にフラック
スを除去できるため、素子を汚染しないで、混成集積回
路装置の信頼性の向上を図ることができるという優れた
効果を奏する。As described in detail above, according to the present invention, it is possible to reduce air bubbles accumulated in the solder layer, improve the connection strength between the printed circuit board and the element, and improve the heat dissipation of the element. Furthermore, since the flux can be removed when the printed circuit board is cleaned, there is an excellent effect that the reliability of the hybrid integrated circuit device can be improved without contaminating the elements.
【図１】本発明の実施例を示す図であって、ハンダ付け
工程におけるクリームハンダを塗布した際のプリント基
板上の状態を示す拡大断面図である。FIG. 1 is a diagram showing an embodiment of the present invention, and is an enlarged sectional view showing the state on a printed circuit board when cream solder is applied in a soldering process.
【図２】同じくハンダ付け工程におけるクリームハンダ
をリフローした際のプリント基板上の状態を示す拡大断
面図である。FIG. 2 is an enlarged sectional view showing the state on the printed circuit board when cream solder is reflowed in the same soldering process.
【図３】洗浄工程におけるプリント基板上の状態を示す
拡大断面図である。FIG. 3 is an enlarged sectional view showing the state on the printed circuit board during the cleaning process.
【図４】素子実装工程におけるプリント基板上の状態を
示す拡大断面図である。FIG. 4 is an enlarged cross-sectional view showing the state on the printed circuit board in the element mounting process.
【図５】治具の形状を示す平面図である。FIG. 5 is a plan view showing the shape of the jig.
【図６】リフロー工程におけるプリント基板上の状態を
示す拡大断面図である。FIG. 6 is an enlarged cross-sectional view showing the state on the printed circuit board during the reflow process.
【図７】各工程を完了して完成された混成集積回路装置
を示す拡大断面図である。FIG. 7 is an enlarged cross-sectional view showing a completed hybrid integrated circuit device after completing each process.
１ プリント基板
２ 配線パターン
３ ハンダとしてのクリームハンダ３ａ フラ
ックス
３ｂ ハンダ
４ 治具
５ 素子
Ｃ 混成集積回路装置1 Printed circuit board 2 Wiring pattern 3 Cream solder 3a as solder Flux 3b Solder 4 Jig 5 Element C Hybrid integrated circuit device
Claims (1)
された配線パターンの所定の位置にハンダによって素子
を接続した混成集積回路装置の製造方法において、前記
プリント基板における所定の配線パターン位置にフラッ
クスの存在下で配線パターン上にハンダ層を形成するハ
ンダ層形成工程と、その後プリント基板を洗浄して前記
ハンダ層のフラックスを除去する洗浄工程と、前記ハン
ダ層の表面に素子を配置させる素子実装工程と、その状
態でハンダをリフローするリフロー工程とにより、ハン
ダと素子とを接続することを特徴とする混成集積回路装
置の製造方法。1. A method for manufacturing a hybrid integrated circuit device in which elements are connected by solder to predetermined positions of a wiring pattern formed on a printed circuit board made of an insulating material, wherein flux is applied to a predetermined position of the wiring pattern on the printed circuit board. a solder layer forming step in which a solder layer is formed on the wiring pattern in the presence of a solder layer; a cleaning step in which the printed circuit board is then cleaned to remove flux from the solder layer; and an element mounting step in which an element is placed on the surface of the solder layer. and a reflow step of reflowing the solder in that state to connect the solder and the element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4522091A JPH04282891A (en) | 1991-03-11 | 1991-03-11 | Manufacture of hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4522091A JPH04282891A (en) | 1991-03-11 | 1991-03-11 | Manufacture of hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04282891A true JPH04282891A (en) | 1992-10-07 |
Family
ID=12713187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4522091A Pending JPH04282891A (en) | 1991-03-11 | 1991-03-11 | Manufacture of hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04282891A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007067145A (en) * | 2005-08-31 | 2007-03-15 | Mitsubishi Materials Corp | METHOD OF BONDING SUBSTRATE TO ELEMENT USING Au-Sn ALLOY SOLDER PASTE |
| JP2007173768A (en) * | 2005-11-24 | 2007-07-05 | Mitsubishi Materials Corp | METHOD OF USING Au-Sn ALLOY SOLDER PASTE TO BOND SUBSTRATE AND ELEMENT |
| JP2008010545A (en) * | 2006-06-28 | 2008-01-17 | Mitsubishi Materials Corp | METHOD FOR JOINING WHOLE OF JUNCTION FACE OF ELEMENT TO SUBSTRATE BY USING Au-Sn ALLOY SOLDER PASTE |
-
1991
- 1991-03-11 JP JP4522091A patent/JPH04282891A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007067145A (en) * | 2005-08-31 | 2007-03-15 | Mitsubishi Materials Corp | METHOD OF BONDING SUBSTRATE TO ELEMENT USING Au-Sn ALLOY SOLDER PASTE |
| JP2007173768A (en) * | 2005-11-24 | 2007-07-05 | Mitsubishi Materials Corp | METHOD OF USING Au-Sn ALLOY SOLDER PASTE TO BOND SUBSTRATE AND ELEMENT |
| JP2008010545A (en) * | 2006-06-28 | 2008-01-17 | Mitsubishi Materials Corp | METHOD FOR JOINING WHOLE OF JUNCTION FACE OF ELEMENT TO SUBSTRATE BY USING Au-Sn ALLOY SOLDER PASTE |
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