JPH04282838A - Manufacture of ldd type mos transistor - Google Patents

Abstract

PURPOSE:To provide a LDD type MOS transistor, in which the series resistance below a gate oxide film can be reduced, and which preserves hot carrier resistance and is excellent in gm characteristic by forming the light dope layer of the MOS transistor. CONSTITUTION:A PSG film 3 being doped with impurities on the level of forming a source and a drain is made at the part excluding the gate electrode formation area on a semiconductor substrate 1, and making use of the shadow effect of this PSG film 3, an Ti film 8 is deposited except on the drain region obliquely by electron beam deposition method, and with this Ti film 8 as a mask, a light dope layer 10 is made.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to LDD (Lightly
-Doped-Drain) structure.

0002

[Prior Art] Conventionally, in order to prevent characteristic fluctuations caused by hot carriers in NMOS transistors, high concentration
A low concentration of N- is placed between the drain and the P- layer below the gate.
A method of providing an offset layer has been proposed. This structure is LDD (Lightly Doped Dr.
ain) structure, and its idea is to alleviate the peak electric field strength of the drain depletion layer that occurs in a pinch-off state. In other words, by lowering the concentration of the drain, the depletion layer is extended to the drain side, thereby reducing the voltage handled by the substrate side and weakening the electric field.

FIG. 2 shows a cross-sectional structure of a typical LDD.

In FIG. 2, 101 is a P-type substrate, 102
is a LOCOS oxide film, 103 is a gate oxide film, 104 is a gate polysilicon electrode, 105 is an N- offset layer, 106 is a gate sidewall oxide film, 1
07 is a protective oxide film during source/drain ion implantation,
108 is a source/drain layer, 109 is an interlayer insulation film, 1
10 and 111 are source/drain contact holes;
112 and 113 are source/drain electrodes.

The structure of this LDD type MOS transistor is that the gate has a stacked structure of oxide film/polysilicon/WSi.

Next, a method for manufacturing the above-mentioned LDD type MOS transistor will be explained with reference to FIGS. 3(a) to 3(c).

First, a field oxide film 201 with a thickness of 7000 Å is formed on a P-type substrate 200 by the LOCOS method, and then a field oxide film 201 with a thickness of 20
A gate oxide film 202 of 0 Å is grown, a first polysilicon 203 and a polycide gate WSix 204 are grown, and a gate electrode is selectively left by a well-known photolithographic etching technique. Then n- layer (light doped layer) 2
As (arsenic) ions are implanted to form 05. (See Figure 3(a))

Next, a SiO2 film 206 is grown on the entire surface by CVD. (See Figure 3(b))

[0009]
CVD-SiO2 film 206 is selectively formed by RIE method.
is etched to form sidewalls 207. Then, using the gate electrode with the sidewall 207 formed by ion implantation as a mask, P (phosphorus) is implanted into n+
A source/drain layer 208 is formed. (Figure 2(c)
reference)

0010

[Problems to be Solved by the Invention] However, in the structure and manufacturing method of the above-mentioned LDD type MOS transistor,
Since the n- lightly doped layer was formed on both the source side and the drain side, as shown in FIG. 4, the resistance Rn- of one lightly doped layer was required to be doubled, which hindered improvement in gm.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a method for manufacturing an LDD type MOS transistor with excellent gm.

0012

[Means for solving the problems] LDD type MOS of the present invention
The method for manufacturing a transistor consists of two steps: forming an impurity oxide film doped with the same impurity concentration as that used to form the source/drain in areas other than the gate electrode formation area on the semiconductor substrate; and forming a gate oxide film in the gate electrode formation area. In the process of forming a film, a high melting point metal is obliquely deposited using an electron beam evaporation method. The present invention includes the steps of forming an ion implantation shielding film outside the drain region due to the shadow effect of the impurity oxide film, and forming a lightly doped layer on the drain region side using the ion implantation shielding film as a mask.

[0013]

[Operation] The method for manufacturing an LDD type MOS transistor of the present invention is to form an impurity oxide film doped with an impurity at the same concentration as the impurity concentration for forming a source/drain on a semiconductor substrate in a region other than the gate electrode formation region. do. Next, a gate oxide film is formed in the gate electrode formation area, and then,
When a high melting point metal is obliquely deposited by electron beam evaporation, the high melting point metal is deposited in areas other than the drain region due to the shadow effect of the impurity oxide film. Thereafter, by performing ion implantation using the ion implantation shielding film as a mask, a lightly doped layer is formed only on the drain side.

[0014]

[Embodiment] An embodiment of the present invention will be explained using FIGS. 1(a) to 1(g).

The method for manufacturing an LDD structure of the present invention consists of the following steps.

First, a field SiO2 film 2 of about 7000 Å is formed on a P-type semiconductor substrate 1 using the LOCOS method, and then a PSG film 3 doped with impurities at the same concentration as that for forming the source/drain is formed by CVD. The film is grown to a thickness of about 4,000 Å using a method, and then a region 4 where a gate electrode is to be formed is opened using a photolithography technique. (See Figure 1(a))

Next, a gate oxide film 5 is grown in the region 4 where the gate electrode is to be formed by heat treatment at 200 Å×850° C. in a wet atmosphere. At the same time, thermal diffusion is performed to form source/drain regions 6 using the PSG film 3 containing impurities. (See Figure 1(b))

Next, the degree of vacuum is set to 1×10-7 (Torr).
, the substrate temperature was 100-150°C, and the growth rate was 5 Å/se.
Adjust to c. Then, a Ti (titanium) film 8 of about 1500 Å is formed on the semiconductor substrate 1 by electron beam evaporation from an oblique evaporation direction 7 .

Then, as shown in FIG. 1C, due to the shadow effect of the PSG film 3 containing impurities, the Ti film 8 is formed only in the area other than the region 9 where the drain is to be formed. Thereafter, using this Ti film 8 as a mask, a lightly doped layer 10 is formed in the region 9 where a drain is to be formed. (See Figure 1(c))

Next, T using 0.1-0.5% HF.
The i film 8 is etched for about 10 seconds to completely remove the Ti film 8.

[0021] After that, polysilicon 1 was deposited using the LPCVD method.
1 is grown to a thickness of 400 Å over the entire surface. (See Figure 1(d))

0
[022] Next, a resist is applied, and polysilicon 1 on the PSG film 3 is removed by RIE using CHF3 gas.
Etch back until 1 is removed.

As a result, an oxide film region 12 and a polysilicon region 13 are formed. (See Figure 1(e))

0024
] Next, by the CVD method, the growth concentration was 320°C and the pressure was 0.
A W (tungsten) film 14 is selectively buried only on the polysilicon region 13 under the conditions of 1 Torr and gas ratio SiH4 /WF6 =1.5.

Thereafter, contacts for taking out electrodes are obtained on the PSG film 3 for the source region 16 and drain region 15 by photolithography.

[0026] Ti, W, P used for explanation in the above embodiments
SG is not limited to this.

[0027]

Effects of the Invention As is clear from the above description, the method for manufacturing an LDD type MOS transistor of the present invention utilizes the shadow effect of the impurity oxide film to form a lightly doped layer of the MOS transistor only on the drain side. Therefore, it is possible to reduce the series resistance under the gate oxide film, maintain hot carrier resistance, and realize an LDD type MOS transistor with excellent gm characteristics.

[Brief explanation of the drawing]

FIG. 1 is a process diagram of a method for manufacturing an LDD type MOS transistor of the present invention.

FIG. 2 is a cross-sectional view of a conventional LDD type MOS transistor.

FIG. 3 is a process diagram of a conventional method for manufacturing an LDD type MOS transistor.

FIG. 4 is a circuit diagram of an LDD type MOS transistor.

[Explanation of symbols]

1 P-type semiconductor substrate 2 Field SiO2 film 3 PSG film 4 Planned area for gate electrode formation 5 Gate oxide film 6 Source/drain region 7 Vapor deposition direction 8 Ti film 9 Drain formation area 10 Light doped layer 11 Polysilicon 12 Oxide film region 13 Polysilicon area 14 W film 15 Drain region 16 Source area

Claims (1)

[Claims] 1. A step of forming an impurity oxide film doped with an impurity concentration sufficient to form a source/drain in a region other than a gate electrode formation region on a semiconductor substrate, and a step of forming an impurity oxide film doped with an impurity concentration sufficient to form a source/drain. The method includes the steps of: forming an ion implantation shielding film by obliquely depositing a high melting point metal on a region other than the drain region using a beam evaporation method; and forming a lightly doped layer on the drain region side using the ion implantation shielding film as a mask. LDD type M characterized by
A method for manufacturing an OS transistor.