JPH04281644A - Traffic observation circuit - Google Patents

Abstract

PURPOSE:To attain accurate observation and detection of minimum cell arrival interval rule violation even when a timer counter is circulated once when a cell passing on a line of a communication network passes at a prescribed interval or over in which the information to be communicated is transferred while being divided in the unit of cells being fixed length packets. CONSTITUTION:The circuit is provided with a timer 22 counted up for each one-cell hold time, a means 21 storing a cell arrival time for each logic channel as a stored time stamp, a means 23 discriminating whether or not the cell arrival interval satisfies a specified value based on the time stamp and the timer value, and a means using the discrimination means 23 so as to discriminate whether or not the current time is deviated from the time stamp time by a specified value or over for a specific period of each logic channel independently of the presence of cell arrival with respect to each logic channel and displaying the result.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a traffic observation circuit that observes and controls the traffic of cells passing through the lines of a communication network that divides and transfers information to be communicated into fixed-length packets of cells. It is related to.

0002

[Background Art] Asynchronous transfer mode (Asynchronous transfer mode)
In a communication network using ATM (Aus Transfer Mode), media with different communication bit rates can be handled in a unified manner by dividing information to be communicated into fixed-length cells and transmitting them.

[0003] In this ATM network, traffic during communication is generally variable.

That is, subscribers can perform flexible communications by changing communication traffic according to increases and decreases in the amount of information generated.

On the other hand, from the standpoint of effective use of network resources, it is necessary to understand temporal changes in traffic.

[0006] For this reason, in an ATM network, communication traffic is declared at the time of call setup, and communication is performed according to the declared value.

[0007] Regarding these declared values, the network side observes the input traffic from the subscriber line, determines whether the values are as declared, and regulates the violating traffic.

[0008] For example, when a violation is detected, the subscriber accommodating exchange immediately discards cells sent by the subscriber in excess of the declared number, or a violation tag is added to the cell, and the violation tag is added at the transit exchange during network congestion. Violating traffic is controlled by methods such as selectively discarding cells.

[0009] As a declaration parameter, there are two methods: one is to declare the maximum value of the number of cells arriving in each specified cycle to define the average traffic, and the other is to observe the cell arrival interval and define the maximum traffic from the minimum value. (Figure 2).

[0010] Among these, the maximum traffic is also called the peak traffic value, and has a great influence on the cell transfer quality in the ATM network.

In the present invention, a method for observing this maximum traffic will be described.

[0012] When observing the cell arrival interval, the following two methods can be considered.

(2) A counter counts up the time from the arrival of one cell until the arrival of the next cell.

(2) Store the time (time stamp value) at which the cell arrived, and subtract the time stamp value from the time at which the next cell arrives.

Method (2) is easy to control.

However, when considering the use of PBX, calls are multiplexed even on subscriber lines, especially on high-speed subscriber lines (
150 Mb/s, 600 Mb/s, etc.), it is possible to multiplex hundreds to thousands of calls.

[0017] In order to observe traffic for each call in a communication network in which a large number of calls are multiplexed, it is necessary to have a large number of counters, which increases the amount of hardware and is not practical.

On the other hand, method (2) consists of one timer, a memory for storing the time of cell arrival for each call, and a subtraction circuit (FIG. 3).

The timestamp value for each call is stored in a memory whose address is the logical channel number VCI corresponding to the call.

[0020] When a cell arrives, the time stamp TST of the previous cell arrival is read from the corresponding address, and the cell arrival interval is calculated by calculation with the current timer value TIM.

[0021] A timer consists of a counter and a clock source that determines a time base for a unit of time.

[0022] Normally, a cyclic counter is used as the counter, and the maximum value of the counter is set larger than the cell arrival interval.

When the counter is a binary n-bit counter, the cell arrival interval D is D=TIM-TSTTIM<T when TIM≧TST.
For ST, D=2n +TIM-TST.

[0024]

SUMMARY OF THE INVENTION Consider using the circuit shown in FIG. 3 to observe input traffic of an ATM network.

[0025] At the time of call setup, the "minimum cell arrival interval Dmin" corresponding to the maximum traffic is specified for each logical channel, and if the cell arrival interval is smaller than Dmin during actual communication, it is treated as a violation of the specified value (violation processing Possible methods include discarding the violating cell and marking the violating cell and forwarding it as a low-priority cell).

[0026] In the ATM network, 64 kb/s to several tens of Mb/s
Calls with a wide range of degrees are multiplexed.

For example, in order to observe the cell arrival interval of a call with 53 bytes per cell and a maximum traffic of 50 Mb/s, it is necessary to set the unit time of the timer to about 8.5 μsec.

[0028] At this time, the cell interval of 65 kb/s is about 7
This is 80 units of time (approximately 6.6 msec).

Furthermore, in ATM communication, cell traffic is not necessarily constant.

If no cells are sent out for 1 second, the cell interval will be about 120,000 units of time. When configuring 120,000 units of time using a binary counter, 17 bits are required.

Moreover, in the case of ATM, although the minimum cell arrival interval can be defined by the maximum traffic speed, the maximum arrival interval is not.

Since the size of the timer is finite no matter how large it is, accurate cell spacing cannot be observed, and violations of the specified value of input traffic in the ATM network cannot be detected.

An example is shown in FIG.

When the timer is configured with a binary 16-bit counter, the timer value cycles through 0 to 65535 in decimal notation.

Here, the minimum cell arrival interval specified value Dmin
is 780 units of time (equivalent to 64 kb/s).

Assume that the time stamp value at the time when one cell arrives is TST=65000.

If the next cell arrives after 700 time units (approximately 70 kb/s), the timer value is TIM=6500.
0+700-65536=164, which is a violation of the specified value.

On the other hand, if the next cell arrives after 66236 unit time, the timer value becomes TIM=65000+66236-65 even though it satisfies the specified value.
536-65536=164, and in calculation, the cell arrival interval D=700, and a violation of the specified value is detected.

[0039] When cells arrive at intervals of a certain value or more, there is a problem in that a counter with a finite number of bits cannot accurately observe and detect a violation of the minimum cell arrival interval regulation.

An object of the present invention is to provide a traffic observation circuit that can solve the conventional problems and perform accurate traffic observation.

[0041]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a communication network in which information is divided into fixed-length cells and transferred by dividing peak traffic into cells for each logical channel in advance in order to observe traffic within the network. In a traffic observation circuit that performs traffic observation by setting an arrival interval as a specified value, a timer that counts up every cell holding time, a holding means that holds a cell arrival time for each logical channel,
determining means for determining whether the cell arrival interval satisfies the specified value from the value held in the holding means for holding the cell arrival time and the value of the timer; Regardless of the presence or absence, the determination means determines whether or not the current time has elapsed by the specified value or more from the time of the value held in the holding means at a certain period specific to each logical channel, and displays the result. and a display means for displaying a cell, and when a cell arrives, the value displayed on the display means corresponding to the logical channel of the cell is referred to, and if the displayed value is the same at the previous determination time, the holding means Only when the specified value has not elapsed since the time of the value held in the cell, the cell arrival interval is determined to be the specified value using the judgment means from the timer value representing the current time and the value held in the holding means. It is characterized by determining whether or not the following is satisfied.

[0042]

[Operation] In FIG. 3, the memory holds a specified value C1 (VCI) for each call and a timestamp value C2 (VCI) at the time of cell arrival, using the logical channel number VCI assigned to each call as an address. do.

[0043] When a call is connected, a specified value C1 (VCI) is written on the memory with the corresponding VCI as an address.

During communication, the time of the previous cell arrival is stored in the memory as a timestamp value C2 (VCI).

When a cell arrives, the VCI of the arriving cell is received at the same time as the cell arrival signal, and the minimum arrival interval specified value C1 (VCI) and the previous time stamp value C2 (VCI) are read out using this VCI as an address.

Timer value TIM and C2(V
D=TIM−C2(VCI) indicates the cell arrival interval.

[0047] D is compared with the specified value C1 (VCI), and D≧
C1 (VCI) satisfies the regulations. Conversely, D<C1
(VCI), it is a violation of the specified value and a violation detection signal is issued.

[0048] In the above traffic observation, the following two
Two treatments are required.

[0049] ■ Arrival interval calculation when a cell arrives during communication

0
050] ■Writing/deletion of default values during call setup/cancellation

Here, the arrival interval calculation (
Comparison of input traffic with a specified value/determination of violation) must be performed every time a cell arrives, so the circuit is controlled in units of one cell holding time.

In the conventional technique shown in FIG. 3, the holding time for one cell is
The call processing phase is divided into an arrival processing phase that performs (1) and a call processing phase that performs (2).

[0053] Through this process, violation of the specified value can be observed, but as described in the prior art section,
When the arrival interval of cells is indefinite as in ATM communication, errors occur in observation.

In order to compensate for the above-mentioned drawbacks, the traffic observation circuit of the present invention adds one bit to the "flag" column F to the table in the memory that holds the specified value and the timestamp value at the time of the previous cell arrival.

An overview of the present invention is shown in FIG.

As described above, the specified value is declared by the subscriber at the time of call setup as a value corresponding to the maximum traffic. That is, the specified value is set to an arbitrary value for each logical channel.

In the present invention, for each logical channel, the difference between the timer value and the timestamp value is calculated at a fixed time period even if no cell arrives, and the difference is determined by the call to which the logical channel is assigned. By turning on the "flag" at the time when the predetermined minimum arrival interval is exceeded, it is possible to compensate for the drawbacks shown in the prior art section.

Therefore, as shown in FIG. 6, in addition to the arrival processing phase and the call processing phase, as processing phases within one cell holding time,

(2) A periodic processing phase is provided to periodically check the arrival interval.

In the present invention, each phase specifically performs the following processing.

■Cell arrival processing phase:

[0062] When the cell arrives, it is determined whether the specified cell value is violated.

The cell arrival interval is obtained by subtracting the timestamp value TST held in the memory 21 for the VCI of the arriving cell from the value TIM of the timer counter 22 at that time.

If this value is smaller than the specified value Dmin held in the memory 21, the traffic is determined to be a violation, and the violation processing unit 24 is notified of this fact.

Note that when the flag F held in the memory 21 is ON, it is assumed that the specified value is unconditionally satisfied.

At the end of this phase, the time stamp value TST of the VCI is rewritten to the value TIM of the timer counter 22.

■Call setup processing phase:

Call setting processing is performed based on the signal from the call control section 25.

VC obtained from the call control unit 25 at the time of call setup
The specified value Dmin is written on the table of the memory 21 using I as the address, and the flag F is set to "ON".

■Cyclic processing phase:

Regardless of whether or not a cell arrives for a certain VCI, it is determined whether the specified value is satisfied.

The timer counter 22 for a certain VCI
The timestamp value TST held in the memory 21 is subtracted from the value TIM, and this value becomes the specified value D of the VCI.
If it exceeds min, the cell arrival interval already satisfies the specified value, and therefore the flag F of the VCI is set to "ON".

Regarding the periodic processing of (2) in each of these phases, the n-bit counter 2 for the timer is used for each VCI.
From the cycle of 2 (TMAX=2n), the corresponding VCI
Processing must be performed at a cycle less than or equal to the minimum arrival interval specified value.

The reason for this is shown in FIG. 9, focusing on a specific VCI.

In FIG. 9, the cell of the VCI is at time t0.
Assume that you arrive at

[0076] Let t1 be the time at which the specified minimum interarrival interval Dmin of cells of the VCI has passed from t0 (t1=t
0+Dmin), and then t2 is the time when the value of the timer counter goes through one cycle and becomes the same value as at time t0 (
t2=t0+Tmax).

[0077] Here, from time t1 to t2, the VC
Assuming that periodic processing is not performed on I, if a cell of the VCI arrives after time t2, the arrival interval calculated from the timestamp value and timer value of the VCI will satisfy the specified value of the VCI. Furthermore, since the "flag" of the VCI does not indicate that it satisfies the specified value, the cell of the VCI is considered to be in violation of the specified value, even though it actually satisfies the specified value. Detected.

Therefore, periodic processing must be performed on the VCI at least once between time t1 and time t2.

Therefore, periodic processing must be performed on the VCI at a constant cycle equal to or less than the value (Cyc) obtained by subtracting the minimum arrival interval specified value of the VCI from the timer counter circulation period.

[0080] Let N be the number of VCIs subject to traffic observation, and let Dmin be the maximum value of the specified minimum arrival interval for each VCI.
- max, if the periodic processing is performed once per cell holding time as shown in Fig. 6, then Cyc- max = T
In order to perform periodic processing for all VCIs during max-Dmin-max, it is necessary that N≦Cyc-max.

Furthermore, when there are many target VCIs, the periodic processing must be performed multiple times within one cell holding time, as shown in FIG.

That is, it is assumed that the periodic processing is performed a number of times in one cell holding time, and the relationship N≦a×Cyc-max should hold.

On the contrary, N, Tmax, Dmin − ma
When x is given, the number of periodic processes may be set so that a≧N/Cyc-max.

Examples will be explained below.

[0085]

Embodiment FIG. 5 shows an embodiment of a traffic observation circuit for observing input traffic for each call on a line in which a plurality of calls are multiplexed.

Multiplexed calls are managed using a logical channel number (VCI) assigned to each call.

In FIG. 5, 10 is a cell arrival/VCI detection section, 11 is a specified value holding section, 12 is an observation circuit control section, and 1
3 is a time stamp holding unit, 14 is a timer counter,
15 is a clock section.

The cell arrival/VCI detection unit 10 detects the arrival of a cell and the VCI of the cell, and detects the cell arrival signal as well as the VCI.
The value of CI is sent to the observation circuit control section 12.

The specified value holding unit 11 holds a minimum cell arrival interval specified value (Dmin) for each VCI, and the time stamp holding unit 13 holds a timestamp value (TS
Each VCI has a flag (T) and a flag (F).

The timer counter 14 uses an n-bit cyclic counter. The timer counter 14 is the clock section 1
It receives the clock C1 from 5 and is counted up.

[0091] The clock section 15 generates a clock in units of cell holding time.

Therefore, the value of the timer counter value 14 indicates the time when the cell holding time is the unit time.

In this embodiment, processing cycles are assigned to the three types of phases (1) to (2) described above with reference to FIG.

In FIG. 7, the cell period is one arrival process ■, 1
It is divided into 4 parts and allocated to 1 call setting process (2) and 2 cycle processes (2).

Correspondingly, the clock unit 15 issues a clock C1 having the same period as the cell holding time and a clock C8 having a period ⅛.

The observation circuit control unit 12 performs cell arrival processing, call setting processing, and periodic processing during one cell hold time, and
Violation of the minimum cell arrival interval specified value is detected for each CI.

FIG. 8 shows the configuration of the control section 12.

In FIG. 8, 121 is a periodic control VCI control counter, 122 is a cell arrival information holding section, 123 is a call processing information holding section, 124 is a processing timing management section, 125
126 is a selector for VCI selection, and 126 is a determination unit.

The periodic control VCI control counter 121 is composed of an m-bit counter CA, and selects a target VCI in each periodic processing phase within the cell reservation time.

The input of the counter CA is the AND of the outputs S2, R1, and R2 of the processing timing management section 124.

[0101] Therefore, the number N of VCIs targeted by this measurement circuit is
is 2m.

In this embodiment, there are two cycle processing phases within one cell holding time, so Cyc
(=2m-1) Periodic processing is performed once each cell holding time.

Therefore, in this case, as explained in the [Operation] section, the specified value of the minimum arrival interval is the maximum Tmax-Cy.
c (=2n − 2m−1) cell period (
Figure 9).

For example, if n=m=16, this observation circuit can detect violations of the minimum arrival interval regulation value up to a maximum of 32,768 cell periods (corresponding to about 4.7 kb/s).

The cell arrival information holding unit 122 has a cell arrival flag FB and a register RB, and when a cell is detected in the cell arrival/VCI detecting unit 10, the cell arrival flag F
B is set to "1" and VC1 of the arriving cell is held in register RB.

In the cell arrival processing phase, the cell arrival information holding unit 122 reads the previous timestamp value and flag on the memory of the timestamp holding unit 13 corresponding to the VCI value held in the RB when FB=1. These values are passed to the determination unit 126.

The call processing information holding unit 123 has a call processing flag FC1, a call processing type flag FC2, a VCI register RC1, and a specified value register RC2.

[0108] When a call processing request is received, the call processing flag FC
Let 1 be "1".

[0109] Also, call processing type information is written to flag FC2.

In this embodiment, it is assumed that call setting processing is performed when FC2=0, and call cancellation processing is performed when FC2=1.

Further, the value of the VCI to be subjected to call processing is held in the register RC1.

[0112] Furthermore, when setting up a call, a specified value to be set is held in register RC2.

[0113] In the call setting phase, the call processing information holding unit 123 specifies the minimum cell arrival interval corresponding to peak traffic at the time of call connection, and stores data in the memory corresponding to the VCI assigned to the call in the specified value holding unit 11. Dmin (V
CI).

[0114] At this time, the flag F (VCI) on the memory corresponding to the VCI in the time stamp holding unit 13
Set “ON” to

The processing timing management section 124 receives the clock C8 from the clock section 15 and counts up the timing control counter TC.

The timing control counter TC is a 4-bit cyclic counter, and the value of the upper 2 bits of the timing control counter TC is input to the decoder DC1, and the phase
Control signals S1 to S3 corresponding to ~■ are obtained as outputs (Table 1).

[0117]

[Table 1]

The lower two bits of the timing control counter TC control the operation within each phase, and are input to the decoder DC2 and stored in the memory 111 in the specified value holding section 11.
A write/read signal (R1/W1) of , a write/read signal (R2/W2) of the memory 131 in the time stamp holding section 13, and a judgment timing signal CS of the judgment section 126 are obtained as outputs.

When control signal S1=1, cell arrival processing is performed as follows:
When S2=1, periodic processing is performed, and when S3=1, call setting processing is performed (Table 1).

The VCI selection selector 125 selects a VCI to be used in each processing phase within the cell holding time.

[0121] That is, the output S1 of the processing timing management section
, S2, and S3, the periodic control VCI control counter 12
1. Cell arrival information holding unit 122 and call processing information holding unit 1
It is determined which VCI held in 23 is to be used.

[0122] The determination unit 126 is a VCI selection selector 125.
It is determined whether the VCI of the output satisfies a specified value.

[0123] The V selected by the VCI selection selector 125
Using CI as an address, the time stamp value TST and the value of the flag F held in the time stamp holding unit 13 are read out.

[0124] When the value of flag F is ON, it is assumed that the specified value is unconditionally satisfied.

[0125] If the value of flag F is OFF, determination is made according to the following rules.

The value obtained by subtracting the time stamp value TST held in the time stamp holding unit 13 from the output TIM of the timer counter 14 is compared with the specified value Dmin held in the specified value holding unit 11. The subtraction value is D
If it is smaller than min, it is judged as a violation and Dmin
In the above cases, it is determined that there is no violation.

After the violation of the specified value is determined, the operations are different between the cell arrival processing phase and the periodic processing phase.

In the cell arrival processing phase, if it is determined that the specified value has been violated, the violation processing unit 3 is notified of a violation detection signal.

On the other hand, in the periodic processing phase, if it is determined that the specified value is satisfied, the flag F of the time stamp holding section 13 is set to ON using the VCI as an address.

As shown in the [Problems to be Solved by the Invention] section, if one bit is not provided in the "flag" column on the memory table of the time stamp holding unit 13, the cell arrival interval If the timer counter 14 cycles twice during the time, it may be determined that the specified value has been violated even though the specified minimum arrival interval is sufficiently satisfied.

The operation of this embodiment will be described below using examples in which the timer counter 14 cycles only once and twice during the cell arrival interval with N=16 and n=2.

Since n=2, periodic processing is performed on the VC once every two cells as shown in FIG.

[0133] First, a case will be described in which a cell with the relevant VCI value arrives at time 65000 and the timer counter cycles only once until the next cell with the relevant VCI value arrives.

[0134] When a cell having the VCI value arrives at time 65000, the timer value 65000 is written to the time stamp holding section 13 using the VCI as an address.

[0135] Furthermore, the flag of the VCI value is set to OFF.

At times 65001 and 65535, the VCI is subjected to periodic processing.

In the periodic processing phase, the VCI selection selector 125 selects the value of the periodic control VCI control counter 121 as the VCI value.

[0138] The determination unit 126 reads the time stamp (VCI) and flag (VCI) from the memory of the time stamp holding unit 13 and the specified value Dmin (VCI) from the specified value holding unit 11 using the VCI value as an address. judge.

[0139] At both times 65001 and 65535, the cell arrival interval regulation is not satisfied, so the flag (VCI) of the VCI remains set to "OFF".

[0140] When the timer counter completes one cycle at time 65535 and a cell with the relevant VCI value arrives at time 164, the cell arrival/VCI detection unit 10 detects the arrival of the cell and the VCI value of the cell, and sends the signal to the control unit 12. send.

Correspondingly, the cell arrival information holding unit 122
sets the cell arrival flag FB to "1" and holds the VCI value in the register RB.

In the cell arrival processing phase, the VCI selection selector 125 selects the VCI value of the arriving cell held in the RB of the cell arrival information holding section 122.

The determination unit 126 uses the VCI value as an address to read the time stamp (VCI) and flag (VCI) from the memory of the time stamp holding unit 13 and the specified value Dmin (VCI) from the specified value holding unit 11 and makes a judgment. do.

[0144] In this case, since the flag is OFF and the timestamp value and timer value are 65000 and 164, respectively, it is determined that the specified values are not satisfied, and the arriving cell is processed as a violation (violation processing Methods include discarding the violating cell, marking the violating cell and forwarding it as a low-priority cell, etc.)

[0145] Also, 164 as the time stamp value and "OFF" as the flag are written into the time stamp holding unit 13 using the VCI as an address.

[0146] After that, if no cell with the VCI arrives until time 945, it is determined that the VCI satisfies the specified value in the periodic processing phase at time 945, and a flag is sent to the time stamp holding unit 13 using the VCI as an address. “ON” is written.

Next, a case will be described in which a cell having the VCI value arrives at time 65000 and the timer counter 14 cycles twice until the next cell having the VCI value arrives for the first time.

[0148] When a cell having the VCI value arrives at time 65000, the timer value 65000 is written to the time stamp holding section 13 using the VCI as an address.

[0149] At time 65535, the timer counter 14 completes one cycle, and at time 245, periodic processing is performed on the VCI.

In the periodic processing phase, the VCI selection selector 125 selects the value of the periodic control VCI control counter 121 as the VCI value.

[0151] The determining unit 126 uses the VCI value as an address to read the timestamp (VCI) and flag (VCI) from the memory of the timestamp holding unit 13 and the specified value Dmin (VCI) from the specified value holding unit 11 and makes a judgment. do.

[0152] In this case, the timestamp value and timer value are 65000 and 245, respectively, so the previous VC
The elapsed time since the cell with I arrived is 781, which satisfies the specified value of 780.

[0153] "ON" is written as a flag in the time stamp holding unit 13 using the VCI as an address.

Furthermore, at time 65535, timer counter 1
4 completes one cycle and a cell with the VCI arrives at time 164, the cell arrival/VCI detection section 10 detects the arrival of the cell and the VCI value of that cell, and sends it to the observation circuit control section 12.

Correspondingly, the cell arrival information holding unit 122
sets the cell arrival flag FB to "1" and holds the VCI value in the register RB.

In the cell arrival processing phase, the VCI selection selector 125 selects the VCI value of the arriving cell held in the RB of the cell arrival information holding unit 122.

[0157] The determination unit 126 reads the time stamp (VCI) and flag (VCI) from the memory of the time stamp holding unit 13 and the specified value Dmin (VCI) from the specified value holding unit 11 using the VCI value as an address. judge.

[0158] The timestamp value and timer value are 65,000 and 164, respectively, and the calculated elapsed time is 780, but since the flag is "ON", it is assumed that the cell in question satisfies the specified value without error. It will be judged.

[0159]

[Effects of the Invention] As explained above, according to the present invention,
By periodically detecting violations of the minimum cell arrival interval regulations, even if the timer counter completes one cycle when cells arrive at intervals longer than a certain value, accurate observation and detection of violations of the minimum cell arrival interval regulations can be ensured. Detection becomes possible.

[Brief explanation of the drawing]

FIG. 1 shows an overview of the invention.

FIG. 2 shows a method for specifying peak speed in an ATM network.

FIG. 3 is a conventionally proposed peak speed violation detection circuit using time stamps.

FIG. 4 shows a case where a violation is detected even though the specified value is satisfied when the circuit of FIG. 3 is used.

FIG. 5 is a configuration diagram of a traffic observation circuit proposed by the present invention.

FIG. 6 is an example of processing phases within one cell holding time.

FIG. 7 shows the time relationship of each processing phase within one cell holding time.

FIG. 8 is a configuration diagram of an observation circuit control section.

FIG. 9 shows the relationship between the minimum arrival interval specified value and the periodic processing time in the traffic observation circuit proposed by the present invention.

FIG. 10 is a time-series diagram showing an example of the operation of the traffic observation circuit proposed by the present invention.

[Explanation of symbols]

1 Line 3 Violation processing section 10 Cell arrival/VCI detection section 11 Standard value holding section 12 Observation circuit control section 13 Time stamp holding section 14 Timer counter 15 Clock section 21 Memory 22 Timer counter 23 Judgment circuit 24 Violation processing section 25 Call Control unit 111 Memory in specified value holding unit 121 Periodic control VCI control counter 122 Cell arrival information holding unit 123 Call processing information holding unit 124 Processing timing management unit 125 VCI selection selector 126 Judgment unit

Claims (1)

[Claims] [Claim 1] In a communication network in which information is divided into fixed-length cells and transferred, traffic observation is performed by setting the peak traffic for each logical channel as the specified value of the cell arrival interval in advance in order to observe the traffic within the network. In the observation circuit, there is a timer that counts up every cell holding time, a holding means that holds the cell arrival time for each logical channel, and a value held in the holding means that holds the cell arrival time and a value of the timer. determining means for determining whether or not the cell arrival interval satisfies the specified value based on the value; and the determining means for determining whether or not the cell arrival interval satisfies the specified value, and the determining means for determining the current time at a specific period for each logical channel, regardless of whether or not a cell has arrived for each logical channel. display means for determining whether or not more than the predetermined value has elapsed since the time of the value held in the holding means, and displaying the result; with reference to the value displayed on the display means corresponding to the logical channel, and if the displayed value has not passed the specified value from the time of the value held in the holding means at the previous judgment time; A traffic observation circuit characterized in that the determining means determines whether or not a cell arrival interval satisfies a specified value based on the timer value representing the current time and the value held in the holding means.