JPH04279069A - Ferroelectric thin film member - Google Patents

Ferroelectric thin film member

Info

Publication number
JPH04279069A
JPH04279069A JP3065320A JP6532091A JPH04279069A JP H04279069 A JPH04279069 A JP H04279069A JP 3065320 A JP3065320 A JP 3065320A JP 6532091 A JP6532091 A JP 6532091A JP H04279069 A JPH04279069 A JP H04279069A
Authority
JP
Japan
Prior art keywords
layer
substrate
single crystal
atoms
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3065320A
Other languages
Japanese (ja)
Inventor
Akihiro Ito
彰浩 伊藤
Koichi Haga
浩一 羽賀
Hiroshi Miura
博 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Research Institute of General Electronics Co Ltd
Ricoh Co Ltd
Original Assignee
Ricoh Research Institute of General Electronics Co Ltd
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Research Institute of General Electronics Co Ltd, Ricoh Co Ltd filed Critical Ricoh Research Institute of General Electronics Co Ltd
Priority to JP3065320A priority Critical patent/JPH04279069A/en
Publication of JPH04279069A publication Critical patent/JPH04279069A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a high-performance dielectric thin film device which can conjugate with Si or GeIC by forming a highly crystallized dielectric film in the form of a substrate. CONSTITUTION:In this ferroelectric thin film member having a ferroelectric oxide layer containing Pb atoms on a single crystal substrate containing at least one of Si atoms and Ge atoms, an intermediate layer which is composed of a cubic crystal and the deviation of the lattice constant of which is <=15% of the lattice constant of the single crystal substrate is provided by one or more layers between the substrate and ferroelectric oxide layer.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、光スイッチ、光変調器
、高集積メモリー、赤外センサー、超音波センサー、マ
イクロアクチュエーター、エレクトロルミネッセンス素
子等に関する。
TECHNICAL FIELD The present invention relates to optical switches, optical modulators, highly integrated memories, infrared sensors, ultrasonic sensors, microactuators, electroluminescent devices, and the like.

【0002】0002

【従来の技術】PbTiO3、PbTiO3のPb及び
Tiの一部をそれぞれLa、Zrで置換した(Pb、L
a)TiO3、Pb(Zr、Ti)O3、(Pb、La
)(Zr、Ti)O3等のPbを含むペロブスカイト構
造酸化物誘電体材料は、次のような優れた特性がある。 (1) 組成比により強誘電性のほか常誘電性や反強誘
電性の材料にもなる。 (2) 誘電率が大きい。 (3) 圧電特性や焦電特性が優れている。 (4) 誘電特性に対応して高い一次および二次の電気
光学効果、メモリ効果を持つ。これらの特性のほかに、
透光性も良好である。 この材料を薄膜化した種々のデバイスが提案されている
。電気光学効果を利用した導波路型光スイッチ、光変調
器、圧電性を利用した超音波センサ、焦電性を利用した
赤外線センサ、強誘電性を利用した不揮発性メモリが報
告されている。さらに、この材料が高い誘電率を有する
ことを利用して、エレクトロルミネッセンス素子の絶縁
膜として用い、素子の駆動電圧を低くすることや、ダイ
ナミックRAMのキャパシタ絶縁膜として用い、セルの
小面積化を計ることが試みられている。このペロブスカ
イト構造誘電体材料を単結晶基板上に成長させることに
より、膜が単結晶化又は高配向化して結晶性が向上する
。この誘電体材料の前記各特性は、結晶学的異方性があ
り、膜の結晶性を高めるほど前記各特性の異方性がより
顕著に出現し、面方位を選択すれば、より大きな特性を
引き出すことができる。また、結晶性を高めると結晶粒
界による光の散乱が少なくなり、透光性も向上する。 このようなねらいで各種単結晶上で、この高誘電体材料
を結晶性よく成膜することが行われている。しかし、S
iやGe単結晶基板上に直接この誘電体膜を結晶性よく
成長させた例はない。この理由としてこの酸化物誘電体
膜の成長過程中に、膜に構成元素となる酸素がSi、G
e表面を酸化させ、表面に非晶質のSiO2、GeO2
層ができるため、誘電体膜成長時、Si、Ge単結晶基
板からの影響が遮断されるためであると考えられる。
[Prior Art] Pb and Ti in PbTiO3 and PbTiO3 are partially replaced with La and Zr, respectively (Pb, L
a) TiO3, Pb(Zr, Ti)O3, (Pb, La
) (Zr, Ti)O3 and other perovskite structure oxide dielectric materials containing Pb have the following excellent properties. (1) Depending on the composition ratio, it can be a paraelectric or antiferroelectric material in addition to ferroelectric. (2) Large dielectric constant. (3) Excellent piezoelectric and pyroelectric properties. (4) It has high first- and second-order electro-optical effects and memory effects corresponding to its dielectric properties. Besides these characteristics,
Translucency is also good. Various devices using thin films of this material have been proposed. Waveguide optical switches and optical modulators that utilize electro-optic effects, ultrasonic sensors that utilize piezoelectricity, infrared sensors that utilize pyroelectricity, and nonvolatile memories that utilize ferroelectricity have been reported. Furthermore, by utilizing the high dielectric constant of this material, it can be used as an insulating film for electroluminescent devices to lower the driving voltage of the device, and it can be used as a capacitor insulating film for dynamic RAM to reduce the area of cells. Attempts are being made to measure. By growing this perovskite structure dielectric material on a single-crystal substrate, the film becomes single-crystalline or highly oriented, resulting in improved crystallinity. Each of the above-mentioned properties of this dielectric material has crystallographic anisotropy, and as the crystallinity of the film is increased, the anisotropy of each of the above-mentioned properties appears more prominently, and if the plane orientation is selected, the properties become larger. can be extracted. In addition, increasing crystallinity reduces light scattering by grain boundaries and improves translucency. With this aim, films of this high dielectric constant material with good crystallinity have been formed on various single crystals. However, S
There is no example of directly growing this dielectric film with good crystallinity on an i or Ge single crystal substrate. The reason for this is that during the growth process of this oxide dielectric film, oxygen, which is a constituent element of the film, is
eThe surface is oxidized to form amorphous SiO2, GeO2 on the surface.
This is thought to be because the formation of a layer blocks the influence from the Si and Ge single crystal substrates during dielectric film growth.

【0003】そこで、Si、Ge単結晶基板の上に、エ
ピタキシャル成長する中間層を設ける必要がある。中間
層を用いた例は、Si基板上でMgAl2O4層を用い
た例と(特開昭62−39825、特開昭63−551
98)とSi基板上でSrF2、CaF2層を用いた例
がある。しかしMgAl2O4中間層の成長温度が 9
50℃と高温であること、HClガスを主な反応ガスと
して使用することなどプロセス条件が過酷なことにより
、デバイス製造プロセス上制限が多い。CaF2、Sr
F2の場合は、これらの強誘電体との格子整合を考える
と単結晶基板はSi、Geとも(100)方位面が好ま
しい。しかしながらCaF2はSi(100)方位には
エピタキシャル成長しない。SrF2はSi(100)
方位に成長するもののSiに比べ格子定数差が大きく、
この歪みが強誘電体作製上好ましくない。このような点
より従来の成長手法においてはデバイスに応用できる良
好な単結晶強誘電体膜は得られなかった。
[0003] Therefore, it is necessary to provide an epitaxially grown intermediate layer on the Si or Ge single crystal substrate. Examples using an intermediate layer include an example using a MgAl2O4 layer on a Si substrate (Japanese Patent Application Laid-Open No. 62-39825, Japanese Patent Application Laid-open No. 63-551).
98) and an example using SrF2 and CaF2 layers on a Si substrate. However, the growth temperature of the MgAl2O4 intermediate layer is 9
There are many limitations in the device manufacturing process due to harsh process conditions such as the high temperature of 50° C. and the use of HCl gas as the main reaction gas. CaF2, Sr
In the case of F2, considering the lattice matching with these ferroelectric materials, the single crystal substrate is preferably a (100) oriented plane for both Si and Ge. However, CaF2 does not grow epitaxially in the Si (100) orientation. SrF2 is Si(100)
Although it grows in the same direction, it has a large difference in lattice constant compared to Si,
This distortion is unfavorable in the production of ferroelectric materials. For these reasons, conventional growth methods have not been able to produce good single-crystal ferroelectric films that can be applied to devices.

【0004】0004

【発明が解決しようとする課題】本発明の目的は、上述
の問題を解決して、安価でデバイス製造上熟成した半導
体集積回路技術を用いることができるSi、Ge単結晶
基板上に高結晶性の誘電体膜を形成することを可能にす
ることによりSi、Ge又はSi1−XGeXICとの
複合化が可能な高性能誘電体薄膜デバイスを提供するこ
とである。
SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a highly crystalline structure on a Si, Ge single crystal substrate that is inexpensive and allows the use of mature semiconductor integrated circuit technology in device manufacturing. An object of the present invention is to provide a high-performance dielectric thin film device that can be combined with Si, Ge, or Si1-XGeXIC by making it possible to form a dielectric film of.

【0005】[0005]

【課題を解決するための手段】上記課題を解決するため
の本発明の構成は、特許請求の範囲に記載のとおりの薄
膜強誘電体部材である。本薄膜強誘電体部材についての
詳細を以下に説明する。本強誘電体部材用基板としては
Si原子あるいはGe原子のうち少なくとも1種を有す
る材料すなわちSi、SiGe、Ge等が好ましい。こ
の材料に直接Pb系の酸化物を単結晶成長を試みた場合
、Si、SiGe、Ge等が非常に酸化しやすく、この
層間に結晶系が立方晶でこれらの基板材と格子定数が近
く基板表面がアモルファス化しにくい中間層を設ける必
要がある。中間層の格子定数と単結晶基板の格子定数と
の差が単結晶基板の格子定数の15%より大きいと、中
間層が多結晶体となり、その上に堆積させる、Pb系の
酸化物層をエピタキシャル成長させることができない。
[Means for Solving the Problems] The structure of the present invention for solving the above problems is a thin film ferroelectric member as described in the claims. The details of this thin film ferroelectric member will be explained below. The substrate for the ferroelectric member is preferably a material containing at least one type of Si atoms or Ge atoms, ie, Si, SiGe, Ge, or the like. When attempting to grow a single crystal of Pb-based oxide directly on this material, Si, SiGe, Ge, etc. are very easily oxidized, and the crystal system between these layers is cubic and the lattice constant is close to that of these substrate materials. It is necessary to provide an intermediate layer whose surface is unlikely to become amorphous. If the difference between the lattice constant of the intermediate layer and the lattice constant of the single crystal substrate is larger than 15% of the lattice constant of the single crystal substrate, the intermediate layer becomes a polycrystalline substance, and the Pb-based oxide layer deposited on it becomes polycrystalline. It cannot be epitaxially grown.

【0006】この中間層としてはZn原子を含む材料で
、例えばZnS、ZnSe、Zn(S、Se)、ZnM
nSe、Ga原子を含む材料GaP、AlGaAsその
他の材料としてInP、AlAs、AlP、CaS、C
aSe、SrS等があげられる。また基板材上に他のデ
バイスを作製する場合、この中間層が絶縁物の必要があ
る時は中間層としてF原子を含むものが好ましい。例え
ばCaF2、SrF2、BaF2、(Ca、Sr)F2
、(Ca、Ba)F2、(SrBa)F2等である。し
かしながらこれらの層はSi、Ge(100)上に配向
しにくいため多層構成にする必要がある。多層構成にす
る場合は、基板材とのマッチングを考慮し、格子定数、
配向性のしやすさ、熱膨脹係数等の機能分離が可能にな
る。これらの中間層の膜厚は、単層の場合は10Å〜2
000Å、好ましくは30Å〜1000Åがよい。多層
構成の場合、量子効果を利用する場合は、10Å〜20
0Å、好ましくは20Å〜100Åがよい。また機能分
離層として使用する場合は、1層につき10Å〜200
0Å、好ましくは20Å〜1000Åがよい。この中間
層の作製方法はMBE法、ALE法、EB蒸着法、MO
CVD法、スパッタリング法、熱CVD法、プラズマC
VD法、MOCVD法等があげられる。
[0006] This intermediate layer is made of a material containing Zn atoms, such as ZnS, ZnSe, Zn(S, Se), ZnM
nSe, materials containing Ga atoms, GaP, AlGaAs, and other materials such as InP, AlAs, AlP, CaS, C
Examples include aSe, SrS, etc. Further, when other devices are manufactured on the substrate material, if this intermediate layer is required to be an insulator, it is preferable that the intermediate layer contains F atoms. For example, CaF2, SrF2, BaF2, (Ca, Sr)F2
, (Ca,Ba)F2, (SrBa)F2, etc. However, since these layers are difficult to align on Si or Ge (100), it is necessary to have a multilayer structure. When creating a multilayer structure, consider matching with the substrate material and adjust the lattice constant,
It becomes possible to separate functions such as ease of orientation and coefficient of thermal expansion. The thickness of these intermediate layers is 10 Å to 2 Å in the case of a single layer.
000 Å, preferably 30 Å to 1000 Å. In the case of a multilayer structure, when using quantum effects, the thickness is 10 Å to 20 Å.
The thickness is preferably 0 Å, preferably 20 Å to 100 Å. In addition, when used as a functional separation layer, each layer has a thickness of 10 Å to 200 Å.
The thickness is preferably 0 Å, preferably 20 Å to 1000 Å. The manufacturing method of this intermediate layer is MBE method, ALE method, EB evaporation method, MO
CVD method, sputtering method, thermal CVD method, plasma C
Examples include the VD method and the MOCVD method.

【0007】次に本構成の主要機能を満足させるPb原
子を含む酸化物を推積する。この酸化物としてはPbT
iO3、(Pb、La)TiO3、Pb(Zn、Ti)
O3、(Pb、La)(Zn、Ti)O3があげられこ
れらの層は使用目的に応じ単層あるいは多層構造で作製
される。この層の膜厚は単層の場合は0.1μm〜20
μmがよく、好ましくは0.2μm〜15μmがよい。 これらの層を多層形成する場合は、量子効果を利用する
場合、10Å〜200Åがよく、好ましくは20Å〜1
00Åがよい。この層を100層〜5000層形成する
と量子効果デバイスとして応用が可能である。またこれ
らの層を圧電性、強誘電性等の利用より機能分離し、多
層化する事も可能である。この場合、1層の膜厚は10
0Å〜2μmがよい。これらの層の作製方法は、MBE
法、ALE法、EB蒸着法、MO−CVD法、スパッタ
リング法、熱CVD法、レーザー蒸着法、プラズマCV
D法等があげられる。図1は本発明の基本構成を示した
もので、単結晶基板1の上に順次、中間層2および強誘
電体膜3を有するものである。これまでの例ではSi、
SiGe、Ge基板上に中間層を設け、その上部にPb
を含む酸化物層を設ける事を説明したが、中間層とPb
を含む酸化物層の間にこれらの層の接合性を向上する目
的又は酸化物強誘電体膜の機能をより高める目的で単結
晶酸化物からなる酸化物バッファ層を設ける。これらの
酸化物バッファ層は材料名で限定するものではなく、結
晶単位格子の少なくとも1つの結晶面内で構成金属元素
のうち、少なくとも1種の元素の4個の原子の配置が、
1辺の長さが5.1〜6.1Åの範囲の四角形をなす(
整合条件A)か、3.5〜4.8Åの範囲の四角形をな
し(整合条件B)、かつ少なくとも1つの結晶面内で4
個の酸素原子の配置が1辺の長さが3.5〜4.8Åの
範囲の四角形をなす(整合条件C)、1辺の長さが2.
5〜3.4Åの範囲の四角形をなす(整合条件D)酸化
物である。整合条件AとBは下地立方晶の中間層の上に
酸化物バッファ層がエピタキシャル成長するための条件
であり、整合条件CとDは酸化物バッファ層上にPbを
含む酸化物強誘電体層がエピタキシャル成長するための
条件である。つまり酸化物バッファ層はAC、AD、B
C、BDの組合せのいずれかを満たす結晶構造をもつ材
料からなる。例としてC−ZrO2、ThO2(整合条
件ABD)、γ−Al2O3、SrO(整合条件ABC
)、MgO(整合条件BCD)、MgAl2O4(整合
条件AD)、SrTiO3、BaTiO3(整合条件B
D)等が挙げられる。
Next, an oxide containing Pb atoms that satisfies the main functions of this structure is estimated. This oxide is PbT
iO3, (Pb, La)TiO3, Pb(Zn, Ti)
O3, (Pb, La) (Zn, Ti) O3, and these layers are produced in a single layer or multilayer structure depending on the purpose of use. The thickness of this layer is 0.1 μm to 20 μm in the case of a single layer.
The thickness is preferably 0.2 μm to 15 μm. When forming multiple layers of these layers, the thickness is preferably 10 Å to 200 Å, preferably 20 Å to 1
00 Å is good. If 100 to 5000 layers of this type are formed, it can be applied as a quantum effect device. It is also possible to separate these layers functionally by utilizing piezoelectricity, ferroelectricity, etc., and to make them multilayered. In this case, the thickness of one layer is 10
The thickness is preferably 0 Å to 2 μm. The fabrication method for these layers is MBE
method, ALE method, EB evaporation method, MO-CVD method, sputtering method, thermal CVD method, laser evaporation method, plasma CV
Examples include method D. FIG. 1 shows the basic configuration of the present invention, in which an intermediate layer 2 and a ferroelectric film 3 are sequentially formed on a single crystal substrate 1. In the previous examples, Si,
An intermediate layer is provided on the SiGe, Ge substrate, and Pb is placed on top of the intermediate layer.
Although it has been explained that an oxide layer containing Pb is provided, the intermediate layer and Pb
An oxide buffer layer made of a single crystal oxide is provided between the oxide layers containing single crystal oxide for the purpose of improving the bonding properties of these layers or for the purpose of further enhancing the function of the oxide ferroelectric film. These oxide buffer layers are not limited by the name of the material, but the arrangement of four atoms of at least one element among the constituent metal elements within at least one crystal plane of the crystal unit cell is
It forms a rectangle with a side length of 5.1 to 6.1 Å (
Matching condition A) or square shape in the range of 3.5 to 4.8 Å (matching condition B), and 4 Å in at least one crystal plane
The arrangement of oxygen atoms forms a rectangle with a side length of 3.5 to 4.8 Å (matching condition C), and a side length of 2.5 Å.
It is an oxide having a rectangular shape in the range of 5 to 3.4 Å (matching condition D). Matching conditions A and B are conditions for epitaxial growth of an oxide buffer layer on the underlying cubic intermediate layer, and matching conditions C and D are for growing an oxide ferroelectric layer containing Pb on the oxide buffer layer. This is a condition for epitaxial growth. In other words, the oxide buffer layers are AC, AD, B
It is made of a material having a crystal structure that satisfies either the combination of C and BD. Examples include C-ZrO2, ThO2 (matching condition ABD), γ-Al2O3, SrO (matching condition ABC
), MgO (matching condition BCD), MgAl2O4 (matching condition AD), SrTiO3, BaTiO3 (matching condition B
D) etc.

【0008】Si及びGeを含む単結晶基板上にこれら
の中間層を作製する際、発明が解決すべき課題の欄に記
載したように酸化物形成を行うと、Si及びGe表面に
SiO2、GeO2が形成されてしまう。そのため、Z
nS、ZnSe、Zn(S、Se)、ZnMnSe、G
aP、AlGaAs、InP、AlAs、AlP等を形
成する必要がある。Si及びGe基板は大気中に放置し
た場合、表面に酸化物が形成されるため、これらの中間
層の形成の際これらの酸化物を除去する必要がある。こ
れらの酸化物の除去法は大別して4種類ほどある。まず
、1000℃以上の熱によってSiO2を蒸発させる方
法、エッチングガス、例えばHCl、H2等を用いて1
000℃程度の加熱によりエッチングしてしまう方法、
表面の酸化物を湿式エッチング等により除去した後、表
面をF、H、S等の元素によりパッシベーションして真
空中において700℃程度に加熱し除去する方法、真空
中でシリコンを蒸着し、SiO層を表面に形成後、70
0℃程度でSiOを蒸発してしまう方法等が考えられる
。これらの方法の中で好ましいのは700℃程度に加熱
する方法である。高温に加熱した場合、SiあるいはG
e基板が変型したり、前もってデバイスを作製してある
場合、これらのデバイスが破壊してしまうことが予測さ
れる。これらの酸化物除去法を行った後、中間層を形成
する必要がある。
When producing these intermediate layers on a single crystal substrate containing Si and Ge, if oxides are formed as described in the section of the problem to be solved by the invention, SiO2 and GeO2 are formed on the Si and Ge surfaces. is formed. Therefore, Z
nS, ZnSe, Zn(S, Se), ZnMnSe, G
It is necessary to form aP, AlGaAs, InP, AlAs, AlP, etc. When Si and Ge substrates are left in the atmosphere, oxides are formed on their surfaces, so it is necessary to remove these oxides when forming these intermediate layers. There are roughly four types of methods for removing these oxides. First, a method of evaporating SiO2 with heat of 1000°C or higher, using an etching gas such as HCl, H2, etc.
A method of etching by heating to about 000℃,
After removing the oxide on the surface by wet etching etc., the surface is passivated with elements such as F, H, S, etc. and heated to about 700°C in vacuum to remove it. Silicon is evaporated in vacuum and SiO layer is removed. After forming on the surface, 70
Possible methods include evaporating SiO at about 0°C. Among these methods, preferred is the method of heating to about 700°C. When heated to high temperatures, Si or G
If the e-substrate is deformed or devices have been previously fabricated, it is expected that these devices will be destroyed. After performing these oxide removal methods, it is necessary to form an intermediate layer.

【0009】[0009]

【実施例】以下、実施例によって、本発明を具体的に説
明する。 実施例1 Si基板を湿式エッチング法(RCA洗浄法)により酸
化物を除去し、99.99%のHFに浸漬し表面をH原
子及びF原子でパッシベーションする。この基板を数枚
準備し、格子定数の異なる中間層を真空蒸着法により1
000Å形成した。真空蒸着装置の圧力は10−9To
rrとし、中間層を形成した。中間層としては下記表1
に示す材料を用いた。Si基板の格子定数は5.43Å
であり使用した中間層はBN、GaAs、ZnSe、Z
nS、InSbを用いた。これら各種中間層形成後、ス
パッタリング法によりPbTiO3薄膜を1μm形成し
た。この薄膜形成後のエピタキシャル成長の可否と表面
性を表1に示す。格子定数差は次式により定義した。
[Examples] The present invention will be specifically explained below with reference to Examples. Example 1 Oxide is removed from a Si substrate by a wet etching method (RCA cleaning method), and the surface is passivated with H atoms and F atoms by immersing it in 99.99% HF. Several of these substrates are prepared, and one intermediate layer with different lattice constants is formed by vacuum evaporation.
000 Å was formed. The pressure of the vacuum evaporation equipment is 10-9To
rr to form an intermediate layer. Table 1 below shows the middle class.
The materials shown in were used. The lattice constant of the Si substrate is 5.43 Å
The intermediate layers used were BN, GaAs, ZnSe, and Z
nS and InSb were used. After forming these various intermediate layers, a 1 μm thick PbTiO3 thin film was formed by sputtering. Table 1 shows whether or not epitaxial growth can be performed after this thin film is formed and the surface properties. The lattice constant difference was defined by the following equation.

【数1】 表面性の定義は、×:Rmax>5μm、○:0.5μ
m<Rmax<5μm、 ◎:0.5μm>Rmax とした。表1よりわかるように、Siの格子定数と中間
層の格子定数差が19%以上においてはPb系酸化物は
エピ成長せず、表面性も悪い。
[Equation 1] The definition of surface property is ×: Rmax>5 μm, ○: 0.5 μm
m<Rmax<5 μm, ◎: 0.5 μm>Rmax. As can be seen from Table 1, when the difference between the lattice constant of Si and the lattice constant of the intermediate layer is 19% or more, the Pb-based oxide does not grow epitaxially and the surface properties are poor.

【0010】実施例2 中間層上にPb系酸化物を直接形成する場合、膜の接合
力が不足する場合があり、この場合Pb系酸化物と中間
層の間に前記酸化物バッファ層を形成するとよい。実施
例2においてはこの酸化物の形成と効果について示す。 単結晶Ge(100)基板上にZnS(100)を中間
層として形成し、この上部にMBE法によってγ−Al
2O3層を100Å形成する。このγ−Al2O3層上
にPb(ZrTi)O3薄膜を1μmスパッタリング法
により形成した。γ−Al2O3層の形成により膜の密
着性がGe基板上にZnSを直接成長するものに比べ2
0%程度向上した。
Example 2 When a Pb-based oxide is directly formed on the intermediate layer, the bonding strength of the film may be insufficient. In this case, the oxide buffer layer is formed between the Pb-based oxide and the intermediate layer. It's good to do that. In Example 2, the formation and effects of this oxide will be described. ZnS (100) is formed as an intermediate layer on a single crystal Ge (100) substrate, and γ-Al is deposited on top of this by MBE method.
A 2O3 layer is formed to a thickness of 100 Å. A 1 μm thick Pb(ZrTi)O3 thin film was formed on this γ-Al2O3 layer by sputtering. Due to the formation of the γ-Al2O3 layer, the adhesion of the film is improved by 2 compared to that of directly growing ZnS on the Ge substrate.
It improved by about 0%.

【表1】[Table 1]

【0011】前記したPb系単結晶薄膜は強誘電部材と
して使用するに十分な結晶性あるいは表面性を有する。 この部材を利用したデバイス応用について以下に記載す
る。この部材を利用した光デバイスは、光スイッチ、光
変調器、エレクトロルミネセンス素子等があげられる。 さらに光集積メモリ用のコンデンサ、赤外センサ、超音
波センサ、マイクロアクチュエータ非線形光学素子が挙
げられる。Pb素単結晶薄膜はS、Ge原子の少なくと
も一方を有する単結晶基板上に形成されており、この単
結晶基板を用いたトランジスタの駆動回路により、上記
強誘電体を応用したデバイスを直接駆動することもでき
る。さらにSi、Ge原子の少なくとも一方を含む基板
上にセンサーや発光素子を形成し、上記強誘電体を応用
したデバイスと組合わせ、O−O、O−E、E−Oデバ
イスを作製できることはいうまでもない。
The Pb-based single crystal thin film described above has sufficient crystallinity or surface properties to be used as a ferroelectric member. Device applications using this member will be described below. Optical devices using this member include optical switches, optical modulators, electroluminescent elements, and the like. Further examples include capacitors for optical integrated memory, infrared sensors, ultrasonic sensors, microactuators, and nonlinear optical elements. The Pb single crystal thin film is formed on a single crystal substrate containing at least one of S and Ge atoms, and a transistor drive circuit using this single crystal substrate directly drives the device applying the ferroelectric material. You can also do that. Furthermore, it is possible to fabricate O-O, O-E, and E-O devices by forming sensors and light-emitting elements on a substrate containing at least one of Si and Ge atoms, and combining them with devices applying the above-mentioned ferroelectric materials. Not even.

【0012】光スイッチ素子とエレクトロネッセンス(
EL)素子を例にあげて応用実施例の構成を説明する。 まず、導波路スイッチの1種であるTIR(Total
 Internal Reflection)型スイッ
チで説明する。Si原子又はGe原子の少なくとも一方
を含有する単結晶基板上に結晶系が立方晶系で格子定数
が5.2〜5.9Åである材料であるZnS、ZnSe
、Zn(S、Se)、CaS、CaSe、SrS、Ga
P、AlGaAs、GaAs、InP、SrF2、Ca
F2等のうちいずれか1層又は複数層の中間層を10〜
300000Åの膜厚でエピタキシャル成長させる。成
膜手法はMBE(Molecular Bezm Ep
itaxy)法、ALE法(Atomic Layer
 Epitaxy)法、エレクトロンビーム蒸着法、M
OCVD(Metal Orgamic Chemic
al Vapor Deposition)法、スパッ
タリング法、熱CVD法、プラズマCVD法等により行
う。次に、PbTiO3、PbTiO3のPb原子及び
Ti原子の一部をそれぞれLa、Zrで置換した(Pb
、La)TiO3、Pb(Z、Ti)O3、(Pb、L
a)(Zr、Ti)O3等のPb原子を含むペロブスカ
イト構造酸化物誘電体材料からなる誘電体膜を1層又は
複数層を膜厚100〜300000Åの範囲で結晶性よ
く成長させる。この誘電体膜の成膜方法は、MBE法、
ALE法、エレクトロンビーム蒸着法、MOCVD法、
スパッタリング法、熱CVD法、プラズマCVD法等に
よる。次に電極層としてAl、Au、Pt、ITO、I
n2O3、SnO2、ZnO等をMOCVD法、スパッ
タリング法、プラズマCVD法、熱CVD法、エレクト
ロンビーム蒸着法等を用いて形成する。なお、前記酸化
物バッファ層として、中間層と誘電体膜の間にSi/G
e単結晶基板又は中間層での光の吸収による光損失を防
止する目的で、屈折率がPb系強誘電体膜より小さいZ
rO2、Y2O3、La2O3、Al2O3、TiO2
、MgO、SrTiO3、BaTiO3、LiNbO3
、LiTaO3、MgAl2O4などのエピタキシャル
膜を100〜300000Åの膜厚で、MBE法、AL
E法、エレクトロンビーム蒸着法、MOCVD法、スパ
ッタリング法、熱CVD法、プラズマCVD法で設ける
場合もある。同様の目的で上部バッファ層として、誘電
体膜と電極膜の間にSiO2、Ta2O5、Y2O3、
La2O3、Al2O3、TiO2、MgO、SrTi
O3、BaTiO3、LiNbO3、LiTaO3、M
gAl2O4、CaF2、SrF2、BaF2、ZnS
等の非晶質又は多結晶又はエピタキシャル成長膜を膜厚
 100〜300000Åで設ける場合もある。
[0012] Optical switch elements and electronescence (
The configuration of an applied example will be described using an EL) element as an example. First, we will introduce TIR (Total), which is a type of waveguide switch.
This will be explained using an internal reflection) type switch. ZnS, ZnSe, which is a material with a cubic crystal system and a lattice constant of 5.2 to 5.9 Å, is deposited on a single crystal substrate containing at least one of Si atoms or Ge atoms.
, Zn(S, Se), CaS, CaSe, SrS, Ga
P, AlGaAs, GaAs, InP, SrF2, Ca
One or more intermediate layers of F2 etc. are 10~
Epitaxial growth is performed to a film thickness of 300,000 Å. The film formation method is MBE (Molecular Bezm Ep).
itaxy) method, ALE method (Atomic Layer
Epitaxy) method, electron beam evaporation method, M
OCVD (Metal Organic Chemical
This is carried out by a vapor deposition method, a sputtering method, a thermal CVD method, a plasma CVD method, or the like. Next, some of the Pb atoms and Ti atoms of PbTiO3 and PbTiO3 were replaced with La and Zr, respectively (Pb
, La)TiO3, Pb(Z,Ti)O3, (Pb,L
a) One or more layers of a dielectric film made of a perovskite structure oxide dielectric material containing Pb atoms such as (Zr, Ti)O3 are grown with good crystallinity to a film thickness of 100 to 300,000 Å. The method for forming this dielectric film is MBE method,
ALE method, electron beam evaporation method, MOCVD method,
By sputtering method, thermal CVD method, plasma CVD method, etc. Next, as an electrode layer, Al, Au, Pt, ITO, I
n2O3, SnO2, ZnO, etc. are formed using a MOCVD method, a sputtering method, a plasma CVD method, a thermal CVD method, an electron beam evaporation method, or the like. Note that as the oxide buffer layer, Si/G is used between the intermediate layer and the dielectric film.
e In order to prevent optical loss due to absorption of light in the single crystal substrate or intermediate layer, Z
rO2, Y2O3, La2O3, Al2O3, TiO2
, MgO, SrTiO3, BaTiO3, LiNbO3
, LiTaO3, MgAl2O4, etc. with a thickness of 100 to 300,000 Å, MBE method, AL
It may be provided by the E method, electron beam evaporation method, MOCVD method, sputtering method, thermal CVD method, or plasma CVD method. For the same purpose, SiO2, Ta2O5, Y2O3,
La2O3, Al2O3, TiO2, MgO, SrTi
O3, BaTiO3, LiNbO3, LiTaO3, M
gAl2O4, CaF2, SrF2, BaF2, ZnS
In some cases, an amorphous, polycrystalline, or epitaxially grown film such as the above may be provided with a thickness of 100 to 300,000 Å.

【0013】これを二重絶縁構造エレクトロルミネッセ
ンス(EL)素子を例にあげて説明する。Si/Ge単
結晶基板上にZnS、ZnSe、Zn(S、Se)、C
aS、CaSe、SrS、GaP、AlGaAs、Ga
As、InPの材料で1層又は複数層からなる中間層を
厚さ10〜300000Åの範囲でエピタキシャル成長
させる。 エピタキシャル成長の手段としてはMBE法、ALE法
、エレクトロンビーム蒸着法、MOCVD法、スパッタ
リング法、熱CVD法、プラズマCVD法等の方法を単
独もしくは併用して用いる。次に、この中間層上に前記
誘電体膜を1層又は複数層 100〜300000Åの
範囲で結晶性よく成長させる。この誘電体膜の成膜方法
はMBE法、ALE法、エレクトロンビーム蒸着法、ス
パッタリング法、MOCVD法、熱CVD法、プラズマ
CVD法等による。上記誘電体層の上に、高結晶性発光
層を成長させる。この発光層はZnS、ZnSe、Zn
(S、Se)等を母材とし、発光中心としてMnを添加
したZnS:Mn系材料、もしくは上記母材にCuを添
加したZnS:Cu系材料、もしくは上記母材に希土類
フッ化物(TbF3、ErF3、NdF3、SmF3等
)を添加した材料系等が用いられる。また、SrSを母
材とし、発光中心にCe、Sm、Tb、Er、Mn等を
添加した材料やCaSを母材とし発光中心にEr等を添
加した材料も発光層として用いられる。この発光層は単
層と限らず多層構成もとりうる。さらに、上記発光層の
上に上部絶縁層として、上記誘電体材料、SiO2、S
iON、Si3N4、ZnO、Al2O3、MgO、S
rTiO3、Y2O3、Ta2O5、MgAl2O4、
CaF2、SrF2、BaF2等の非晶質又は多結晶又
はエピタキシャル成長膜を膜厚100〜300000Å
で設ける。膜作成方法としては、MBE法、ALE法、
スパッタリング法、エレクトロンビーム蒸着法、MOC
VD法、熱CVD法、プラズマCVD法等による。
This will be explained using a double insulation structure electroluminescent (EL) element as an example. ZnS, ZnSe, Zn(S, Se), C on Si/Ge single crystal substrate
aS, CaSe, SrS, GaP, AlGaAs, Ga
An intermediate layer made of one or more layers of As or InP is epitaxially grown to a thickness of 10 to 300,000 Å. As a means for epitaxial growth, methods such as MBE method, ALE method, electron beam evaporation method, MOCVD method, sputtering method, thermal CVD method, plasma CVD method, etc. are used alone or in combination. Next, one or more layers of the dielectric film are grown on this intermediate layer to a thickness of 100 to 300,000 Å with good crystallinity. The method for forming this dielectric film is MBE method, ALE method, electron beam evaporation method, sputtering method, MOCVD method, thermal CVD method, plasma CVD method, or the like. A highly crystalline light emitting layer is grown on the dielectric layer. This light emitting layer is made of ZnS, ZnSe, Zn
(S, Se) etc. as a base material and Mn is added as a luminescent center, or a ZnS:Cu system material where Cu is added to the base material, or a rare earth fluoride (TbF3, A material system doped with ErF3, NdF3, SmF3, etc. is used. Further, materials that have SrS as a base material and have Ce, Sm, Tb, Er, Mn, etc. added to the luminescent center, or materials that have CaS as the base material and have Er, etc. added as the luminescent center can also be used as the light emitting layer. This light-emitting layer is not limited to a single layer, and may have a multilayer structure. Furthermore, an upper insulating layer made of the dielectric material, SiO2, S
iON, Si3N4, ZnO, Al2O3, MgO, S
rTiO3, Y2O3, Ta2O5, MgAl2O4,
Amorphous, polycrystalline, or epitaxially grown film of CaF2, SrF2, BaF2, etc. with a thickness of 100 to 300,000 Å
Provided by Film preparation methods include MBE method, ALE method,
Sputtering method, electron beam evaporation method, MOC
By VD method, thermal CVD method, plasma CVD method, etc.

【0014】実施例3 図2に示すように、Si単結晶基板1上にZnSを中間
層2としてTIR型光スイッチを作製した。Si単結晶
(100)基板1上にZnS中間層2をMBE法により
基板温度 500℃で厚さ1500Å形成した。中間層
2はジンクブレンド構造で面方位が(100)の良好な
配向性を示した。 次に、(Pb0.84La0.16)(Zr0.5Ti
0.5)0.96O3組成の誘電体層をMOCVD法で
基板温度 600℃で厚さ4000Å形成した。誘電体
層はペロブスカイト構造で面方位(100)の良好な配
合性を示した。これをイオンビームエッチング加工して
幅20μm、膜厚差交差角2°、厚さ600Åのリッジ
型導波路を形成した。さらに交差部には導波光損欠を防
ぐためバッファ層7としてTa2O5薄膜を反応性スパ
ッタリング法で、厚さ2000Å形成した。その上に駆
動用のAlプレーナー電極6をスパッタリング法により
、長さ1.7mm、幅5μmの電極ギャップをもたせ、
厚さ  2000Åで形成した。スイッチング動作実験
は、波長0.633μmのHe−Neレーザー光をGa
Pプリズムを用い導波路へ入れた。駆動電圧15Vでス
イッチング動作が可能で、消光比は1ldBであった。
Example 3 As shown in FIG. 2, a TIR type optical switch was fabricated on a Si single crystal substrate 1 using ZnS as an intermediate layer 2. A ZnS intermediate layer 2 was formed to a thickness of 1500 Å on a Si single crystal (100) substrate 1 at a substrate temperature of 500° C. by MBE. Intermediate layer 2 had a zinc blend structure and exhibited good orientation with a plane orientation of (100). Next, (Pb0.84La0.16)(Zr0.5Ti
0.5) A dielectric layer having a composition of 0.96O3 was formed to a thickness of 4000 Å at a substrate temperature of 600° C. by MOCVD. The dielectric layer had a perovskite structure and exhibited good compatibility with the (100) plane orientation. This was processed by ion beam etching to form a ridge-type waveguide having a width of 20 μm, a film thickness difference crossing angle of 2°, and a thickness of 600 Å. Further, a Ta2O5 thin film having a thickness of 2000 Å was formed at the intersection by reactive sputtering as a buffer layer 7 in order to prevent loss of guided light. On top of that, an Al planar electrode 6 for driving is formed by sputtering to create an electrode gap of 1.7 mm in length and 5 μm in width.
It was formed with a thickness of 2000 Å. In the switching operation experiment, a He-Ne laser beam with a wavelength of 0.633 μm was
A P prism was used to enter the waveguide. Switching operation was possible with a drive voltage of 15 V, and the extinction ratio was 1 ldB.

【0015】比較例1 比較として実施例1の構成からZnS中間層を省いた構
成の素子の場合、Si単結晶上に直接成膜したPLZT
誘電体膜はペロブスカイト構造で面方位が(110)(
101)(100)(001)が混在した多結晶体で、
駆動電圧25Vと高電圧印加しないとスイッチング動作
が可能とならず、消光比は7dBと不充分なものであっ
た。
Comparative Example 1 For comparison, in the case of an element having a structure in which the ZnS intermediate layer was omitted from the structure of Example 1, a PLZT film formed directly on a Si single crystal was used.
The dielectric film has a perovskite structure with a plane orientation of (110) (
101) (100) (001) is a mixed polycrystalline substance,
Switching operation was not possible unless a high driving voltage of 25 V was applied, and the extinction ratio was 7 dB, which was insufficient.

【0016】実施例4 図3に示すように、Si単結晶(100)基板1上にG
aAs中間層2をMBE法において基板温度500℃で
膜厚300Å形成する。膜はシンクブレンド構造で(1
00)の面方位をもつ。次に、PbTiO3誘電体層3
をスパッタリング法で基板温度530℃で膜厚3000
Å形成した。誘電体層3はペロブスカイト構造で面方位
は(001)のである。次にMOCVD法により、Zn
S:Mn(Mn0.5at%)発光層4を基板温度45
0℃で膜厚3000Å形成する。発光層4はジンクブレ
ンド構造で面方位は(100)である。さらにSi3N
4上部絶縁層5をプラズマCVD法により基板温度 2
50℃で膜厚3000Å形成した。この上部絶縁層5は
非晶質膜である。最後にITO透明導電膜6をスパッタ
リング法で基板温度250℃で膜厚2000Å形成した
。上記方法で作製したEL素子で透明電極であるITO
とSi単結晶基板との間に3KHzの周波数の交流電圧
を印加して発光の様子をITO側から観察した。このE
L素子の発光開始電圧は130Vであり、150V印加
条件で5000cd/m2の発光輝度が得られている。
Example 4 As shown in FIG. 3, G was deposited on a Si single crystal (100) substrate 1.
An aAs intermediate layer 2 is formed to a thickness of 300 Å at a substrate temperature of 500° C. using the MBE method. The membrane has a sink blend structure (1
00). Next, PbTiO3 dielectric layer 3
Using the sputtering method, the film thickness was 3000°C at a substrate temperature of 530°C.
A was formed. The dielectric layer 3 has a perovskite structure and has a (001) plane orientation. Next, by MOCVD method, Zn
S:Mn (Mn0.5 at%) light emitting layer 4 at substrate temperature 45
A film with a thickness of 3000 Å is formed at 0°C. The light emitting layer 4 has a zinc blend structure and a (100) plane orientation. Furthermore, Si3N
4 The upper insulating layer 5 is heated to the substrate temperature by plasma CVD method.
A film thickness of 3000 Å was formed at 50°C. This upper insulating layer 5 is an amorphous film. Finally, an ITO transparent conductive film 6 was formed to a thickness of 2000 Å by sputtering at a substrate temperature of 250°C. ITO, which is a transparent electrode, in the EL device produced by the above method
An alternating current voltage with a frequency of 3 KHz was applied between the substrate and the Si single crystal substrate, and the state of light emission was observed from the ITO side. This E
The light emission starting voltage of the L element was 130V, and a light emission brightness of 5000 cd/m2 was obtained under the condition of applying 150V.

【0017】比較のため、図4に示すように実施例2の
素子作製プロセスからGaAs中間層を省いた構成の素
子を作った。Si単結晶上1に直接成膜したPbTiO
3膜3は(110)(101)(100)(001)配
向を示し、多結晶体であった。次のZnS:Mn発光層
4もジンクブレンド構造で(220)と(331)配向
を持つ多結晶体であった。実施例3と同一条件での発光
実験では、この比較例の発光開始電圧は150Vであり
、ブレークダウン電圧である300V付近でも3500
cd/m2であった。実施例4と比較例1の結果を比較
すると、実施例4のほうが最大発揮度が大きく、発光開
始電圧も小さい。発光輝度が大きい第1の理由として、
実施例4の発光層の結晶性が比較例1より良好であるた
めと考えられる。そして本発明の中間層の効果により、
結晶性のよいPbTiO3膜が得られたので、結晶性の
よいZnS:M発光層が成長したためと考えられる。発
光開始電圧が小さい第1の理由として実施例4の場合P
bTiO3膜が高い誘電率が得られる(001)面配向
しているため、駆動電圧が効率的に発光層に印加したた
めと考えられる。
For comparison, as shown in FIG. 4, an element was fabricated from the element fabrication process of Example 2, except that the GaAs intermediate layer was omitted. PbTiO deposited directly on Si single crystal 1
3 Film 3 exhibited (110) (101) (100) (001) orientation and was polycrystalline. The next ZnS:Mn light-emitting layer 4 also had a zinc blend structure and was a polycrystalline material with (220) and (331) orientations. In a light emission experiment under the same conditions as Example 3, the light emission starting voltage of this comparative example was 150V, and even around the breakdown voltage of 300V, it was 3500V.
cd/m2. Comparing the results of Example 4 and Comparative Example 1, Example 4 has a higher maximum efficiency and a lower luminescence starting voltage. The first reason for the high luminance is that
This is thought to be because the crystallinity of the light-emitting layer of Example 4 was better than that of Comparative Example 1. And due to the effect of the intermediate layer of the present invention,
This is thought to be because a PbTiO3 film with good crystallinity was obtained, so a ZnS:M light-emitting layer with good crystallinity was grown. In the case of Example 4, the first reason for the low emission starting voltage is P
This is thought to be because the driving voltage was efficiently applied to the light emitting layer because the bTiO3 film was oriented in the (001) plane, which provided a high dielectric constant.

【0018】[0018]

【発明の効果】以上、説明したように、単結晶基板上に
、中間層を介することにより、結晶性よく前記誘電体膜
を成長させているので、この誘電体膜の特性を最大限に
利用した素子を作製できる。さらにこの誘電体上に他材
料の膜を積層した場合も、結晶性よく積層でき、多層の
高性能素子を作製できる。さらに、上記素子は、安価で
高品質で集積回路プロセス技術が高度に進展しているS
i、Ge又はSi1−XGe単結晶を基板に用いること
により、前記誘電体膜を用いた薄膜機能デバイスと、前
記単結晶基板を用いた電子デバイスや光検知素子との複
合化が可能となる。
[Effects of the Invention] As explained above, since the dielectric film is grown with good crystallinity on a single crystal substrate via an intermediate layer, the characteristics of this dielectric film can be utilized to the maximum. It is possible to fabricate a device with Furthermore, even when films of other materials are laminated on this dielectric, they can be laminated with good crystallinity, and a multilayer high-performance element can be produced. Furthermore, the above-mentioned elements are inexpensive, high quality, and integrated circuit process technology is highly advanced.
By using i, Ge, or Si1-XGe single crystal as a substrate, it becomes possible to combine a thin film functional device using the dielectric film with an electronic device or a photodetector using the single crystal substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】  本発明の強誘電体部材の基本構成を示す説
明図、
FIG. 1 is an explanatory diagram showing the basic configuration of the ferroelectric member of the present invention,

【図2】  実施例3の光スイッチの構成を示す説明図
FIG. 2 is an explanatory diagram showing the configuration of the optical switch of Example 3,

【図3】  実施例4のEL素子の構成を示す説明図
[Fig. 3] An explanatory diagram showing the configuration of the EL element of Example 4,

【図4】  比較例1のEL素子の構成を示す説明図
である。
FIG. 4 is an explanatory diagram showing the configuration of an EL element of Comparative Example 1.

【符号の説明】[Explanation of symbols]

1  単結晶基板 2  中間層 3  強誘電体膜 4  発光層 5  上部絶縁層 6  透明電極層 7  バッファ層 1 Single crystal substrate 2 Middle class 3 Ferroelectric film 4 Luminescent layer 5 Upper insulating layer 6 Transparent electrode layer 7 Buffer layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  Si原子あるいはGe原子のうち少な
くとも一種を有する単結晶基板上に、Pb原子を含む酸
化物強誘電体層を有する薄膜強誘電体部材において、基
板と酸化物強誘電体層との間に、結晶系が立方晶で格子
定数のずれが単結晶基板の格子定数の15%以下である
中間層を一層以上有することを特徴とする薄膜強誘電体
部材。
Claim 1: A thin film ferroelectric member having an oxide ferroelectric layer containing Pb atoms on a single crystal substrate containing at least one of Si atoms or Ge atoms, wherein the substrate and the oxide ferroelectric layer are bonded together. A thin film ferroelectric member characterized in that it has one or more intermediate layers having a cubic crystal system and a lattice constant deviation of 15% or less of the lattice constant of a single crystal substrate.
【請求項2】  中間層とPb原子を含む酸化物強誘電
体層との間に酸化物バッファ層を有することを特徴とす
る請求項1記載の薄膜強誘電体部材。
2. The thin film ferroelectric member according to claim 1, further comprising an oxide buffer layer between the intermediate layer and the oxide ferroelectric layer containing Pb atoms.
JP3065320A 1991-03-07 1991-03-07 Ferroelectric thin film member Pending JPH04279069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3065320A JPH04279069A (en) 1991-03-07 1991-03-07 Ferroelectric thin film member

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3065320A JPH04279069A (en) 1991-03-07 1991-03-07 Ferroelectric thin film member

Publications (1)

Publication Number Publication Date
JPH04279069A true JPH04279069A (en) 1992-10-05

Family

ID=13283504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3065320A Pending JPH04279069A (en) 1991-03-07 1991-03-07 Ferroelectric thin film member

Country Status (1)

Country Link
JP (1) JPH04279069A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5866238A (en) * 1994-05-05 1999-02-02 Minolta Co., Ltd. Ferroelectric thin film device and its process
JP2001196187A (en) * 2000-01-14 2001-07-19 Tdk Corp Structure for inorganic el and inorganic el element
WO2012111279A1 (en) * 2011-02-18 2012-08-23 パナソニック株式会社 Piezoelectric element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5866238A (en) * 1994-05-05 1999-02-02 Minolta Co., Ltd. Ferroelectric thin film device and its process
JP2001196187A (en) * 2000-01-14 2001-07-19 Tdk Corp Structure for inorganic el and inorganic el element
WO2012111279A1 (en) * 2011-02-18 2012-08-23 パナソニック株式会社 Piezoelectric element
US9391258B2 (en) 2011-02-18 2016-07-12 Panasonic Intellectual Property Management Co., Ltd. Piezoelectric element

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