JPH04276886A - Histogram calculation cell and histogram calculation array - Google Patents

Abstract

PURPOSE:To speed up histogram calculation and to easily prepare LSI of histogram calculation by making it possible to calculate a horizontal and a vertical histogram through one time data processing at a time in a histogram calculating array for calculating a histogram from a binarization picture element matrix. CONSTITUTION:A plurality of histrogram calculated cells 11 are arranged is parallel that includes a counter circuit 12 for inputting processed data 15 therein, counting binary data of every column, and outputting counted values, and an increment circuit 13 for inputting therein row count information 17 where binary data of every column is accumulatively added from the preceding stage, adding the binary data of every column of processed data 15 to the row count information 17 to output row count information 18, wherein the horizontal histograms are prepared by inputting processed data in every histogram calculation cell 11 at a time by counted value 16 outputted from the counter circuit 12, and wherein vertical histrograms are prepared by the row count information 18 that is accumulatively added from the first stage and that is outputted at the final stage.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a histogram calculation array for calculating a horizontal histogram and a vertical histogram from a binarized pixel matrix, used in character recognition, pattern recognition, etc., and a histogram calculation cell for configuring the array. .

0002

2. Description of the Related Art FIG. 4 is a diagram showing a conventional histogram calculation array. In the figure, 41 to 48 are counter circuits, 49 is a sequencer circuit, and 50 is a pixel matrix horizontal/vertical conversion circuit.

A conventional histogram calculation array has a structure in which counter circuits 41 to 48 are arranged in parallel. When each counter circuit receives processing data in which a predetermined number of consecutive binary data of "1" and "0" are input, it counts the frequency of "1" and outputs it as a count value.

FIG. 5 is a diagram showing an example of conventional histogram calculation. The operation of the conventional histogram calculation array shown in FIG. 4 will be explained with reference to the same figure. As an example of a binarized pixel matrix, the 8 rows by 8 columns shown in FIG. 5(a) is used. Of each pixel, the one with diagonal lines is “1”
, and those with a white background correspond to "0". The conventional histogram calculation array performs horizontal histogram calculation and vertical histogram calculation in two steps, as described below.

(1) Horizontal histogram calculation mode Under the control of the sequencer circuit 49, each row of the binarized pixel matrix shown in FIG. 5A is input to each counter circuit as one piece of processing data. That is, the first row of the binarized pixel matrix is input to the counter circuit 41 as processed data 1, the second row is inputted to the counter circuit 42 as processed data 2, and the third row is inputted to the counter circuit 43 as processed data 3. The fourth line is inputted as processed data 4 to the counter circuit 44, and the fifth line is inputted as processed data 5 to the counter circuit 45.
and input the 6th line to the counter circuit 4 as processing data 6.
6, the seventh line is inputted as processed data 7 to the counter circuit 47, and the eighth line is inputted as processed data 8 to the counter circuit 48.

Each counter circuit counts the number of "1"s in the input processing data and outputs it as a horizontal count value. Taking the first row as an example, the binarized data in the first row is "01001000", so the counter circuit 4
1 outputs "2" as the horizontal count value. Similarly, the counter circuit 42 outputs a horizontal count value "3", the counter circuit 43 outputs a horizontal count value "4",
The counter circuit 44 outputs the horizontal count value "6", the counter circuit 45 outputs the horizontal count value "6", the counter circuit 46 outputs the horizontal count value "4", and the counter circuit 47 outputs the horizontal count value "4". The counter circuit 48 outputs a horizontal count value of "2".

When the horizontal count values of the first to eighth rows of the binarized pixel matrix output by the counter circuits 41 to 48 are arranged, they are "2, 3, 4, 6, 6, 4, 3, 2". This is the horizontal histogram.

(2) Vertical histogram calculation mode After the horizontal histogram calculation is completed, the pixel matrix horizontal/
The vertical conversion circuit 50 rotates the binarized pixel matrix shown in FIG. 5(a) by 90 degrees. As a result, Figure 5 (b
) is obtained. (To avoid confusion, “*” has been added in the figure.)

Under the control of the sequencer circuit 49, each row of the binarized pixel matrix shown in FIG. 5(b) is input to each counter circuit as one piece of processing data. That is, the first row of the binarized pixel matrix is inputted as processed data 1 to the counter circuit 41, the second row is inputted as processed data 2 to the counter circuit 42, and the third row is inputted as processed data 3 to the counter circuit 43.
and input the fourth line to the counter circuit 4 as processing data 4.
4, input the fifth line as processed data 5 to the counter circuit 45, input the sixth line as processed data 6 to the counter circuit 46, input the seventh line as processed data 7 to the counter circuit 47, The eighth row is input to the counter circuit 48 as processed data 8.

Each counter circuit counts the number of "1"s in the input processing data and outputs it as a vertical count value. Taking the first row as an example, the binarized data in the first row is "00011000", so the counter circuit 4
1 outputs "2" as the vertical count value. Similarly, the counter circuit 42 outputs a vertical count value "4", the counter circuit 43 outputs a vertical count value "0",
The counter circuit 44 outputs the vertical count value "8", the counter circuit 45 outputs the vertical count value "4", the counter circuit 46 outputs the vertical count value "4", and the counter circuit 47 outputs the horizontal count value "4". 6", and the counter circuit 48 outputs a horizontal count value of "2".

When the vertical count values of the first to eighth rows of the binarized pixel matrix output by the counter circuits 41 to 48 are arranged, they are "2, 4, 0, 8, 4, 4, 6, 2". This is the vertical histogram.

0012

[Problems to be Solved by the Invention] A conventional histogram calculation array is configured to calculate the horizontal histogram and the vertical histogram in two separate modes under the control of the sequencer circuit 49. It had been. As a result, the following problems occurred.

(1) Since the histogram calculation is divided into two times, a horizontal histogram calculation mode and a vertical histogram calculation mode, it is necessary to activate the sequencer circuit 49 twice. For this reason, the histogram creation speed is restricted, and the required speed cannot be obtained.

(2) Since the circuit scale of the counter circuit controlled by the sequencer circuit 49 and the pixel matrix horizontal/vertical conversion circuit 50 is large, it is difficult to incorporate them into an LSI.

[0015] The present invention solves these problems and provides two
To realize a histogram calculation array that can simultaneously calculate a horizontal histogram and a vertical histogram from a valued pixel matrix in one data process, and to provide a histogram calculation cell that is a constituent unit of the histogram calculation array and is easily integrated into an LSI. The purpose is to

[0016]

[Means for Solving the Problems] In order to achieve the above object, the histogram calculation cell according to the present invention inputs one row of processed data, counts the binary data in each column, and calculates the count value. The output counter circuit and the row count information in which binary data is cumulatively added for each column are input from the previous stage, and the binary data for each column of the processed data for one row is added to the row count information of the previous stage. and an increment circuit that outputs row count information.

The histogram calculation array according to the present invention comprises:
A histogram calculation array for creating a horizontal histogram and a vertical histogram of a binary pixel matrix of m rows and n columns [m, n are positive integers], in which m pieces of histogram calculation cells according to the present invention are arranged in parallel, The lines are connected so that the row count information output from the previous stage increment circuit is input to the next stage increment circuit, and the horizontal histogram is created by simultaneously inputting one row of processed data consisting of n pieces of binary data to each histogram calculation cell. The counter circuit in each histogram calculation cell counts and outputs the binary data of each column.The vertical histogram is created using m count values for each column that are cumulatively added from the first stage.
It is configured to be created using row count information output from the m-th stage.

FIG. 1 is a diagram showing the principle of the present invention. FIG. 5A shows a histogram calculation circuit, and FIG. 1B shows an example of histogram calculation.

In FIG. 1(a), 11 is a histogram calculation cell, 12 is a counter circuit, 13 is an increment circuit, 14 is a clock signal, 15 is processing data, 16 is a count value, 17 is a row count information input, and 18 is a Shows row count information output.

The histogram calculation cell 11 is configured to include a counter circuit 12 and an increment circuit 13.

The counter circuit 12 counts the binary data of each column of the input processed data 15 for one row and outputs a count value 16.

The increment circuit 13 has two increment circuits for each column.
The row count information 17 in which the value data has been cumulatively added is input from the previous stage, and the binary data for each column of the processed data 15 for one row is added to the row count information 17 in the previous stage, and the row count information 18 is output. do.

[0023]

[Operation] The operation of the histogram calculation cell 11 shown in FIG. 1(a) will be explained using the example of histogram calculation shown in FIG. 1(b).

FIG. 1B shows a state in which calculation is being performed on the third row of a binary pixel matrix of 8 rows by 8 columns. The shaded area in the binarized pixel matrix is the binary data “
1", and the white portion corresponds to binary data "0".

[0025] The third line is “0, 1, 0, 0, 1, 0, 0
, 0". This is input to the counter circuit 12 as processed data 3 (15). The counter circuit 12 counts the frequency of "1" in the input processed data 3 (15), and The result "2" is output as the count value 16.

On the other hand, the increment circuit 13 receives row count information from the previous stage. In the example of Figure 1(b),
“1” in the first row and “1” in the second row are added for each column from the first column to the eighth column, “1, 1, 0, 1, 2, 2,”
0, 1'' becomes the row count information input 17.The increment circuit 13 receives the row count information input 17 ``1, 1, 0''.
, 1, 2, 2, 0, 1", processing data 3 (15) "0
, 1, 0, 0, 1, 0, 0, 0" for each column to calculate row count information "1, 2, 0, 1, 3, 2, 0, 1", and 18.A histogram calculation array is constructed by arranging a large number of histogram calculation cells 11 in parallel.Specifically, it is constructed as follows.

[0027] Where m and n are positive integers, 2
The histogram calculation array that creates the horizontal histogram and vertical histogram of the valued pixel matrix has m histogram calculation cells 11 arranged in parallel, and the row count information 17 output from the previous stage increment circuit is input to the next stage increment circuit 13. It is configured by connecting the wires as follows.

The histogram calculation array configured in this manner creates a horizontal histogram and a vertical histogram in the following manner.

The horizontal histogram is created by simultaneously inputting one row of processed data 15 consisting of n pieces of binary data into each histogram calculation cell 11.
The counter circuit 12 in
It is created by counting and outputting m count values 16.

The vertical histogram is composed of n pieces of binary data for each column cumulatively added from the first stage, and is created using the row count information 18 output from the m-th stage.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a diagram showing an example of the configuration of a histogram calculation array according to the present invention. In the same figure, 21 is histogram calculation cell #1 [hereinafter referred to as cell #1], 21
a is a counter circuit, 21b is an increment circuit, 22
is cell #2, 22a is a counter circuit, 23b is an increment circuit, 23 is cell #3, 23a is a counter circuit,
23b is an increment circuit, 28 is cell #8, 28a
The counter circuit 28b is an increment circuit.

The histogram calculation array of the present invention has a structure in which cells #1 (21) to #8 (28) are arranged in parallel. When each cell receives processed data in which a predetermined number of consecutive binary data of "1" and "0" are input, the counter circuit counts the frequency of "1" and outputs it as a horizontal count value. At the same time, the increment circuit inputs the row count information in which binary data is cumulatively added for each column from the previous stage, and adds the binary data for each column of the processed data for one row to this row count information from the previous stage. to output line count information.

FIG. 3 is a diagram showing an example of histogram calculation according to the present invention. The operation of the histogram calculation array of the present invention shown in FIG. 2 will be explained with reference to the same figure. As an example of the binarized pixel matrix, the 8 rows by 8 columns shown in FIG. 3 is used. Of each pixel, those with diagonal lines are “
The histogram calculation array of the present invention calculates the horizontal histogram and the vertical histogram in one data process, but this avoids confusion. For this purpose, horizontal histogram calculation and vertical histogram calculation will be explained separately.

(1) Calculation of horizontal histogram Each row of the binarized pixel matrix shown in FIG. 3 is input to each cell as one piece of processing data. That is, the first row of the binarized pixel matrix is input as processed data 1 to cell #1 (21), the second row is inputted as processed data 2 to cell #2 (22), and the third row is inputted as processed data. 3 into cell #3 (23), input the fourth row into cell #4 as processing data 4,
Input the 5th row as processing data 5 to cell #5, input the 6th row to cell #6 as processing data 6, input the 7th row to cell #7 as processing data 7, and process the 8th row. Input as data 8 to cell #8 (28). [Although not shown, cells #4 to #7 have the same circuit configuration as the other cells. ]

Each cell counts the number of "1"s in the input processing data using a built-in counter circuit and outputs it as a horizontal count value. Taking the first row as an example, the binarized data in the first row is "01001000", so the counter circuit 21a calculates "2", and cell #1 (21) calculates "2" as the horizontal count value. ” is output. Similarly, cell #2 (22) has a horizontal count value “
3", and cell #3 (23) outputs the horizontal count value "4".
”, cell #4 outputs the horizontal count value “6”, cell #5 outputs the horizontal count value “6”, and cell #6 outputs the horizontal count value “6”.
outputs a horizontal count value "4", cell #7 outputs a horizontal count value "3", and cell #8 (28) outputs a horizontal count value "2".

When the horizontal count values of the first to eighth rows of the binarized pixel matrix output by cells #1 (21) to #8 (28) are arranged, they are "2, 3, 4, 6, 6,4,3
, 2''. This is the horizontal histogram.

(2) Vertical histogram calculation The increment circuit built into each cell calculates the row count information output from the previous cell in parallel with the counter circuit calculating the horizontal count value of the input processing data. is input, "1" for each column of processing data is cumulatively added to this to create row count information, and the row count information is output to the next cell.

Since cell #1 (21) is the first stage, the input of the increment circuit 21b is grounded. Therefore, the row count information at the previous stage of the increment circuit 21b becomes "0, 0, 0, 0, 0, 0, 0, 0". The increment circuit 21b receives this row count information “0”.
,0,0,0,0,0,0,0" and processing data 1"0,
1, 0, 0, 1, 0, 0, 0" for each column to calculate the row count information "0, 1, 1, 0, 0, 1, 0, 0", and use it as the row count information. Output.

Cell #2 (22) stores the row count information “0, 1, 0, 0, 1, 0, 0” output by cell #1 (21).
, 0", and input this row count information and processing data 2"
0, 0, 1, 0, 1, 0, 1, 0” for each column to generate row count information “0, 1, 1, 0, 2, 0, 1, 0”
is calculated and output as row count information.

Cell #3 (23) stores the row count information “0, 1, 1, 0, 2, 0, 1” output by cell #2 (22).
, 0", and input this row count information and processing data 3"
1, 1, 0, 1, 1, 0, 0, 0" for each column to generate row count information "1, 2, 1, 1, 3, 0, 1, 0"
is calculated and output as row count information.

Cell #4 inputs the row count information "1, 2, 1, 1, 3, 0, 1, 0" outputted by cell #3 (23), and uses this row count information and processing data 4 " 0,1,
1, 1, 1, 0, 1, 1" for each column to calculate row count information "1, 3, 2, 2, 4, 0, 2, 1" and output it as row count information. .

Cell #5 inputs the row count information “1, 3, 2, 2, 4, 0, 2, 1” output by cell #4,
This row count information and processing data 5 “0, 1, 1, 1,
1, 0, 1, 1" are added for each column to calculate row count information "1, 4, 3, 3, 5, 0, 3, 2" and output as row count information.

Cell #6 inputs the row count information “1, 4, 3, 3, 5, 0, 3, 2” output by cell #5,
This row count information and processing data 6 “1, 1, 0, 1,
1, 0, 0, 0" for each column to calculate row count information "2, 5, 3, 4, 6, 0, 3, 2" and output as row count information.

Cell #7 inputs the row count information “2, 5, 3, 4, 6, 0, 3, 2” output by cell #6,
This row count information and processing data 7 “0, 0, 1, 0,
1, 0, 1, 0" for each column to calculate row count information "2, 5, 4, 4, 7, 0, 4, 2" and output as row count information.

Cell #8 (28) inputs the row count information "2, 5, 4, 4, 7, 0, 4, 2" output from cell #7, and uses this row count information and processing data 8 " 0,1,
0, 0, 1, 0, 0, 0" for each column to calculate row count information "2, 6, 4, 4, 8, 0, 4, 2" and output it as row count information. .

The row count information "2, 6, 4, 4, 8, 0, 4, 2" output by cell #8 (28) at the final stage forms a vertical histogram as it is.

Above, an example of creating a horizontal histogram and a vertical histogram of a binarized pixel matrix of 8 rows x 8 columns was shown, but the histogram calculation array of the present invention
, n are arbitrary positive integers, and can be applied to create a horizontal histogram and a vertical histogram of a binary pixel matrix of m rows by n columns. In this case, the histogram calculation array is constructed by arranging m histogram calculation cells in parallel and connecting them so that the row count information output from the previous stage increment circuit is input to the next stage increment circuit.

[0048]

According to the histogram calculation array of the present invention, a horizontal histogram and a vertical histogram can be calculated simultaneously from a binarized pixel matrix of any size by one data processing. Therefore, it is possible to speed up histogram calculation.

Furthermore, since the histogram calculation array of the present invention has a histogram calculation cell as a constituent unit and has a configuration in which a plurality of histogram calculation cells are arranged in parallel, it can easily be used even when the pixel width of the binarized pixel matrix is expanded. I can handle it. moreover,
It can be easily integrated into LSI.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the invention.

FIG. 2 is a diagram showing an example of the configuration of a histogram calculation array according to the present invention.

FIG. 3 is a diagram showing an example of calculating a histogram according to the present invention.

FIG. 4 shows a conventional histogram calculation array.

FIG. 5 is a diagram showing an example of conventional histogram calculation.

[Explanation of symbols]

11 Histogram calculation cell 12 Counter circuit 13 Increment circuit 14 Clock 15 Processing data 16 Count value 17　Line count information input 18 Row count information output

Claims (2)

[Claims] [Claim 1] A counter circuit that inputs one row of processed data, counts binary data in each column, and outputs a count value, and a counter circuit that outputs a count value by inputting one row of processed data, and a counter circuit that receives row count information in which the binary data is cumulatively added for each column. A histogram calculation cell characterized in that it includes an increment circuit that inputs from a previous stage, adds binary data for each column of processed data for one row to row count information of the previous stage, and outputs row count information. [Claim 2] 2 of m rows x n columns [m and n are positive integers]
a histogram calculation array for creating horizontal and vertical histograms of a valued pixel matrix, the array comprising:
m pieces of histogram calculation cells according to claim 1 are arranged in parallel and connected so that the row count information output from the increment circuit at the previous stage is inputted to the increment circuit at the next stage,
In the horizontal histogram, one row of processed data consisting of n pieces of binary data is simultaneously input to each histogram calculation cell, and a counter circuit in each histogram calculation cell counts and outputs the binary data of each column. The vertical histogram is created using m count values, and the vertical histogram consists of n binary data for each column cumulatively added from the first stage, and is created using row count information output from the m-th stage. Histogram calculation array.