JPH04276660A - Formation method of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten a development period when two kinds of nonvolatile memory circuits are changed and to reduce the number of production processes in a semiconductor integrated circuit device where the two kinds of nonvolatile memory circuits are mounted on the same substrate. CONSTITUTION:At the formation method of a semiconductor integrated circuit device 20, an EPROM version where an EPROM 23 for a memory cell Qme of two-layer gate structure and an EPROM 25, whose memory capacity is small, for a memory cell Qie of one-layer gate structure are mounted on a semiconductor substrate 1 is developed, and a mask ROM version where a mask ROM 26 for a memory cell Qmm of one-layer gate structure instead of said EPROM 23 and an EPROM 25 which is substantially the same as said EPROM are mounted on the semiconductor substrate 1 is developed.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular to a technique that is effective when applied to a semiconductor integrated circuit device in which two types of nonvolatile memory circuits for different purposes are mounted on the same substrate. .

0002

[Prior Art] Semiconductor integrated circuit devices (A
As SIC), multiple types of ultraviolet erasable nonvolatile memory circuits (Erasable Program
Microprocessors equipped with mable read only memory (hereinafter referred to as EPROM) have been developed. Specifically, the microprocessor is, for example, 1
It is equipped with an EPROM that has a relatively large storage capacity of 6 to 64 Kbytes and is used for storing programs. Further, in addition to the above-mentioned EPROM, the microprocessor is equipped with an EPROM having a relatively small storage capacity of several to several tens of kilobytes and used for trimming internal functions (changing programs) and the like.

[0003] In the EPROM having a large storage capacity, a memory cell is constructed of a field effect transistor having a two-layer gate structure, that is, a control gate electrode (control gate electrode) is laminated on a charge storage gate electrode (floating gate electrode). In EPROM, when the memory cell is composed of a field effect transistor that adopts a single-layer gate structure,
The control gate electrode is arranged in a different region from the charge storage gate electrode, increasing the memory cell area. This kind of EPRO
Compared to M, EPROM whose memory cells are field-effect transistors that adopt a two-layer gate structure can reduce the memory cell area and achieve higher integration (larger capacity).
.

The field effect transistor employing the above-mentioned two-layer gate structure is formed by the following manufacturing process.

First, a gate insulating film is formed on the main surface of a semiconductor substrate within an active region surrounded by an element isolation insulating film.

Next, a first layer of gate material, such as a polycrystalline silicon film, is deposited over the entire surface of the substrate covering the gate insulating film. Thereafter, the first layer gate material is patterned for the first time in order to define the gate width of the charge storage gate electrode of the field effect transistor. This patterning is performed by RIE in order to achieve miniaturization.

Next, a gate insulating film is formed on the surface of the first layer of gate material. The gate insulating film is formed of a silicon oxide film obtained by oxidizing the surface of a polycrystalline silicon film using, for example, a thermal oxidation method.

Next, a second layer gate material, such as a polycrystalline silicon film, is deposited on the entire surface of the substrate with a gate insulating film interposed on the surface of the first layer gate material. After this, in order to define the gate lengths of the charge storage gate electrode and the control gate electrode of the field effect transistor, the second layer gate material and the first layer gate material are subjected to a second patterning, that is, overlapping, respectively. Make the cut. This patterning is performed by RIE similarly to the first patterning. When patterning is completed, a charge storage gate electrode is formed using the first layer gate material, and a control gate electrode is formed using the second layer gate material.

Next, using the charge storage gate electrode and the control gate electrode as an impurity introduction mask, n-type impurities are introduced into the main surface of the active region of the semiconductor substrate to form a source region and a drain region.

The field effect transistor formed in this manner adopts a two-layer gate structure, and the charge storage gate electrode and the control gate electrode are cut in layers in the manufacturing process, so that microfabrication can be performed and the memory cell area can be reduced. can be reduced.

Furthermore, the EPROM with a small storage capacity is constructed with the same structure as the memory cell of the EPROM with a large storage capacity, for the purpose of reducing the number of steps in the manufacturing process of a semiconductor integrated circuit device.

[0012] Regarding EPROM, for example, ISSCC, 1987, pages 70 and 71 (ISSCC87/Wednesday, F
ebruary 25, 1987, p. 70-71).

[0013]

[Problem to be Solved by the Invention] The present inventor has discovered the above-mentioned E.
We found the following problems with microprocessors equipped with PROM.

In the early stages of development, the aforementioned microprocessor is equipped with an EPROM as a large-capacity storage circuit, but when mass production begins, the large-capacity storage circuit is replaced with an EPROM and read-only type in order to reduce manufacturing costs. Non-volatile memory circuit, ie mask ROM (Read
Only Memory) is installed. In other words, the development of microprocessors progresses from the EPROM version in the early stages of development to the mask ROM version at the pace of mass production. Mask ROM
In this case, a memory cell is configured with a field effect transistor that uses a single-layer gate structure, which requires one less layer of gate material than a field-effect transistor that uses a two-layer gate structure. With this change to the mask ROM version, in order to reduce the number of steps in the manufacturing process, we decided to use EPRO, which has a smaller storage capacity.
Since there is not much need for high integration in M, a field effect transistor employing a single-layer gate structure is used as a memory cell, and a new development is being carried out. For this reason, when developing the EPROM version of the microprocessor, we designed and developed two types of EPROMs with different storage capacities, and when developing the mask ROM version, we designed and developed the mask ROM and created a new EPROM with a smaller storage capacity. Since it is necessary to design and develop two types of memory circuits for a total of four types of memory circuits, the development period becomes long.

Furthermore, as the development period for this microprocessor becomes longer, the development cost increases.

[0016] Furthermore, the above-mentioned microprocessor is based on EP
When changing from a ROM version to a mask ROM version, change the EPROM with a large storage capacity to a mask ROM (change from a two-layer gate structure to a one-layer gate structure), and do not change the EPROM with a small storage capacity (change from a two-layer gate structure to a one-layer gate structure). It is conceivable to continue developing the two-layer gate structure. However, although the field effect transistor, which is a memory cell, can be configured with a single-layer gate structure in a mask ROM, a two-layer gate structure is adopted in an EPROM with a small storage capacity, so a two-layer gate material is required in the manufacturing process. A forming process is required. Therefore, the number of steps in the microprocessor manufacturing process increases.

[0017] Furthermore, the above-mentioned microprocessor is based on EP
When changing from ROM version to mask ROM version, mask R
It is conceivable to configure the OM memory cell with a field effect transistor that employs a two-layer gate structure (the upper layer gate electrode is used as a dummy gate electrode), and to develop it without changing the EPROM, which has a small storage capacity. However, as described above, the microprocessor requires a step of forming two layers of gate materials in the manufacturing process, which increases the number of steps in the manufacturing process.

[0018] Furthermore, in the above-mentioned microprocessor, when both the EPROM or mask ROM with a large storage capacity and the EPROM with a small storage capacity are composed of field effect transistors adopting a two-layer gate structure, In the second patterning, that is, the overlapping cutting step, the gate material of the first layer is patterned the first time, so the etching area is small. In RIE, the end point of the etching time is detected based on the amount of change in the reactive gas generated during etching, so if the etching area is small, the amount of reactive gas generated is small, making it difficult to detect the end point of the etching time. In practice, to detect the end point of etching time, the etching area is approximately 5% of the total area of the semiconductor wafer.
[%] or more is required. For this reason, in the microprocessor, the etching controllability during the manufacturing process deteriorates, and the yield in the manufacturing process decreases.

An object of the present invention is to provide a semiconductor integrated circuit device in which two types of nonvolatile memory circuits are mounted on the same substrate.
It is an object of the present invention to provide a technique that can shorten the development period when changing the nonvolatile memory circuit.

Another object of the present invention is to shorten the development period when changing the nonvolatile memory circuit in a semiconductor integrated circuit device in which two types of nonvolatile memory circuits are mounted on the same substrate, and to reduce the manufacturing process. The objective is to provide technology that can reduce the number of steps.

Another object of the present invention is to provide a technique that can improve the yield in the manufacturing process in a semiconductor integrated circuit device in which two types of nonvolatile memory circuits are mounted on the same substrate.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0023]

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

(1) In a method for forming a semiconductor integrated circuit device in which two types of nonvolatile memory circuits with different storage capacities are mounted on the same substrate, a field effect transistor adopting a two-layer gate structure is mounted on the first substrate as a memory cell. A first nonvolatile memory circuit of an ultraviolet erasable type or an electrically erasable type, whose memory cells are field effect transistors adopting a single-layer gate structure, and whose storage capacity is smaller than that of the first nonvolatile memory circuit; a first step in which a second non-volatile memory circuit of an ultraviolet erasable type or an electrically erasable type is mounted, and a single-layer gate is mounted on a second substrate different from the first substrate in place of the first non-volatile memory circuit; a read-only third non-volatile memory circuit whose memory cells are field-effect transistors employing this structure; It comprises a stage.

(2) The third nonvolatile memory circuit mounted on the second stage semiconductor integrated circuit device of the means (1) has a plurality of memory cells connected in series between the data line and the source line. It has a vertical structure in which memory cell columns are arranged, or a horizontal structure in which memory cells are connected in parallel between data lines and source lines.

[0026]

[Operation] According to the above-mentioned means (1), in the first stage semiconductor integrated circuit device, the first nonvolatile memory circuit adopts a two-layer gate structure in which a control gate electrode is laminated on a charge storage gate electrode. Since the field effect transistor is used as the memory cell, the memory cell area can be reduced and the capacity can be increased. When developing a semiconductor integrated circuit device from the first stage to the second stage (when developing a mask ROM version), a field effect transistor that adopts a single-layer gate structure is used as a memory cell instead of the first nonvolatile memory circuit. Since the gate structure of the memory cell is made into a single layer together with the memory cell of the second nonvolatile memory circuit, the number of steps in the manufacturing process can be reduced and the semiconductor integrated circuit device can be improved. In addition to shortening the development period, the second non-volatile memory circuit installed in the first stage can be installed as is in the second stage, and the semiconductor The development period for integrated circuit devices can be shortened.

Further, in the semiconductor integrated circuit device of the second stage, each of the memory cells of the third nonvolatile memory circuit and the second nonvolatile memory circuit is constituted by a field effect transistor adopting a single-layer gate structure, and the manufacturing process is as follows. During the process, the etching area during gate electrode patterning is increased,
Since the end point of the etching time can be reliably detected, the yield in the manufacturing process can be improved, and since the memory cells of the third nonvolatile memory circuit occupy a smaller area than the memory cells of the first nonvolatile memory circuit, it is possible to You can improve your degree.

Furthermore, in the semiconductor integrated circuit device of the second stage, development costs can be reduced by reducing the number of steps in the manufacturing process based on the single-layer gate structure of the memory cell and by shortening the development period.

According to the above-mentioned means (2), the vertically structured memory cells of the third nonvolatile memory circuit are connected to each of the data line and the source line for each of the plurality of memory cells (for each memory cell column). Since the number of connections with wiring can be reduced and the degree of integration can be improved, the horizontal structure memory cell has a gate width of the charge storage gate electrode of the field effect transistor which is the memory cell of the first nonvolatile memory circuit. Since the area of the isolation region between memory cells can be reduced by an amount corresponding to the distance between the directions, the degree of integration can be improved.

[0030] The configuration of the present invention will be explained below.
The present invention will be described along with an embodiment in which the present invention is applied when changing a semiconductor integrated circuit device equipped with a vertical structure (NAND structure) mask ROM to a semiconductor integrated circuit device equipped with a mask ROM having a vertical structure (NAND structure).

In all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[0032]

Embodiment FIG. 1 (layout diagram) shows the configuration of a microprocessor (EPROM version) which is an embodiment of the present invention.

As shown in FIG. 1, a microprocessor (semiconductor integrated circuit device) 20 in the early stage of development had a C in the center.
PU22, EPROM23, interrupt controller circuit (
Interrupt) 24 and variable peripherals (Intel
ligent Sub Processor) 25. The peripheral part of the microprocessor 20 has I/O
Port 21 is installed.

EPROM of the microprocessor 20
23 is used for storing programs, for example 16
It has a relatively large storage capacity of ~64 [Kbytes].

The variable peripheral 25 includes a timer, an A/D
Built-in converter, etc., allows users to change programs, etc.
It is equipped with an EPROM that trims internal functions. This EPROM has a relatively small storage capacity of several to several tens of kilobytes.

When the microprocessor 20 configured as described above is mass-produced, a mask ROM 26 is installed in place of the EPROM 23, as shown in FIG. 2 (layout diagram of a mask ROM version). E of variable peripheral 25
The PROM is equipped with the same microprocessor 20 as the EPROM version.

Next, the EP of the microprocessor 20
The cross-sectional structures and manufacturing processes of the ROM version and the mask ROM version will be explained.

<EPROM version> Microprocessor 20
As shown in Figure 3 (cross-sectional view of main parts), the EPROM version of
It is basically composed of a p-type semiconductor substrate 1 made of single crystal silicon. In the formation region of the n-channel field effect transistor, a p-type well region 2 is formed on the main surface of the p--type semiconductor substrate 1. Although not shown, in the formation region of the p-channel field effect transistor,
An n-type well region is formed on the main surface of the p--type semiconductor substrate 1.

EPROM 23 of microprocessor 20
As shown on the right side of FIG. 3, the memory cell Qme, the write system MISFET Qmw, and the read system MISFET Qmr
have each of the following.

The memory cell Qme is formed on the main surface of the p-type well region 2 within a region defined and surrounded by the element isolation insulating film 3. In other words, memory cell Qm
e is mainly composed of a channel forming region (p-type well region 2), gate insulating films 4 and 6, a charge storage gate electrode 5, a control gate electrode 7, and a pair of n + type semiconductor regions 9 which are a source region and a drain region. be done.

The gate insulating film 4 is formed of a silicon oxide film obtained by oxidizing the main surface of the p-type well region 2. The gate insulating film 6 is formed of a silicon oxide film obtained by oxidizing the surface of the charge storage gate electrode (polycrystalline silicon film) 5.

The charge storage gate electrode 5 is formed in the first layer gate material forming step during the manufacturing process, and is made of, for example, a polycrystalline silicon film. The control gate electrode 7 is formed in the second layer gate material forming step during the manufacturing process, and is made of, for example, a polycrystalline silicon film. charge storage gate electrode 5,
Any of the control gate electrodes 7 may be constructed of another gate material, for example, a laminated gate material formed of a polycrystalline silicon film and a high melting point metal silicide film laminated thereon.

This memory cell Qme is constituted by a field effect transistor adopting a two-layer gate structure, and the n+ type semiconductor region 9 corresponding to the drain region is connected to the data line 12.
connected to. Data line 12 extends on the surface of interlayer insulating film 10 and is connected to n + -type semiconductor region 9 through a connection hole formed in interlayer insulating film 10 . data line 1
2 is formed in the first layer wiring forming step during the manufacturing process, and is formed of, for example, an aluminum alloy film.

An interlayer insulating film 1 is formed on the upper layer of this data line 12.
A wiring 14 extends through the wiring 3, and the wiring 14 is formed in a second layer wiring formation step during the manufacturing process, and is made of, for example, an aluminum alloy film. A final protective film 15 is formed on the wiring 14.

The write system MISFET Qmw is mainly composed of a channel forming region, a gate insulating film 4, a gate electrode 5, and a pair of n+ type semiconductor regions 9 which are a source region and a drain region. The gate electrode 5 of this writing system MISFETQmw is formed of the first layer gate material. Also,
Since a high voltage is applied to the gate insulating film 4 when writing information to the memory cell Qme, the gate insulating film 4 is connected to the readout system MISFET Qm.
It is formed with a thicker film thickness than the gate insulating film 6 of r.

The readout MISFET Qmr is mainly composed of a channel forming region, a gate insulating film 6, a gate electrode 7, and a pair of n+ type semiconductor regions 9, which are a source region and a drain region. The gate electrode 7 of this readout MISFET Qmr is formed of a second layer gate material.

The write system MISFETQmw and the read system MISFETQmr may both be formed of a first layer gate material or a second layer gate material. In this case, the gate insulating film of the write system MISFETQmw is formed thicker than the gate insulating film of the read system MISFETQmr.

Variable peripheral 25 of microprocessor 20
As shown on the left side of Figure 3, the EPROM installed in
It includes a memory cell Qie, a write system MISFET Qiw, and a read system MISFET Qir.

The memory cell Qie is formed on the main surface of the p-type well region 2 in a region defined and surrounded by the element isolation insulating film 3 . In other words, memory cell Qm
e represents a channel forming region (p-type well region 2), a gate insulating film 6, a charge storage gate electrode 7, a control gate electrode 8,
Although not shown, it is mainly composed of a pair of n+ type semiconductor regions 9, which are a source region and a drain region. The charge storage gate electrode 7 is formed of a second layer gate material, and the control gate electrode 8 is formed of an n+ type semiconductor region. In other words, the memory cell Qie is constituted by a field effect transistor that employs a single layer gate structure using only the second layer gate material.

The write system MISFET Qiw is mainly composed of a channel forming region, a gate insulating film 6, a gate electrode 7, and a pair of n+ type semiconductor regions 9 which are a source region and a drain region. The gate electrode 7 of this writing system MISFET Qiw is formed of the second layer gate material.

The readout MISFET Qir is mainly composed of a channel forming region, a gate insulating film 6, a gate electrode 7, and a pair of n+ type semiconductor regions 9 which are a source region and a drain region. The gate electrode 7 of this readout MISFET Qir is formed of a second layer gate material.

In other words, the EP mounted on the variable peripheral 25
ROM memory cell Qie, write system MISFET Qi
w, each of the readout MISFET Qir is composed of one type of charge storage gate electrode 7 and gate electrode 7 formed of the second layer gate material. Also, basically, the memory cell Qie, the write system MISFET Qiw, the read system M
Each ISFETQir may be formed using the first layer gate material.

Next, a method for manufacturing the above-mentioned microprocessor 20 will be briefly explained using FIGS. 4 to 8 (cross-sectional views of main parts shown for each manufacturing process).

First, the element isolation insulating film 3 is formed on the main surface of the inactive region of the p-type well region 2 of the p--type semiconductor substrate 1.

Next, as shown in FIG. 4, the variable peripheral 25
A control gate electrode 8 is formed in the memory cell Qie region of the EPROM. As shown in FIG. 4, the control gate electrode 8 is formed by introducing an n-type impurity, for example, As or P, using an ion implantation method using an impurity introduction mask 16 formed by photolithography. Ru.

Next, the memory cell Qme of the EPROM 23
, in each area of the writing system MISFETQmw,
A gate insulating film 4 is formed. Thereafter, as shown in FIG. 5, a charge storage gate electrode 5 is formed in the region of the memory cell Qme, and a gate electrode 5 is formed in the region of the write system MISFET Qmw. Each of the charge storage gate electrode 5 and the gate electrode 5 is formed of the first layer gate material. Each of the charge storage gate electrode 5 and the gate electrode 5 has a first
patterned by the second patterning process,
The charge storage gate electrode 5 is patterned to define the gate width of the field effect transistor.

Further, this patterning step is performed, for example, by RIE in order to achieve miniaturization. In this patterning step, the entire region of the memory cell Qie of the EPROM of the variable peripheral 25 is etched after the first layer gate material is deposited.

Next, the memory cell Qme of the EPROM 23
, readout MISFETQmr, EP of variable peripheral 25
ROM memory cell Qie, write system MISFET Qi
w. A gate insulating film 6 is formed in each region of the readout MISFET Qir.

Next, as shown in FIG. 6, memory cell Qm
In the region e, the control gate electrode 7 and the readout system MISF
ETQmr, EPROM memory cell Qie of variable peripheral 25, write system MISFETQiw, read system MIS
A gate electrode 7 is formed in each region of FET Qir. Each of the control gate electrode 7 and the gate electrode 7 is formed of the second layer gate material. The gate electrode 7 is patterned in the second patterning process, and the control gate electrode 7 is basically not patterned and remains over almost the entire area of the memory cell array.

[0060] Also, this patterning step is performed by RIE as described above.

Next, the memory cell Qme of the EPROM 23
In the region, the control gate electrode 7 and the charge storage gate electrode 7 are each patterned for the third time, and the charge storage gate electrode 5 and the control gate electrode 7 are completed as shown in FIG. This patterning is so-called overlapping cutting performed by RIE, and mainly defines the gate length direction of the field effect transistor.

Next, as shown in FIG. 8, memory cell Qm
e, writing system MISFETQmw, reading system MISFE
TQmr, memory cell Qie, write system MISFETQ
iw, n+ used as the source region and drain region in each region of the readout MISFET Qir
A type semiconductor region 9 is formed. This n+ type semiconductor region 9 is formed using, for example, an ion implantation method.

Also, by the process of forming this n+ type semiconductor region 9, the memory cell Qme of the EPROM 23, the write system MISFETQmw, and the read system MISFETQm
r, memory cell Qie of EPROM of variable peripheral 25;
Writing system MISFETQiw, reading system MISFETQ
Each ir is completed.

Next, the interlayer insulating film 10, the connection hole, and the wiring 12
, interlayer insulating film 13, connection hole, wiring 14, final protective film 15
By sequentially forming each of the E shown in FIG.
The PROM version of the microprocessor 20 is completed.

<Mask ROM version> Microprocessor 2
The mask ROM version of No. 0, as shown in FIG. 9 (cross-sectional view of main parts), is similarly constructed of a p- type semiconductor substrate 1, and has a p-type well region 2 and an n-type well region.

The microprocessor 20 is an EPROM 23
Instead, a mask ROM26 is installed, and this mask RO
M26 is a memory cell Qmm as shown on the right side of FIG.
, and a readout MISFETQmr. The mask ROM 26 has a vertical structure (NAND structure) in which a memory cell column in which a plurality of memory cells Qmm are connected in series is arranged between a data line (12) and a source line (9).

The memory cell Qmm basically includes, for example, a memory cell Qmm having an enhancement type threshold voltage corresponding to information 1, and a memory cell Qmm having a depletion type threshold voltage corresponding to information 0 (
There are two types D).

The memory cell Qmm is formed on the main surface of the p-type well region 2 in a region defined and surrounded by an element isolation insulating film 3, and includes a channel forming region, a gate insulating film 4, and a gate electrode 5. , is mainly composed of a pair of n+ type semiconductor regions 9, which are a source region and a drain region. The basic structure of memory cell Qmm (D) is memory cell Q.
Although it is similar to mm, it has an n-type semiconductor region 17 formed in the channel formation region to adjust the threshold voltage.

Memory cell Qmm, memory cell Qmm(D
), since the microprocessor 20 has a one-layer gate structure (single gate structure),
It is formed in the first layer gate material forming step.

Since information is written into the mask ROM 26 during the manufacturing process, the writing system MISFET used for high voltage is basically unnecessary and can be abolished.

The readout MISFET Qmr is composed of a channel forming region, a gate insulating film 4, a gate electrode 5, and a pair of n+ type semiconductor regions 9, which are a source region and a drain region. The gate electrode 5 of this readout system MISFETQmr has a one-layer gate structure.
It is formed in the layered gate material forming process.

Variable peripheral 25 of microprocessor 20
As shown on the left side of Figure 9, the EPROM installed in
It has a memory cell Qie, a write system MISFET Qiw, and a read system MISFET Qir, and is basically an EPR.
It has the same structure as that installed in the OM version microprocessor 20 (the same module or the same circuit unit is used). However, the charge storage gate electrode 5 of the memory cell Qie, the gate electrode 5 of the write system MISFET Qiw, and the gate electrode 5 of the read system MISFET Qir
Since the microprocessor 20 has a one-layer gate structure, each of these is formed in the step of forming the first layer gate material.

Next, a method of manufacturing the above-mentioned microprocessor 20 will be briefly explained using FIGS. 10 to 14 (cross-sectional views of main parts shown for each manufacturing process).

First, like the EPROM version described above, p-
An element isolation insulating film 3 is formed in the p-type well region 2 of the type semiconductor substrate 1, and then, as shown in FIG. 10, a control gate electrode 8 is formed in the region of the memory cell Qie of the EPROM of the variable peripheral device 25. .

Next, as shown in FIG.
In the memory cell array region No. 26, an n-type semiconductor region 17 is formed on the main surface of the p-type well region 2, and the threshold voltage of all memory cells Qmm is set in advance to be a depression type. The n-type semiconductor region 17 is formed using, for example, an ion implantation method.

Next, the memory cell Qm of the mask ROM 26
m(D), readout MISFETQmr, variable peripheral 2
5 EPROM memory cell Qie, write system MISF
A gate insulating film 4 is formed in each region of ETQiw and readout MISFETQir.

Next, as shown in FIG. 12, the memory cell Q
mm (D), read system MISFETQmr, write system M
Gate electrodes 5 of ISFET Qiw and readout MISFET Qir, and charge storage gate electrode 5 of memory cell Qie are formed. The charge storage gate electrode 5 and the gate electrode 5 are each formed of the same gate material, that is, formed in the step of forming the first layer gate material. Further, the patterning process of each of the charge storage gate electrode 5 and the gate electrode 5 is performed by RIE, but the memory cell Qie of the EPROM has a single layer gate structure and is patterned in both the gate width direction and the gate length direction. Moreover, since the memory cell Qmm of the mask ROM 26 is similarly patterned, the etching area is increased and the end point of the etching time can be reliably detected.

Next, as shown in FIG.
Among the 26 memory cells Qmm(D), a p-type semiconductor region 18 is formed in the channel formation region of the memory cell Qmm into which predetermined information is written, and the threshold voltage of this memory cell Qmm is set to an enhancement type. . P-type semiconductor region 18 is formed using an ion implantation method.

Next, as shown in FIG. 14, the memory cell Q
mm, readout MISFETQmr, memory cell Qie
, writing MISFETQiw, reading MISFET
A pair of n+ type semiconductor regions 9 to be used as the source and drain regions of Qir are formed and completed.

Next, by sequentially forming the wirings 12, 14, the final protective film 15, etc., the mask ROM version of the microprocessor 20 shown in FIG. 9 is completed.

As described above, in the method for forming the microprocessor 20 in which two types of nonvolatile memory circuits with different memory capacities are mounted on the same semiconductor substrate 1, the semiconductor substrate 1 is
Equipped with an EPROM 23 in which a field effect transistor employing a two-layer gate structure is used as a memory cell Qme, and an EPROM (25) with a small storage capacity in which a field effect transistor employing a single-layer gate structure is used as a memory cell Qie. In the first step of developing an EPROM version, on the different semiconductor substrate 1, a mask ROM 26, a field effect transistor having a single-layer gate structure as a memory cell Qmm instead of the EPROM 23, and the EPROM (
25) and a second step of developing a mask ROM version containing each of the substantially identical EPROMs (25). With this configuration, the EPROM version of the microprocessor 2
0, the EPROM 23 has a charge storage gate electrode 5
Since the memory cell Qme is a field effect transistor that adopts a two-layer gate structure in which the control gate electrode 7 is laminated on top, the area of the memory cell Qme can be reduced and the capacity can be increased. A memory cell Qie is configured with a field effect transistor adopting a gate structure, and the microprocessor 2 is transferred from the first stage to the second stage.
0 (when developing from the EPROM version to the mask ROM version), a mask ROM 26 was installed in which the memory cell Qmm was a field effect transistor that adopted a single-layer gate structure instead of the EPROM 23, and the memory cell Qmm was The gate structure is the memory cell Qie of the EPROM (25).
In addition, since it is made into a single layer, the number of steps in the manufacturing process can be reduced and the development period of the microprocessor 20 can be shortened.
is installed as is in the second stage, and the development period of the microprocessor 20 can be shortened by the amount corresponding to the design and development of the EPROM (25) in the second stage.

Furthermore, in the second stage microprocessor 20 which is the mask ROM version, the mask ROM 26
, EPROM (25), both memory cells Qmm and Qie are constructed with field effect transistors that adopt a single-layer gate structure, and during the manufacturing process, the etching area during patterning of the gate electrode 5 is increased and the etching time is reduced. Since the end point can be detected reliably, the yield in the manufacturing process can be improved, and since the memory cell Qmm of the mask ROM 26 occupies a smaller area than the memory cell Qme of the EPROM 23, the degree of integration can be improved.

Furthermore, in the second stage microprocessor 20 which is the mask ROM version, the mask ROM 26
The reduction in the number of steps in the manufacturing process based on the single-layer gate structure of the memory cell Qmm of the EPROM (25) and the memory cell Qie of the EPROM (25) and the shortening of the development period can each reduce the development cost.

Furthermore, the mask ROM 2 installed in the second stage microprocessor 20 which is the mask ROM version
6 has a vertical structure in which a memory cell column in which a plurality of memory cells Qmm are connected in series is arranged between a data line (12) and a source line (9). With this configuration, the memory cells Qmm of the vertical structure of the mask ROM 26 have a data line for each of the plurality of memory cells Qmm (for each memory cell column).
Since it is connected to each source line, the number of connections to wiring can be reduced and the degree of integration can be improved.

[0085] As described above, the invention made by the present inventor is as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, it goes without saying that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the gist thereof.

For example, in the present invention, the mask ROM 26 of the mask ROM version of the microprocessor 20 may be configured in a horizontal structure (NOR structure) in which the memory cells Qmm are connected in parallel between the data line and the source line. good. in this case,
In the horizontally structured memory cell Qmm, the area of the isolation region between the memory cells Qmm is reduced by an amount corresponding to the separation dimension in the gate width direction of the charge storage gate electrode 5 of the field effect transistor, which is the memory cell Qme of the EPROM 23. Therefore, the degree of integration can be improved.

The present invention also provides an EPROM version of the microprocessor 20, in which the EPROM 23, the EPROM
(25) into an EEPROM (Electric
ally Erasable Programmable
e Read Only Memory).

Furthermore, the present invention is not limited to microprocessors, but can be applied to semiconductor integrated circuit devices such as logic LSIs that employ a gate array method, a custom method, or the like.

[0089]

Effects of the Invention A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device in which two types of nonvolatile memory circuits are mounted on the same substrate, the development period when changing the nonvolatile memory circuit can be shortened.

In a semiconductor integrated circuit device in which two types of nonvolatile memory circuits are mounted on the same substrate, the development period when changing the nonvolatile memory circuit can be shortened, and the number of steps in the manufacturing process can be reduced.

In a semiconductor integrated circuit device in which two types of nonvolatile memory circuits are mounted on the same substrate, the yield in the manufacturing process can be improved.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram of an EPROM version of a microprocessor that is an embodiment of the present invention.

FIG. 2 is a layout diagram of a mask ROM version of the microprocessor.

FIG. 3 is a sectional view of essential parts of the microprocessor (EPROM version).

FIG. 4 is a sectional view of a main part in a first step in the manufacturing process of the microprocessor.

FIG. 5 is a sectional view of main parts in a second step.

FIG. 6 is a sectional view of main parts in the third step.

FIG. 7 is a sectional view of main parts in the fourth step.

FIG. 8 is a sectional view of main parts in the fifth step.

FIG. 9 is a sectional view of essential parts of a mask ROM version of the microprocessor.

FIG. 10 is a sectional view of a main part in a first step in the manufacturing process of the microprocessor.

FIG. 11 is a sectional view of main parts in a second step.

FIG. 12 is a sectional view of main parts in the third step.

FIG. 13 is a sectional view of main parts in the fourth step.

FIG. 14 is a sectional view of main parts in the fifth step.

[Explanation of symbols]

20...Microprocessor, 22...CPU, 23...EP
ROM, 24... Interrupt controller circuit, 25... Variable peripheral, 26... Mask ROM, 21... I/O port, 1...
Semiconductor substrate, 2... well region, 4, 6... gate insulating film,
5, 7... Gate electrode, 9... Semiconductor region, 12, 14... Wiring, Qme, Qmm, Qie... Memory cell, Qmw, Q
mr, Qiw, Qir...MISFET.

Claims (3)

[Claims] 1. A method for forming a semiconductor integrated circuit device in which two types of nonvolatile memory circuits with different storage capacities are mounted on the same substrate, in which a field effect transistor adopting a two-layer gate structure is mounted on a first substrate as a memory cell. A first nonvolatile memory circuit of an ultraviolet erasable type or an electrically erasable type, the memory cell of which is a field effect transistor that adopts a single-layer gate structure, the memory capacity of which is smaller than that of the first nonvolatile memory circuit; a first stage in which a second nonvolatile memory circuit of an erasable type or an electrically erasable type is mounted, and a second substrate different from the first substrate, in place of the first nonvolatile memory circuit;
a third read-only nonvolatile memory circuit whose memory cells are field-effect transistors that employ a single-layer gate structure;
A method for forming a semiconductor integrated circuit device, comprising: a second step of mounting each of said second nonvolatile memory circuits and substantially the same second nonvolatile memory circuits. 2. The third non-volatile memory circuit mounted on the second stage semiconductor integrated circuit device includes a memory cell column in which a plurality of memory cells are connected in series between a data line and a source line. 2. The method of forming a semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a vertical structure or a horizontal structure in which memory cells are connected in parallel between a data line and a source line. 3. The semiconductor integrated circuit device is a microprocessor equipped with a nonvolatile memory circuit, and the first
Both the first non-volatile memory circuit in the first stage and the third non-volatile memory circuit in the second stage are used as memory circuits for storing programs, and the second non-volatile memory circuit is used in both the first stage and the second stage. 3. The method of forming a semiconductor integrated circuit device according to claim 1, wherein the method is used as a memory circuit for trimming an internal circuit.