JPH04276632A - Substrate for semiconductor epitaxial growth use - Google Patents

Abstract

PURPOSE:To prevent the propagation of a penetrating transition inside a semiconductor crystal layer by a method wherein a CdTe crystal layer whose lattice constant is different is formed on a GaAs substrate as a buffer layer and strain superlattice layers in which crystal layers whose prescribed lattice constant is different from each other have been laminated alternately are formed on it. CONSTITUTION:Strain superlattice layers 4 are formed on a buffer layer 3 by a CdTe crystal layer having a proper thickness. Intermediate layers 12 by CdTe crystal layers are inserted between the strain superlattice layers 4 in which five layers of ZnTe crystal layers 9 and CdTe crystal layers 2 have been formed alternately. A CdTe crystal layer having a proper thickness is formed as a top layer 5 on the uppermost layer of a substrate for semiconductor epitaxial growth use. At this structure, one strain superlattice layer out of the strain superlattice layers 4 which are formed of at least two or more layers must be formed in a position at 1.5mum or higher from the boundary face between the GaAs substrate 1 and the buffer layer 3 by the CdTe crystal layer.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for semiconductor epitaxial growth, in which a semiconductor crystal layer having a lattice constant different from that of the substrate is epitaxially grown on a semiconductor substrate.

[0002] In recent years, when trying to obtain a large-area substrate, for example, as a method for forming a substrate of cadmium tellurium (CdTe), where it is difficult to obtain a high-quality, large-area substrate with good crystallinity, Gallium arsenide (Ga
A method is adopted in which a CdTe crystal layer is formed on an As) substrate by epitaxial growth.

By this method, for example, mercury, cadmium, tellurium (Hg1-x
CdTe or cadmium-zinc-tellurium (Cd y Zn1-y Te) is grown on a GaAs substrate as a substrate for epitaxial growth of Cdx Te) crystal.
A semiconductor epitaxial growth substrate on which crystals are epitaxially grown is used.

0004

[Prior Art] The above-mentioned semiconductor epitaxial growth substrate is manufactured by molecular beam epitaxial growth (Molecular Beam Epitaxial Growth).
Beam Epitaxy (MBE) method or metal organic chemical vapor phase epitaxy (Metal Organic Chemistry) method.
Mical Vapor Deposition;MO
As shown in FIG. 5, a CdTe crystal layer 2 of a predetermined thickness is grown on a GaAs substrate 1 by the method described above.

[0005]

Problems to be Solved by the Invention The lattice constant of the GaAs substrate described above is 5.653 Å, and the lattice constant of the CdTe crystal layer is 6.481 Å.
481-5.653)/5.653×100 =14.
There is a large lattice mismatch with a value of 6%, and a large number of crystal defects occur in the epitaxially grown CdTe crystal layer. In particular, GaAs substrates and epitaxially grown CdT
A kind of threading dislocation, which is a crystal defect generated at the interface of the e-crystal layer, propagates through the epitaxially grown CdTe crystal layer and reaches the vicinity of the surface of the CdTe crystal layer.

[0006] On a substrate for semiconductor epitaxial growth containing many crystal defects, Hg1-x Cdx Te
When a semiconductor crystal layer is epitaxially grown and used to form a semiconductor element such as an infrared sensing element, dislocations propagate to the Hg1-x Cdx Te crystal layer and the electrical Only bad characteristics can be obtained.

[0007] In order to solve this problem, Japanese Patent Laid-Open No. 1-1
No. 58719 describes a strain absorption method in which a strained superlattice layer and an intermediate layer are crystal-grown on a semi-insulating compound semiconductor substrate to give physical properties close to amorphous, so that misfit dislocations can be absorbed by these layers. a buffer layer formed on the substrate and a stress relaxation layer that relieves stress of the strain absorption layer;
A compound semiconductor device has been proposed in which a crystal is formed with a dislocation trap layer that traps dislocations propagating from the substrate, but the structure is complicated, and a stress relaxation layer and a stress relaxation layer are required in place of the strain absorption layer. Manufacturing is not easy as the growth temperature of the dislocation trap layer is different. An object of the present invention is to provide a substrate for semiconductor epitaxial growth, which prevents the propagation of threading dislocations within a semiconductor crystal layer epitaxially grown on a semiconductor substrate, and reduces the dislocation density near the surface of the crystal layer.

[0008]

[Means for Solving the Problems] As shown in FIGS. 1(a) and 1(b), the semiconductor epitaxial substrate of the present invention includes a gallium arsenide crystal layer epitaxially grown on a gallium arsenide substrate 1 or an insulating substrate. A compound semiconductor crystal layer containing cadmium is provided thereon as a buffer layer 3,
On the buffer layer 3, a strained superlattice layer 4 composed of a cadmium tellurium crystal layer 2 and a zinc tellurium crystal layer 9, or a cadmium tellurium crystal layer 2 and a compound semiconductor crystal layer of zinc, cadmium, and tellurium is placed between the substrate 1 and the buffer layer 3. interface with layer 3,
Or 1.5 from the interface between the gallium arsenide crystal layer epitaxially grown on the insulating substrate and the buffer layer 3.
Provided at a distance of µm or more.

Alternatively, a compound semiconductor crystal layer containing cadmium is provided as a buffer layer 3 on a gallium arsenide substrate 1 or a gallium arsenide crystal layer epitaxially grown on an insulating substrate, and a cadmium telluride crystal layer 2 and a cadmium tellurium crystal layer 2 are formed on the buffer layer 3. At least two or more strained superlattice layers 4 composed of a zinc-tellurium crystal layer 9 or a cadmium-tellurium crystal layer and a compound semiconductor crystal layer of zinc, cadmium, and tellurium with an intermediate layer 12 of a compound semiconductor crystal layer containing tellurium in between. At least one of the strained superlattice layers 4 is located at a distance of 1.5 μm or more from the interface between the substrate 1 and the buffer layer 2, and a compound semiconductor crystal layer containing tellurium is provided as the top layer 5. It is characterized by: Further, the thickness of the zinc tellurium crystal layer 9 constituting the strained superlattice layer 4 is 3 to 19
Å.

0010

[Operation] As shown in FIG. 4, a CdTe crystal layer having a different lattice constant from that of the GaAs substrate 1 is provided as a buffer layer 3 on, for example, a GaAs substrate 1.
When a strained superlattice layer 4 is provided in which crystal layers having different lattice constants are alternately laminated, such as a CdTe crystal layer of 10 Å and a ZnTe crystal layer of 10 Å,
When there is no strained superlattice layer as in the conventional case, the threading dislocations 6 that have reached the surface of the top layer 5 of the CdTe crystal layer, as shown by the dotted line, become distorted in the strained superlattice layer as shown by the solid line. The dislocations bend along the layer 4 or at the interface between the strained superlattice layer 4 and the buffer layer 3 like dislocations 7 and 8, interact with each other and disappear, and the propagation of the dislocations is blocked.

In the present invention, in order to further enhance this effect, a structure as shown in FIG. 1(a) is adopted. Two or more strained superlattice layers 4 are provided between the buffer layer 3 and the top layer 5 in order to enhance the dislocation reduction effect. Each strained superlattice layer 4 is
As shown in FIG. 1(b), for example, the structure is such that five or more 10 Å ZnTe crystal layers 9 and 500 Å CdTe crystal layers 2 are grown alternately.

This strained superlattice layer 4 is made of CdTe with an appropriate thickness.
It is provided on the buffer layer 3 of the crystal layer. Further, an intermediate layer 12 of CdTe crystal layers is inserted between the strained superlattice layer 4 in which five ZnTe crystal layers 9 and five CdTe crystal layers 2 are alternately provided. Further, a CdTe crystal layer of an appropriate thickness is provided as a top layer 5 on the uppermost layer of this substrate for semiconductor epitaxial growth. In this structure, as can be seen from FIGS. 2 and 3, at least one of the two or more strained superlattice layers 4 is formed between the GaAs substrate 1 and the CdT
It is necessary to provide it at a position of 1.5 μm or more from the interface of the buffer layer 3 of the e-crystal layer.

The reason for this will be explained. 2(a) shows the case where the CdTe crystal layer 2 is provided on the GaAs substrate 1 without providing a strained superlattice layer, and FIG. 2(b) shows the case where the CdTe crystal layer 2 is provided on the GaAs substrate 1.
When a dTe crystal layer is provided as a buffer layer 3 with a thickness of 1.5 μm or more, one strained superlattice layer 4 is provided, and a CdTe crystal layer is provided as a top layer 5 on top of the strained superlattice layer 4, as shown in FIG.
In c), a CdTe crystal layer is provided as a buffer layer on a GaAs substrate 1 with a thickness of 1.5 μm or less, and a strained superlattice layer 4, an intermediate layer 12 of CdTe crystal layers, and a strained superlattice layer 4 are formed thereon. This is a case where the top layer 5 is provided on top of the top layer 5.

FIG. 2(d) shows Cd on the GaAs substrate 1.
A Te crystal layer is provided as a buffer layer 3 with a thickness of 1.5 μm or less, and on top of that a strained superlattice layer 4 and an intermediate layer 12 of CdTe crystal layers; , a strained superlattice layer 4 is provided, and a top layer 5 is provided thereon.
This is the case when .

FIG. 2(e) shows Cd on the GaAs substrate 1.
A Te crystal layer is provided as a buffer layer 3 with a thickness of 1.5 μm or less, and on top of that a strained superlattice layer 4 and an intermediate layer 12 of CdTe crystal layers; , strained superlattice layer 4 , intermediate layer 1 of CdTe crystal layer
This is a case in which a strained superlattice layer 2 and a strained superlattice layer 4 are provided, and a top layer 5 is provided thereon.

Comparing FIG. 2(a) and FIG. 2(b),
As shown in FIG. 2(a), when the CdTe crystal layer 2 is directly formed on the GaAs substrate 1 without providing the strained superlattice layer 4,
The dislocations in the CdTe crystal layer 2 are 3.4 × 108/cm2 to 4.0 × 1 as shown at point A of the curve 21 in FIG.
It was 0.08/cm2.

FIG. 3 is a diagram showing the relationship between the number of stacked strained superlattice layers and the dislocation density of the top layer. By the way, as shown in FIG. 2(b), GaAs is formed between the buffer layer 3 of the CdTe crystal layer and the top layer 5 of the CdTe crystal layer on the GaAs substrate 1.
In the structure in which the strained superlattice layer 4 is provided at a location 1.5 μm or more from the interface between the substrate 1 and the buffer layer 3, the dislocation density of the CdTe crystal layer of the top layer 5 is as shown at point B in FIG. 3
．． It has decreased to 0 × 108/cm2.

Furthermore, when comparing FIG. 2(b) and FIG. 2(c), as shown in FIG. 2(c), CdTe is deposited on the GaAs substrate 1.
A crystalline buffer layer 3 is formed, and a first strained superlattice layer 4-1 is provided within 1.5 μm from the interface between the GaAs substrate 1 and the buffer layer 3. Then, a CdTe intermediate layer 12 is provided thereon, and a second strained superlattice layer 4-2 is formed at a location 1.5 μm or more from the interface between the GaAs substrate 1 and the buffer layer 3.
As shown in points B and C in Figure 3, the dislocation density in the top layer hardly changes when the first strained superlattice layer is provided within 1.5 μm from the substrate surface. 4-1
It can be seen that this does not contribute to reducing dislocations in the CdTe crystal layer of the top layer 5.

Comparing FIG. 2(c) and FIG. 2(d), it is found that a buffer layer 3 of a CdTe crystal layer is formed on the surface of the GaAs substrate 1, and as shown in FIG. A first strained superlattice layer 4-1 is provided within 1.5 μm, an intermediate layer 12 of a CdTe crystal layer is provided thereon, and a second strained superlattice layer is provided at a location 1.5 μm or more from the substrate surface. When the layer 4-2 and the third strained superlattice layer 4-3 are provided, the dislocation density of the top layer 5 formed as the uppermost layer is 2 × 108/cm2 compared to the case of FIG. 2(c). This means that the number of strained superlattice layers 4-2 and 4-3 that are provided at locations 1.5 μm or more above the substrate surface increases the thickness of the top layer 5 formed on the top layer. It can be seen that the number of dislocations in the CdTe crystal layer is reduced.

[0020] This thickness of 1.5 μm is Ga
This thickness is necessary to sufficiently alleviate residual stress caused by lattice mismatch between the As substrate 1 and the buffer layer of the CdTe crystal layer formed thereon.

If the residual stress in the buffer layer of this CdTe crystal layer is large, the effect of stress in the strained superlattice layer to eliminate dislocations will not work effectively, and the above-mentioned effect of bending threading dislocations will not work effectively. become weak. If this condition is satisfied, the thickness of each crystal layer formed on the buffer layer will be Zn
There are no limitations except for the thickness of the Te crystal layer.

The lower limit of the thickness of the ZnTe crystal layer constituting the strained superlattice layer is Z calculated from the lattice constant of the ZnTe crystal layer.
The upper limit of the ZnTe crystal layer is determined by the thickness of one molecular layer of nTe, and the upper limit of the ZnTe crystal layer is such that when a strained superlattice layer is formed by a ZnTe crystal layer and a CdTe crystal layer, the ZnTe crystal layer does not generate lattice misalignment dislocations. This is an experimentally obtained value for staying within the elastic limit, and for this reason it is desirable that the thickness of the ZnTe crystal layer be between 3 and 19 Å.

Furthermore, in order to form each crystal layer by the MOCVD method or MBE method described above, it is necessary to form the CdTe layer of the superlattice layer.
The thickness of the layer is 500 Å, the CdTe buffer layer and the CdTe top layer are about 1.5 μm, and the CdTe middle layer is 3000 Å.
is practical.

[0024]

[Examples] Hereinafter, examples of the present invention will be explained using the drawings.
This will be explained in detail while comparing with a conventional example.

As shown in FIG. 2(e), the substrate for semiconductor epitaxial growth of the present invention has carbon on a GaAs substrate 1.
A buffer layer 3 made of a dTe crystal layer was formed to a thickness of 1.6 μm using a hot wall epitaxial growth method.

[0026] Next, a 10 Å thick ZnTe layer is placed on top of it.
Crystal layers 9 and a first strained superlattice layer 4-1 in which five CdTe crystal layers 2 each having a thickness of 500 Å are formed alternately are formed by the hot wall epitaxial growth method described above.

In order to form a CdTe crystal layer or a ZnTe crystal layer by the hot wall epitaxial growth method as described above, the GaAs substrate is placed on a rotatable substrate mounting stand equipped with a heater (not shown), and the substrate is Place in a high vacuum container. Then, a heater is provided in the container and a source crucible filled with CdTe alloy and ZnTe alloy is provided, and the GaAs substrate is placed on this predetermined crucible while being heated and rotated, and is maintained for a predetermined period of time. good.

Next, the first strained superlattice layer 4-1 described above
An intermediate layer 12 made of a CdTe crystal layer having a thickness of 3000 Å is formed thereon by the hot wall epitaxial growth method described above. Next, the first strained superlattice layer 4-1 described above
The second strained superlattice layer 4-2, the third strained superlattice layer 4-3, and the fourth strained superlattice layer 4-4 having the same structure as described above with the intermediate layer 12 interposed therebetween. Formed by hot wall epitaxial growth method.

A top layer 5 having a thickness of 1.5 μm and consisting of a CdTe crystal layer is formed on the uppermost layer by the hot wall epitaxial growth method described above. A good CdTe crystal was obtained in which the dislocation density of the top layer 5 made of the CdTe crystal layer formed in this way was reduced to 2×10 8 /cm 2 as shown at point E in FIG.

[0030] Furthermore, the crystal pieces formed in this manner are polished,
When the surface of the longitudinal section was observed with a transmission electron microscope, it was found that the dislocations extending from the GaAs substrate 1 penetrate through the strained superlattice layer 4 formed within 1.5 μm from the top of the substrate, as shown in FIG. However, the distance is 1.5 μm from the top of the substrate.
It has been observed that the strain disappears at the interface between the strained superlattice layer 4 and the buffer layer 3, which is far away.

In this example, a CdTe crystal layer was used for the intermediate layer, but other materials such as cadmium, zinc, tellurium [C
dy Zn1-y Te (0 < y < 1)] crystal layer may be used, and the ZnTe crystal layer forming the strained superlattice layer may be replaced with cadmium-zinc-tellurium [Cdx Zn1-x T
e(0<x<1)] crystal layer may be used.

Further, instead of the GaAs substrate, a GaAs crystal layer may be epitaxially grown on an insulating substrate such as silicon.

[0033]

As described above, according to the semiconductor epitaxial growth substrate of the present invention, the propagation of threading dislocations in the CdTe crystal layer grown on the GaAs substrate is effectively prevented, resulting in a high quality product with low dislocation density. If a Hg1-x Cdx Te crystal layer is epitaxially grown on the substrate and an infrared sensing element is formed using this Hg1-x Cdx Te crystal layer, an element with good electrical characteristics can be obtained. There are benefits to be gained.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a substrate for semiconductor epitaxial growth of the present invention.

FIG. 2 is a sectional view showing an embodiment of the present invention.

FIG. 3 is a diagram showing the relationship between the number of stacked strained superlattice layers and dislocation density in the substrate of the present invention.

FIG. 4 is an explanatory diagram of dislocation annihilation in forming a substrate according to the present invention.

FIG. 5 is a cross-sectional view of a conventional semiconductor epitaxial growth substrate.

[Explanation of symbols]

1 GaAs substrate 2 CdTe crystal layer 3 Buffer layer 4, 4-1, 4-2, 4-3, 4-4 Strained superlattice layer 5
Top layer 6, 7, 8 Threading dislocation 9 ZnTe crystal layer 12 Intermediate layer

Claims (3)

[Claims] 1. A compound semiconductor crystal layer containing cadmium is provided as a buffer layer (3) on a gallium arsenide substrate (1) or a gallium arsenide crystal layer epitaxially grown on an insulating substrate, and a cadmium telluride layer is provided on the buffer layer. A strained superlattice layer (4) composed of a crystal layer (2) and a zinc-tellurium crystal layer (9), or a cadmium-tellurium crystal layer and a compound semiconductor crystal layer of zinc, cadmium, and tellurium.
, the buffer layer (3) and the gallium arsenide substrate (1
), or provided at a position 1.5 μm or more away from the interface with the gallium arsenide crystal layer formed on the insulating substrate, and a compound semiconductor crystal layer containing tellurium is provided as the top layer (5) as the top layer. A substrate for semiconductor epitaxial growth characterized by: 2. A compound semiconductor crystal layer containing cadmium is provided as a buffer layer (3) on a gallium arsenide substrate (1) or a gallium arsenide crystal layer epitaxially grown on an insulating substrate, and a cadmium telluride layer is provided on the buffer layer. A strained superlattice layer (4) composed of a crystal layer (2) and a zinc-tellurium crystal layer (9), or a cadmium-tellurium crystal layer and a compound semiconductor crystal layer of zinc, cadmium, and tellurium.
, an intermediate layer of compound semiconductor crystal layers containing cadmium (
12), and at least one of the strained superlattice layers (4) is formed between the substrate (1) and the buffer layer (3).
1. A substrate for semiconductor epitaxial growth, characterized in that the top layer (5) is located at a distance of 1.5 μm or more from the interface between the semiconductor epitaxial growth substrate and the compound semiconductor crystal layer containing tellurium as the top layer. 3. The substrate for semiconductor epitaxial growth according to claim 1, wherein the zinc tellurium crystal layer (9) constituting the strained superlattice layer (4) has a thickness of 3 to 19 Å.